// Add on the data abort specific fields to the generic abort ISS value
val = AbortFault<DataAbort>::iss();
+
+ val |= cm << 8;
+
// ISS is valid if not caused by a stage 1 page table walk, and when taken
// to AArch64 only when directed to EL2
if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
isv = true;
ar = val;
break;
+ case CM:
+ cm = val;
+ break;
// Just ignore unknown ID's
default:
break;
SAS, // DataAbort: Syndrome Access Size
SSE, // DataAbort: Syndrome Sign Extend
SRT, // DataAbort: Syndrome Register Transfer
+ CM, // DataAbort: Cache Maintenance/Address Translation Op
// AArch64 only
SF, // DataAbort: width of the accessed register is SixtyFour
uint8_t sas;
uint8_t sse;
uint8_t srt;
+ uint8_t cm;
// AArch64 only
bool sf;
bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) :
AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2,
_tranMethod),
- isv(false), sas (0), sse(0), srt(0), sf(false), ar(false)
+ isv(false), sas (0), sse(0), srt(0), cm(0), sf(false), ar(false)
{}
ExceptionClass ec(ThreadContext *tc) const override;