Update Makefile.synth after Paul's patches

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/Makefile.synth b/Makefile.synth
index 1e1253746646a34cd44b56f2aca04ec18502a70b..ee6017a91e931ee2c887fa89dacae40f666b257e 100644 (file)
--- a/Makefile.synth
+++ b/Makefile.synth
@@ -42,17 +42,18 @@ NEXTPNR_FLAGS=--um5g-85k --freq 12
 OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 
-VHDL_FILES  = wishbone_types.vhdl utils.vhdl fpga/main_bram.vhdl
-VHDL_FILES += wishbone_bram_wrapper.vhdl decode_types.vhdl common.vhdl
-VHDL_FILES += fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd wishbone_arbiter.vhdl
-VHDL_FILES += dmi_dtm_dummy.vhdl wishbone_debug_master.vhdl helpers.vhdl
-VHDL_FILES += loadstore1.vhdl crhelpers.vhdl writeback.vhdl ppc_fx_insns.vhdl
-VHDL_FILES += countzero.vhdl insn_helpers.vhdl rotator.vhdl logical.vhdl
-VHDL_FILES += execute1.vhdl fetch1.vhdl gpr_hazard.vhdl cr_hazard.vhdl
-VHDL_FILES += control.vhdl decode2.vhdl cr_file.vhdl cache_ram.vhdl plru.vhdl
-VHDL_FILES += dcache.vhdl core_debug.vhdl multiply.vhdl icache.vhdl fetch2.vhdl
-VHDL_FILES += register_file.vhdl decode1.vhdl divider.vhdl core.vhdl soc.vhdl
-VHDL_FILES += fpga/soc_reset.vhdl fpga/clk_gen_bypass.vhd fpga/toplevel.vhdl
+VHDL_FILES  = fpga/soc_reset.vhdl fpga/clk_gen_bypass.vhd decode_types.vhdl
+VHDL_FILES += common.vhdl wishbone_types.vhdl wishbone_debug_master.vhdl
+VHDL_FILES += wishbone_arbiter.vhdl cache_ram.vhdl utils.vhdl plru.vhdl
+VHDL_FILES += helpers.vhdl dcache.vhdl core_debug.vhdl fetch1.vhdl fetch2.vhdl
+VHDL_FILES += register_file.vhdl insn_helpers.vhdl multiply.vhdl divider.vhdl
+VHDL_FILES += logical.vhdl crhelpers.vhdl countzero.vhdl rotator.vhdl
+VHDL_FILES += ppc_fx_insns.vhdl execute1.vhdl decode1.vhdl cr_file.vhdl
+VHDL_FILES += writeback.vhdl loadstore1.vhdl icache.vhdl cr_hazard.vhdl
+VHDL_FILES += gpr_hazard.vhdl control.vhdl decode2.vhdl core.vhdl
+VHDL_FILES += fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd dmi_dtm_dummy.vhdl
+VHDL_FILES += fpga/main_bram.vhdl wishbone_bram_wrapper.vhdl soc.vhdl
+VHDL_FILES += fpga/toplevel.vhdl
 
 all: microwatt.bit