Reflect changes in the tester behaviour.
---------- Begin Simulation Statistics ----------
-sim_seconds 0.010101 # Number of seconds simulated
-sim_ticks 10100518 # Number of ticks simulated
-final_tick 10100518 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.010140 # Number of seconds simulated
+sim_ticks 10139920 # Number of ticks simulated
+final_tick 10139920 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 129349 # Simulator tick rate (ticks/s)
-host_mem_usage 663928 # Number of bytes of host memory used
-host_seconds 78.09 # Real time elapsed on the host
+host_tick_rate 145167 # Simulator tick rate (ticks/s)
+host_mem_usage 481408 # Number of bytes of host memory used
+host_seconds 69.85 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39550848 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 39550848 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14145024 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 14145024 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 617982 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 617982 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 221016 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 221016 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 3915724718 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 3915724718 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1400425602 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1400425602 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 5316150320 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 5316150320 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 617983 # Number of read requests accepted
-system.mem_ctrls.writeReqs 221016 # Number of write requests accepted
-system.mem_ctrls.readBursts 617983 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 221016 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 39163072 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 387840 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 14016640 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 39550912 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 14145024 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 6060 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 1978 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39722368 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 39722368 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14274816 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 14274816 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 620662 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 620662 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 223044 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 223044 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 3917424201 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 3917424201 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1407783888 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1407783888 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 5325208088 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 5325208088 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 620666 # Number of read requests accepted
+system.mem_ctrls.writeReqs 223044 # Number of write requests accepted
+system.mem_ctrls.readBursts 620666 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 223044 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 39325760 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 396864 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 14138944 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 39722624 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 14274816 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 6201 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 2091 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 76629 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 76171 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 76824 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 76474 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 76756 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 76802 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 76225 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 76042 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 76321 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 76908 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 76950 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 77228 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 77214 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 76769 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6 76576 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 76499 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 27421 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 27227 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 27422 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 27319 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 27412 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 27477 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 27095 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 27637 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 27303 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 27584 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 27647 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 27851 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 27807 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 27671 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6 27568 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 27490 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 10100475 # Total gap between requests
+system.mem_ctrls.totGap 10139879 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 617983 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 620666 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 221016 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 34398 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 67691 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 107083 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 135966 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 123386 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 83518 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 43655 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 16226 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 223044 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 34202 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 67883 # What read queue length does an incoming req see
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+system.mem_ctrls.rdQLenPdf::3 137013 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::4 123761 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::5 83967 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::6 43765 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::7 16432 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 36 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 118 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 1783 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 5370 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 9528 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 12721 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 14465 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 15565 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 15821 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 16096 # What write queue length does an incoming req see
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-system.mem_ctrls.wrQLenPdf::26 15412 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 15030 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 14722 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 14673 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 14636 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 14779 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 15223 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 4310 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::34 1845 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::35 727 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::36 255 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::37 87 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::38 26 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::39 12 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::17 1701 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::28 14842 # What write queue length does an incoming req see
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+system.mem_ctrls.wrQLenPdf::36 311 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::37 122 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::38 61 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::39 14 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::40 3 # What write queue length does an incoming req see
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system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 332523 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 159.925611 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 125.830358 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 125.889032 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 135463 40.74% 40.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 125752 37.82% 78.56% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 43770 13.16% 91.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 17448 5.25% 96.97% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 6543 1.97% 98.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 2325 0.70% 99.63% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 803 0.24% 99.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 286 0.09% 99.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 133 0.04% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 332523 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 13671 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 44.758833 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 43.734391 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 9.598616 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-19 10 0.07% 0.07% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-23 51 0.37% 0.45% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-27 237 1.73% 2.18% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::28-31 592 4.33% 6.51% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-35 1395 10.20% 16.71% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-39 1956 14.31% 31.02% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-43 2298 16.81% 47.83% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::44-47 2196 16.06% 63.89% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-51 1787 13.07% 76.97% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::52-55 1319 9.65% 86.61% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-59 876 6.41% 93.02% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::60-63 474 3.47% 96.49% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-67 243 1.78% 98.27% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::68-71 135 0.99% 99.25% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-75 62 0.45% 99.71% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::76-79 22 0.16% 99.87% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-83 13 0.10% 99.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::84-87 3 0.02% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::92-95 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::104-107 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 13671 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 13671 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.020042 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.018590 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.229581 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 13535 99.01% 99.01% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 53 0.39% 99.39% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 50 0.37% 99.76% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 20 0.15% 99.90% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 6 0.04% 99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 5 0.04% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 2 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 13671 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 28940521 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 40567058 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3059615 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 47.29 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 335053 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 159.568976 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 125.655089 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 125.561192 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 136625 40.78% 40.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 126781 37.84% 78.62% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 44480 13.28% 91.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 17048 5.09% 96.98% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 6525 1.95% 98.93% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 2297 0.69% 99.61% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 855 0.26% 99.87% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 301 0.09% 99.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 141 0.04% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 335053 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 13793 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 44.545857 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 43.515478 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 9.590118 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-19 13 0.09% 0.09% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::20-23 63 0.46% 0.55% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-27 253 1.83% 2.39% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::28-31 644 4.67% 7.05% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::32-35 1374 9.96% 17.02% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::36-39 2023 14.67% 31.68% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::40-43 2256 16.36% 48.04% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::44-47 2260 16.39% 64.42% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::48-51 1885 13.67% 78.09% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::52-55 1286 9.32% 87.41% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::56-59 772 5.60% 93.01% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::60-63 480 3.48% 96.49% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-67 280 2.03% 98.52% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::68-71 112 0.81% 99.33% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::72-75 40 0.29% 99.62% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::76-79 38 0.28% 99.90% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-83 9 0.07% 99.96% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::84-87 2 0.01% 99.98% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::88-91 2 0.01% 99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::112-115 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 13793 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 13793 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.016893 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.015738 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.203483 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 13672 99.12% 99.12% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 53 0.38% 99.51% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 36 0.26% 99.77% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 22 0.16% 99.93% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20 9 0.07% 99.99% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 13793 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 29132870 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 40807705 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3072325 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 47.41 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 66.29 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 3877.33 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1387.71 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 3915.73 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1400.43 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 66.41 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 3878.31 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 1394.38 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 3917.45 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1407.78 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 41.13 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 30.29 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 10.84 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 5.49 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 26.46 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 285611 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 212791 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 46.67 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 97.15 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 12.04 # Average gap between requests
-system.mem_ctrls.pageHitRate 59.98 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 2513405160 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 1396336200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7635376320 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 2270198016 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 659602320 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 6882629616 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 21843000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 21379390632 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 2117.037761 # Core power per rank (mW)
+system.mem_ctrls.busUtil 41.19 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 30.30 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 10.89 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 5.50 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 26.47 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 285829 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 214496 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 46.52 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 97.08 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 12.02 # Average gap between requests
+system.mem_ctrls.pageHitRate 59.89 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 2532486600 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 1406937000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7666913280 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 2290011264 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 662145120 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 6909126408 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 21943800 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 21489563472 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 2119.780745 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 20 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 337220 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 338520 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 9761503 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 9799109 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 659602320 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 218238408 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 5867775600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 6745616328 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.969575 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 9761482 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 337220 # Time in different power states
+system.mem_ctrls_1.refreshEnergy 662145120 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 219079728 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 5890395600 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 6771620448 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 667.969581 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 9799112 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 338520 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.num_reads 98577 # number of read accesses completed
-system.cpu0.num_writes 54699 # number of write accesses completed
-system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 98994 # number of read accesses completed
-system.cpu1.num_writes 54402 # number of write accesses completed
-system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 99663 # number of read accesses completed
-system.cpu2.num_writes 54801 # number of write accesses completed
-system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 99192 # number of read accesses completed
-system.cpu3.num_writes 55310 # number of write accesses completed
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 100000 # number of read accesses completed
-system.cpu4.num_writes 55358 # number of write accesses completed
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 99170 # number of read accesses completed
-system.cpu5.num_writes 54755 # number of write accesses completed
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 99605 # number of read accesses completed
-system.cpu6.num_writes 54887 # number of write accesses completed
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 99434 # number of read accesses completed
-system.cpu7.num_writes 55034 # number of write accesses completed
-system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 99636 # number of read accesses completed
+system.cpu0.num_writes 55756 # number of write accesses completed
+system.cpu1.num_reads 99812 # number of read accesses completed
+system.cpu1.num_writes 55738 # number of write accesses completed
+system.cpu2.num_reads 99728 # number of read accesses completed
+system.cpu2.num_writes 55111 # number of write accesses completed
+system.cpu3.num_reads 99867 # number of read accesses completed
+system.cpu3.num_writes 55484 # number of write accesses completed
+system.cpu4.num_reads 99170 # number of read accesses completed
+system.cpu4.num_writes 55261 # number of write accesses completed
+system.cpu5.num_reads 100000 # number of read accesses completed
+system.cpu5.num_writes 55396 # number of write accesses completed
+system.cpu6.num_reads 99231 # number of read accesses completed
+system.cpu6.num_writes 55296 # number of write accesses completed
+system.cpu7.num_reads 99263 # number of read accesses completed
+system.cpu7.num_writes 55610 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 2048 # delay histogram for all message
system.ruby.delayHist::max_bucket 20479 # delay histogram for all message
-system.ruby.delayHist::samples 4971796 # delay histogram for all message
-system.ruby.delayHist::mean 200.857627 # delay histogram for all message
-system.ruby.delayHist::stdev 577.801677 # delay histogram for all message
-system.ruby.delayHist | 4834086 97.23% 97.23% | 131198 2.64% 99.87% | 6246 0.13% 99.99% | 255 0.01% 100.00% | 8 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 4971796 # delay histogram for all message
+system.ruby.delayHist::samples 4993549 # delay histogram for all message
+system.ruby.delayHist::mean 200.268799 # delay histogram for all message
+system.ruby.delayHist::stdev 576.702096 # delay histogram for all message
+system.ruby.delayHist | 4855621 97.24% 97.24% | 131487 2.63% 99.87% | 6055 0.12% 99.99% | 370 0.01% 100.00% | 13 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 4993549 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 623814
-system.ruby.outstanding_req_hist::mean 15.998459
-system.ruby.outstanding_req_hist::gmean 15.997190
-system.ruby.outstanding_req_hist::stdev 0.126101
-system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 17 0.00% 0.02% | 623693 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 623814
+system.ruby.outstanding_req_hist::samples 626470
+system.ruby.outstanding_req_hist::mean 15.998466
+system.ruby.outstanding_req_hist::gmean 15.997202
+system.ruby.outstanding_req_hist::stdev 0.125833
+system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 17 0.00% 0.02% | 626349 99.98% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 626470
system.ruby.latency_hist::bucket_size 1024
system.ruby.latency_hist::max_bucket 10239
-system.ruby.latency_hist::samples 623686
-system.ruby.latency_hist::mean 2072.612140
-system.ruby.latency_hist::gmean 1591.498940
-system.ruby.latency_hist::stdev 1226.963263
-system.ruby.latency_hist | 164804 26.42% 26.42% | 150821 24.18% 50.61% | 147979 23.73% 74.33% | 131724 21.12% 95.45% | 27974 4.49% 99.94% | 384 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 623686
+system.ruby.latency_hist::samples 626342
+system.ruby.latency_hist::mean 2071.919100
+system.ruby.latency_hist::gmean 1588.311546
+system.ruby.latency_hist::stdev 1228.835712
+system.ruby.latency_hist | 165846 26.48% 26.48% | 150976 24.10% 50.58% | 148385 23.69% 74.27% | 132690 21.18% 95.46% | 28063 4.48% 99.94% | 382 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 626342
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
system.ruby.hit_latency_hist::samples 9
system.ruby.hit_latency_hist::total 9
system.ruby.miss_latency_hist::bucket_size 1024
system.ruby.miss_latency_hist::max_bucket 10239
-system.ruby.miss_latency_hist::samples 623677
-system.ruby.miss_latency_hist::mean 2072.642005
-system.ruby.miss_latency_hist::gmean 1591.643032
-system.ruby.miss_latency_hist::stdev 1226.946927
-system.ruby.miss_latency_hist | 164795 26.42% 26.42% | 150821 24.18% 50.61% | 147979 23.73% 74.33% | 131724 21.12% 95.45% | 27974 4.49% 99.94% | 384 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 623677
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 3 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 77823 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 77826 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 626333
+system.ruby.miss_latency_hist::mean 2071.948829
+system.ruby.miss_latency_hist::gmean 1588.454694
+system.ruby.miss_latency_hist::stdev 1228.819513
+system.ruby.miss_latency_hist | 165837 26.48% 26.48% | 150976 24.10% 50.58% | 148385 23.69% 74.27% | 132690 21.19% 95.46% | 28063 4.48% 99.94% | 382 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 626333
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 2 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 78425 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78427 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 2 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 77422 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77424 # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits 1 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses 78414 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78415 # Number of cache demand accesses
system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses 77856 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77857 # Number of cache demand accesses
+system.ruby.l1_cntrl2.L1Dcache.demand_hits 3 # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses 78001 # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78004 # Number of cache demand accesses
system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses 77999 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78000 # Number of cache demand accesses
+system.ruby.l1_cntrl3.L1Dcache.demand_misses 78494 # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78495 # Number of cache demand accesses
system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl4.L1Dcache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses 78237 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78237 # Number of cache demand accesses
+system.ruby.l1_cntrl4.L1Dcache.demand_hits 2 # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Dcache.demand_misses 78222 # Number of cache demand misses
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system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl5.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses 77909 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77910 # Number of cache demand accesses
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system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
system.ruby.l1_cntrl6.L1Dcache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses 77980 # Number of cache demand misses
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system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl7.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses 78469 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78470 # Number of cache demand accesses
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system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
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-system.ruby.l2_cntrl0.L2cache.demand_accesses 623683 # Number of cache demand accesses
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+system.ruby.l2_cntrl0.L2cache.demand_accesses 626338 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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system.ruby.delayVCHist.vnet_0::bucket_size 2048 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 20479 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 1567834 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 632.927856 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 886.561692 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 1430124 91.22% 91.22% | 131198 8.37% 99.58% | 6246 0.40% 99.98% | 255 0.02% 100.00% | 8 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 1567834 # delay histogram for vnet_0
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+system.ruby.delayVCHist.vnet_0::mean 631.193011 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev 885.262867 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0 | 1436392 91.24% 91.24% | 131487 8.35% 99.59% | 6055 0.38% 99.98% | 370 0.02% 100.00% | 13 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 1574320 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_1::bucket_size 8 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 79 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 2793654 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 2.252049 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 4.236651 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 2389326 85.53% 85.53% | 338163 12.10% 97.63% | 58171 2.08% 99.71% | 7435 0.27% 99.98% | 537 0.02% 100.00% | 22 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 2793654 # delay histogram for vnet_1
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+system.ruby.delayVCHist.vnet_1::mean 2.261817 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 4.246713 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 2397962 85.46% 85.46% | 340890 12.15% 97.61% | 58848 2.10% 99.71% | 7632 0.27% 99.98% | 517 0.02% 100.00% | 24 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 2805873 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 610308 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.009651 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.138784 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 607367 99.52% 99.52% | 0 0.00% 99.52% | 2937 0.48% 100.00% | 0 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 610308 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 613356 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean 0.009639 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev 0.138885 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 610408 99.52% 99.52% | 0 0.00% 99.52% | 2940 0.48% 100.00% | 0 0.00% 100.00% | 8 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
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system.ruby.LD.latency_hist::bucket_size 1024
system.ruby.LD.latency_hist::max_bucket 10239
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-system.ruby.LD.latency_hist::mean 2073.498317
-system.ruby.LD.latency_hist::gmean 1592.038290
-system.ruby.LD.latency_hist::stdev 1226.855968
-system.ruby.LD.latency_hist | 106152 26.41% 26.41% | 97021 24.13% 50.54% | 95622 23.79% 74.33% | 84872 21.11% 95.44% | 18097 4.50% 99.94% | 237 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.LD.latency_hist::stdev 1228.569503
+system.ruby.LD.latency_hist | 106527 26.46% 26.46% | 97059 24.11% 50.57% | 95427 23.70% 74.27% | 85360 21.20% 95.47% | 17986 4.47% 99.94% | 257 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
system.ruby.LD.hit_latency_hist::samples 6
system.ruby.LD.hit_latency_hist::total 6
system.ruby.LD.miss_latency_hist::bucket_size 1024
system.ruby.LD.miss_latency_hist::max_bucket 10239
-system.ruby.LD.miss_latency_hist::samples 401995
-system.ruby.LD.miss_latency_hist::mean 2073.529221
-system.ruby.LD.miss_latency_hist::gmean 1592.187383
-system.ruby.LD.miss_latency_hist::stdev 1226.839046
-system.ruby.LD.miss_latency_hist | 106146 26.40% 26.40% | 97021 24.13% 50.54% | 95622 23.79% 74.33% | 84872 21.11% 95.44% | 18097 4.50% 99.94% | 237 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.LD.miss_latency_hist | 106521 26.46% 26.46% | 97059 24.11% 50.57% | 95427 23.70% 74.27% | 85360 21.20% 95.47% | 17986 4.47% 99.94% | 257 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.latency_hist::bucket_size 1024
system.ruby.ST.latency_hist::max_bucket 10239
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-system.ruby.ST.latency_hist::mean 2071.005156
-system.ruby.ST.latency_hist::gmean 1590.521356
-system.ruby.ST.latency_hist::stdev 1227.158942
-system.ruby.ST.latency_hist | 58652 26.46% 26.46% | 53800 24.27% 50.73% | 52357 23.62% 74.34% | 46852 21.13% 95.48% | 9877 4.46% 99.93% | 147 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.latency_hist::total 221685
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+system.ruby.ST.latency_hist::gmean 1587.500627
+system.ruby.ST.latency_hist::stdev 1229.317345
+system.ruby.ST.latency_hist | 59319 26.51% 26.51% | 53917 24.10% 50.61% | 52958 23.67% 74.28% | 47330 21.16% 95.44% | 10077 4.50% 99.94% | 125 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
system.ruby.ST.hit_latency_hist::samples 3
system.ruby.ST.hit_latency_hist::total 3
system.ruby.ST.miss_latency_hist::bucket_size 1024
system.ruby.ST.miss_latency_hist::max_bucket 10239
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-system.ruby.ST.miss_latency_hist::mean 2071.033142
-system.ruby.ST.miss_latency_hist::gmean 1590.656389
-system.ruby.ST.miss_latency_hist::stdev 1227.143664
-system.ruby.ST.miss_latency_hist | 58649 26.46% 26.46% | 53800 24.27% 50.73% | 52357 23.62% 74.34% | 46852 21.13% 95.48% | 9877 4.46% 99.93% | 147 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Directory_Controller.Fetch 617983 0.00% 0.00%
-system.ruby.Directory_Controller.Data 221016 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 617980 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 221016 0.00% 0.00%
-system.ruby.Directory_Controller.CleanReplacement 396959 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 617983 0.00% 0.00%
-system.ruby.Directory_Controller.M.Data 221016 0.00% 0.00%
-system.ruby.Directory_Controller.M.CleanReplacement 396959 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 617980 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 221016 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50178 12.48% 12.48% | 50038 12.45% 24.93% | 50231 12.49% 37.42% | 50088 12.46% 49.88% | 50377 12.53% 62.41% | 50301 12.51% 74.93% | 50175 12.48% 87.41% | 50630 12.59% 100.00%
-system.ruby.L1Cache_Controller.Load::total 402018
-system.ruby.L1Cache_Controller.Store | 27650 12.47% 12.47% | 27387 12.35% 24.83% | 27627 12.46% 37.29% | 27913 12.59% 49.88% | 27862 12.57% 62.45% | 27609 12.45% 74.90% | 27807 12.54% 87.44% | 27841 12.56% 100.00%
-system.ruby.L1Cache_Controller.Store::total 221696
-system.ruby.L1Cache_Controller.Inv | 75709 12.47% 12.47% | 75402 12.42% 24.89% | 75814 12.49% 37.37% | 75941 12.51% 49.88% | 76137 12.54% 62.42% | 75836 12.49% 74.91% | 76014 12.52% 87.43% | 76329 12.57% 100.00%
-system.ruby.L1Cache_Controller.Inv::total 607182
-system.ruby.L1Cache_Controller.L1_Replacement | 551542 12.52% 12.52% | 547463 12.43% 24.96% | 549808 12.48% 37.44% | 549863 12.49% 49.93% | 551618 12.53% 62.45% | 550552 12.50% 74.95% | 550899 12.51% 87.46% | 552114 12.54% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 4403859
-system.ruby.L1Cache_Controller.Fwd_GETX | 227 12.34% 12.34% | 242 13.15% 25.49% | 244 13.26% 38.75% | 236 12.83% 51.58% | 214 11.63% 63.21% | 219 11.90% 75.11% | 224 12.17% 87.28% | 234 12.72% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total 1840
-system.ruby.L1Cache_Controller.Fwd_GETS | 164 12.75% 12.75% | 163 12.67% 25.43% | 176 13.69% 39.11% | 169 13.14% 52.26% | 153 11.90% 64.15% | 162 12.60% 76.75% | 161 12.52% 89.27% | 138 10.73% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total 1286
-system.ruby.L1Cache_Controller.Data | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.Data::total 9
-system.ruby.L1Cache_Controller.Data_Exclusive | 49353 12.47% 12.47% | 49226 12.44% 24.92% | 49455 12.50% 37.42% | 49297 12.46% 49.88% | 49592 12.54% 62.41% | 49499 12.51% 74.92% | 49412 12.49% 87.41% | 49794 12.59% 100.00%
-system.ruby.L1Cache_Controller.Data_Exclusive::total 395628
-system.ruby.L1Cache_Controller.DataS_fromL1 | 159 12.36% 12.36% | 160 12.44% 24.81% | 147 11.43% 36.24% | 160 12.44% 48.68% | 141 10.96% 59.64% | 142 11.04% 70.68% | 173 13.45% 84.14% | 204 15.86% 100.00%
-system.ruby.L1Cache_Controller.DataS_fromL1::total 1286
-system.ruby.L1Cache_Controller.Data_all_Acks | 28305 12.48% 12.48% | 28033 12.36% 24.85% | 28250 12.46% 37.30% | 28541 12.59% 49.89% | 28500 12.57% 62.46% | 28265 12.47% 74.92% | 28392 12.52% 87.45% | 28468 12.55% 100.00%
-system.ruby.L1Cache_Controller.Data_all_Acks::total 226754
-system.ruby.L1Cache_Controller.Ack | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 9
-system.ruby.L1Cache_Controller.Ack_all | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.Ack_all::total 9
-system.ruby.L1Cache_Controller.WB_Ack | 40511 12.44% 12.44% | 40148 12.33% 24.78% | 40397 12.41% 37.18% | 40704 12.50% 49.69% | 41130 12.63% 62.32% | 40703 12.50% 74.82% | 40662 12.49% 87.31% | 41301 12.69% 100.00%
-system.ruby.L1Cache_Controller.WB_Ack::total 325556
-system.ruby.L1Cache_Controller.NP.Load | 50164 12.48% 12.48% | 50032 12.45% 24.93% | 50223 12.50% 37.42% | 50076 12.46% 49.88% | 50363 12.53% 62.41% | 50292 12.51% 74.93% | 50165 12.48% 87.41% | 50615 12.59% 100.00%
-system.ruby.L1Cache_Controller.NP.Load::total 401930
-system.ruby.L1Cache_Controller.NP.Store | 27646 12.47% 12.47% | 27381 12.35% 24.83% | 27620 12.46% 37.29% | 27908 12.59% 49.88% | 27857 12.57% 62.45% | 27604 12.45% 74.90% | 27800 12.54% 87.44% | 27836 12.56% 100.00%
-system.ruby.L1Cache_Controller.NP.Store::total 221652
-system.ruby.L1Cache_Controller.NP.Inv | 222 13.07% 13.07% | 216 12.72% 25.80% | 227 13.37% 39.16% | 217 12.78% 51.94% | 188 11.07% 63.02% | 211 12.43% 75.44% | 216 12.72% 88.16% | 201 11.84% 100.00%
-system.ruby.L1Cache_Controller.NP.Inv::total 1698
-system.ruby.L1Cache_Controller.I.Load | 10 12.99% 12.99% | 5 6.49% 19.48% | 8 10.39% 29.87% | 11 14.29% 44.16% | 13 16.88% 61.04% | 8 10.39% 71.43% | 9 11.69% 83.12% | 13 16.88% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 77
-system.ruby.L1Cache_Controller.I.Store | 3 8.33% 8.33% | 4 11.11% 19.44% | 5 13.89% 33.33% | 4 11.11% 44.44% | 4 11.11% 55.56% | 5 13.89% 69.44% | 6 16.67% 86.11% | 5 13.89% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 36
-system.ruby.L1Cache_Controller.I.L1_Replacement | 37148 12.52% 12.52% | 37103 12.50% 25.02% | 37284 12.56% 37.58% | 37119 12.51% 50.08% | 36952 12.45% 62.53% | 37057 12.48% 75.01% | 37155 12.52% 87.53% | 37007 12.47% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 296825
-system.ruby.L1Cache_Controller.S.Inv | 700 12.82% 12.82% | 698 12.78% 25.60% | 657 12.03% 37.64% | 666 12.20% 49.84% | 683 12.51% 62.34% | 691 12.66% 75.00% | 647 11.85% 86.85% | 718 13.15% 100.00%
-system.ruby.L1Cache_Controller.S.Inv::total 5460
-system.ruby.L1Cache_Controller.S.L1_Replacement | 145 12.50% 12.50% | 157 13.53% 26.03% | 157 13.53% 39.57% | 156 13.45% 53.02% | 133 11.47% 64.48% | 131 11.29% 75.78% | 143 12.33% 88.10% | 138 11.90% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 1160
-system.ruby.L1Cache_Controller.E.Load | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
-system.ruby.L1Cache_Controller.E.Load::total 3
-system.ruby.L1Cache_Controller.E.Store | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::samples 223723
+system.ruby.ST.miss_latency_hist::mean 2071.712305
+system.ruby.ST.miss_latency_hist::gmean 1587.634133
+system.ruby.ST.miss_latency_hist::stdev 1229.302246
+system.ruby.ST.miss_latency_hist | 59316 26.51% 26.51% | 53917 24.10% 50.61% | 52958 23.67% 74.28% | 47330 21.16% 95.44% | 10077 4.50% 99.94% | 125 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::total 223723
+system.ruby.Directory_Controller.Fetch 620666 0.00% 0.00%
+system.ruby.Directory_Controller.Data 223044 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 620662 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 223044 0.00% 0.00%
+system.ruby.Directory_Controller.CleanReplacement 397614 0.00% 0.00%
+system.ruby.Directory_Controller.I.Fetch 620666 0.00% 0.00%
+system.ruby.Directory_Controller.M.Data 223044 0.00% 0.00%
+system.ruby.Directory_Controller.M.CleanReplacement 397614 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 620662 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 223044 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load | 50387 12.51% 12.51% | 50364 12.51% 25.02% | 50179 12.46% 37.49% | 50465 12.53% 50.02% | 50375 12.51% 62.53% | 50436 12.53% 75.06% | 50129 12.45% 87.51% | 50302 12.49% 100.00%
+system.ruby.L1Cache_Controller.Load::total 402637
+system.ruby.L1Cache_Controller.Store | 28042 12.53% 12.53% | 28053 12.54% 25.07% | 27828 12.44% 37.51% | 28030 12.53% 50.04% | 27852 12.45% 62.48% | 27954 12.49% 74.98% | 27928 12.48% 87.46% | 28057 12.54% 100.00%
+system.ruby.L1Cache_Controller.Store::total 223744
+system.ruby.L1Cache_Controller.Inv | 76503 12.54% 12.54% | 76387 12.52% 25.05% | 75991 12.45% 37.51% | 76469 12.53% 50.04% | 76247 12.49% 62.53% | 76392 12.52% 75.05% | 76025 12.46% 87.51% | 76209 12.49% 100.00%
+system.ruby.L1Cache_Controller.Inv::total 610223
+system.ruby.L1Cache_Controller.L1_Replacement | 552329 12.49% 12.49% | 554080 12.53% 25.02% | 551001 12.46% 37.48% | 553019 12.51% 49.99% | 552775 12.50% 62.49% | 553813 12.53% 75.02% | 551589 12.47% 87.49% | 552978 12.51% 100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total 4421584
+system.ruby.L1Cache_Controller.Fwd_GETX | 235 12.95% 12.95% | 233 12.84% 25.80% | 206 11.36% 37.16% | 229 12.62% 49.78% | 229 12.62% 62.40% | 224 12.35% 74.75% | 227 12.51% 87.27% | 231 12.73% 100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total 1814
+system.ruby.L1Cache_Controller.Fwd_GETS | 155 11.75% 11.75% | 179 13.57% 25.32% | 158 11.98% 37.30% | 167 12.66% 49.96% | 159 12.05% 62.02% | 186 14.10% 76.12% | 154 11.68% 87.79% | 161 12.21% 100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total 1319
+system.ruby.L1Cache_Controller.Data | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.Data::total 10
+system.ruby.L1Cache_Controller.Data_Exclusive | 49564 12.51% 12.51% | 49570 12.51% 25.02% | 49411 12.47% 37.49% | 49662 12.53% 50.02% | 49589 12.51% 62.53% | 49661 12.53% 75.07% | 49353 12.45% 87.52% | 49453 12.48% 100.00%
+system.ruby.L1Cache_Controller.Data_Exclusive::total 396263
+system.ruby.L1Cache_Controller.DataS_fromL1 | 167 12.66% 12.66% | 162 12.28% 24.94% | 164 12.43% 37.38% | 179 13.57% 50.95% | 170 12.89% 63.84% | 150 11.37% 75.21% | 153 11.60% 86.81% | 174 13.19% 100.00%
+system.ruby.L1Cache_Controller.DataS_fromL1::total 1319
+system.ruby.L1Cache_Controller.Data_all_Acks | 28690 12.54% 12.54% | 28678 12.54% 25.08% | 28423 12.43% 37.51% | 28648 12.52% 50.03% | 28457 12.44% 62.47% | 28571 12.49% 74.96% | 28547 12.48% 87.44% | 28727 12.56% 100.00%
+system.ruby.L1Cache_Controller.Data_all_Acks::total 228741
+system.ruby.L1Cache_Controller.Ack | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.Ack::total 10
+system.ruby.L1Cache_Controller.Ack_all | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.Ack_all::total 10
+system.ruby.L1Cache_Controller.WB_Ack | 40897 12.52% 12.52% | 40967 12.54% 25.06% | 40490 12.39% 37.45% | 41087 12.58% 50.03% | 40664 12.45% 62.48% | 41053 12.57% 75.05% | 40626 12.44% 87.48% | 40894 12.52% 100.00%
+system.ruby.L1Cache_Controller.WB_Ack::total 326678
+system.ruby.L1Cache_Controller.NP.Load | 50378 12.51% 12.51% | 50348 12.51% 25.02% | 50170 12.46% 37.48% | 50455 12.53% 50.02% | 50362 12.51% 62.53% | 50427 12.53% 75.06% | 50123 12.45% 87.51% | 50292 12.49% 100.00%
+system.ruby.L1Cache_Controller.NP.Load::total 402555
+system.ruby.L1Cache_Controller.NP.Store | 28035 12.53% 12.53% | 28046 12.54% 25.07% | 27823 12.44% 37.51% | 28023 12.53% 50.04% | 27848 12.45% 62.49% | 27949 12.49% 74.98% | 27917 12.48% 87.46% | 28052 12.54% 100.00%
+system.ruby.L1Cache_Controller.NP.Store::total 223693
+system.ruby.L1Cache_Controller.NP.Inv | 220 12.34% 12.34% | 229 12.84% 25.18% | 209 11.72% 36.90% | 233 13.07% 49.97% | 235 13.18% 63.15% | 247 13.85% 77.01% | 202 11.33% 88.33% | 208 11.67% 100.00%
+system.ruby.L1Cache_Controller.NP.Inv::total 1783
+system.ruby.L1Cache_Controller.I.Load | 7 10.94% 10.94% | 14 21.88% 32.81% | 4 6.25% 39.06% | 10 15.62% 54.69% | 9 14.06% 68.75% | 6 9.38% 78.12% | 6 9.38% 87.50% | 8 12.50% 100.00%
+system.ruby.L1Cache_Controller.I.Load::total 64
+system.ruby.L1Cache_Controller.I.Store | 5 11.63% 11.63% | 6 13.95% 25.58% | 4 9.30% 34.88% | 6 13.95% 48.84% | 3 6.98% 55.81% | 4 9.30% 65.12% | 10 23.26% 88.37% | 5 11.63% 100.00%
+system.ruby.L1Cache_Controller.I.Store::total 43
+system.ruby.L1Cache_Controller.I.L1_Replacement | 37358 12.52% 12.52% | 37278 12.50% 25.02% | 37354 12.52% 37.54% | 37224 12.48% 50.02% | 37375 12.53% 62.54% | 37164 12.46% 75.00% | 37269 12.49% 87.49% | 37314 12.51% 100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total 298336
+system.ruby.L1Cache_Controller.S.Inv | 693 12.90% 12.90% | 679 12.64% 25.54% | 642 11.95% 37.48% | 666 12.40% 49.88% | 649 12.08% 61.96% | 646 12.02% 73.98% | 661 12.30% 86.28% | 737 13.72% 100.00%
+system.ruby.L1Cache_Controller.S.Inv::total 5373
+system.ruby.L1Cache_Controller.S.L1_Replacement | 154 13.01% 13.01% | 143 12.08% 25.08% | 142 11.99% 37.08% | 159 13.43% 50.51% | 164 13.85% 64.36% | 153 12.92% 77.28% | 139 11.74% 89.02% | 130 10.98% 100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total 1184
+system.ruby.L1Cache_Controller.E.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 60.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.E.Load::total 5
+system.ruby.L1Cache_Controller.E.Store | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.E.Store::total 3
-system.ruby.L1Cache_Controller.E.Inv | 23165 12.45% 12.45% | 23206 12.47% 24.91% | 23518 12.64% 37.55% | 23248 12.49% 50.04% | 23136 12.43% 62.47% | 23354 12.55% 75.02% | 23312 12.52% 87.54% | 23192 12.46% 100.00%
-system.ruby.L1Cache_Controller.E.Inv::total 186131
-system.ruby.L1Cache_Controller.E.L1_Replacement | 26108 12.50% 12.50% | 25954 12.42% 24.92% | 25849 12.37% 37.29% | 25977 12.43% 49.72% | 26399 12.63% 62.35% | 26084 12.48% 74.84% | 26041 12.46% 87.30% | 26535 12.70% 100.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement::total 208947
-system.ruby.L1Cache_Controller.E.Fwd_GETX | 70 14.80% 14.80% | 54 11.42% 26.22% | 73 15.43% 41.65% | 64 13.53% 55.18% | 47 9.94% 65.12% | 52 10.99% 76.11% | 52 10.99% 87.10% | 61 12.90% 100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETX::total 473
-system.ruby.L1Cache_Controller.E.Fwd_GETS | 9 12.50% 12.50% | 10 13.89% 26.39% | 14 19.44% 45.83% | 8 11.11% 56.94% | 9 12.50% 69.44% | 9 12.50% 81.94% | 7 9.72% 91.67% | 6 8.33% 100.00%
-system.ruby.L1Cache_Controller.E.Fwd_GETS::total 72
-system.ruby.L1Cache_Controller.M.Load | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 3
-system.ruby.L1Cache_Controller.M.Inv | 13157 12.61% 12.61% | 13076 12.54% 25.15% | 12978 12.44% 37.59% | 13085 12.55% 50.14% | 13028 12.49% 62.63% | 12904 12.37% 75.00% | 13083 12.54% 87.54% | 12992 12.46% 100.00%
-system.ruby.L1Cache_Controller.M.Inv::total 104303
-system.ruby.L1Cache_Controller.M.L1_Replacement | 14405 12.35% 12.35% | 14195 12.17% 24.52% | 14549 12.48% 37.00% | 14728 12.63% 49.63% | 14732 12.63% 62.26% | 14620 12.54% 74.80% | 14622 12.54% 87.34% | 14767 12.66% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 116618
-system.ruby.L1Cache_Controller.M.Fwd_GETX | 27 9.96% 9.96% | 47 17.34% 27.31% | 32 11.81% 39.11% | 31 11.44% 50.55% | 35 12.92% 63.47% | 32 11.81% 75.28% | 37 13.65% 88.93% | 30 11.07% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 271
-system.ruby.L1Cache_Controller.M.Fwd_GETS | 61 12.37% 12.37% | 67 13.59% 25.96% | 66 13.39% 39.35% | 67 13.59% 52.94% | 66 13.39% 66.33% | 53 10.75% 77.08% | 62 12.58% 89.66% | 51 10.34% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total 493
-system.ruby.L1Cache_Controller.IS.Inv | 44 14.10% 14.10% | 32 10.26% 24.36% | 40 12.82% 37.18% | 43 13.78% 50.96% | 40 12.82% 63.78% | 39 12.50% 76.28% | 40 12.82% 89.10% | 34 10.90% 100.00%
-system.ruby.L1Cache_Controller.IS.Inv::total 312
-system.ruby.L1Cache_Controller.IS.L1_Replacement | 304930 12.52% 12.52% | 304677 12.51% 25.03% | 304555 12.50% 37.53% | 302791 12.43% 49.96% | 304661 12.51% 62.47% | 304322 12.49% 74.97% | 304505 12.50% 87.47% | 305212 12.53% 100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2435653
-system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49353 12.47% 12.47% | 49226 12.44% 24.92% | 49455 12.50% 37.42% | 49297 12.46% 49.88% | 49592 12.54% 62.41% | 49499 12.51% 74.92% | 49412 12.49% 87.41% | 49794 12.59% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 395628
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 159 12.36% 12.36% | 160 12.44% 24.81% | 147 11.43% 36.24% | 160 12.44% 48.68% | 141 10.96% 59.64% | 142 11.04% 70.68% | 173 13.45% 84.14% | 204 15.86% 100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1286
-system.ruby.L1Cache_Controller.IS.Data_all_Acks | 616 12.92% 12.92% | 618 12.96% 25.88% | 587 12.31% 38.18% | 587 12.31% 50.49% | 600 12.58% 63.07% | 618 12.96% 76.03% | 548 11.49% 87.52% | 595 12.48% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4769
-system.ruby.L1Cache_Controller.IM.L1_Replacement | 168806 12.55% 12.55% | 165377 12.30% 24.85% | 167414 12.45% 37.30% | 169092 12.58% 49.88% | 168741 12.55% 62.43% | 168337 12.52% 74.95% | 168433 12.53% 87.47% | 168454 12.53% 100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1344654
-system.ruby.L1Cache_Controller.IM.Data | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 9
-system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27645 12.47% 12.47% | 27383 12.35% 24.82% | 27623 12.46% 37.29% | 27911 12.59% 49.88% | 27860 12.57% 62.44% | 27608 12.45% 74.90% | 27804 12.54% 87.44% | 27839 12.56% 100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 221673
-system.ruby.L1Cache_Controller.SM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.L1Cache_Controller.SM.L1_Replacement::total 1
-system.ruby.L1Cache_Controller.SM.Ack | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 9
-system.ruby.L1Cache_Controller.SM.Ack_all | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total 9
-system.ruby.L1Cache_Controller.IS_I.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IS_I.L1_Replacement::total 1
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 44 14.10% 14.10% | 32 10.26% 24.36% | 40 12.82% 37.18% | 43 13.78% 50.96% | 40 12.82% 63.78% | 39 12.50% 76.28% | 40 12.82% 89.10% | 34 10.90% 100.00%
-system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 312
-system.ruby.L1Cache_Controller.M_I.Inv | 38404 12.42% 12.42% | 38147 12.34% 24.77% | 38368 12.41% 37.18% | 38649 12.50% 49.68% | 39039 12.63% 62.31% | 38617 12.49% 74.81% | 38697 12.52% 87.33% | 39174 12.67% 100.00%
-system.ruby.L1Cache_Controller.M_I.Inv::total 309095
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 130 11.86% 11.86% | 141 12.86% 24.73% | 139 12.68% 37.41% | 141 12.86% 50.27% | 132 12.04% 62.32% | 135 12.32% 74.64% | 135 12.32% 86.95% | 143 13.05% 100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1096
-system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 94 13.04% 13.04% | 86 11.93% 24.97% | 96 13.31% 38.28% | 94 13.04% 51.32% | 78 10.82% 62.14% | 100 13.87% 76.01% | 92 12.76% 88.77% | 81 11.23% 100.00%
-system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 721
-system.ruby.L1Cache_Controller.M_I.WB_Ack | 1885 12.86% 12.86% | 1775 12.11% 24.98% | 1795 12.25% 37.23% | 1821 12.43% 49.66% | 1882 12.84% 62.50% | 1852 12.64% 75.14% | 1739 11.87% 87.01% | 1904 12.99% 100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total 14653
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 5
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 5
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 17 9.29% 9.29% | 27 14.75% 24.04% | 26 14.21% 38.25% | 33 18.03% 56.28% | 23 12.57% 68.85% | 20 10.93% 79.78% | 19 10.38% 90.16% | 18 9.84% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 183
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 38626 12.42% 12.42% | 38373 12.34% 24.77% | 38602 12.42% 37.18% | 38883 12.51% 49.69% | 39248 12.62% 62.31% | 38851 12.50% 74.81% | 38923 12.52% 87.33% | 39397 12.67% 100.00%
-system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 310903
-system.ruby.L2Cache_Controller.L1_GETS 403619 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 224049 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 16718 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX_old 316360 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 6791 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 4927098 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 617978 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 617975 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 215635 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 199049 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack 3824 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 189942 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 1286 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 617309 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 398157 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 219826 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_PUTX_old 306767 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTX 543 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTX_old 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement 1199 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2612 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 5381 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 9254 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS 1286 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX 1840 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 14653 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX_old 832 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 599522 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_GETS 21 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_GETX 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 2174 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 617975 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_GETS 62 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_GETX 79 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 5995 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 214429 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 198965 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 186128 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack 2623 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 2612 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack 1201 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all 1199 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L1_GETS 2534 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L1_GETX 1425 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 281 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2159388 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 395619 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L1_GETS 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L1_GETX 5 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.Inv | 23423 12.54% 12.54% | 23271 12.45% 24.99% | 23422 12.53% 37.52% | 23280 12.46% 49.98% | 23423 12.54% 62.52% | 23370 12.51% 75.03% | 23365 12.50% 87.53% | 23299 12.47% 100.00%
+system.ruby.L1Cache_Controller.E.Inv::total 186853
+system.ruby.L1Cache_Controller.E.L1_Replacement | 26089 12.49% 12.49% | 26232 12.55% 25.04% | 25939 12.41% 37.45% | 26323 12.60% 50.05% | 26112 12.50% 62.55% | 26240 12.56% 75.11% | 25933 12.41% 87.52% | 26081 12.48% 100.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement::total 208949
+system.ruby.L1Cache_Controller.E.Fwd_GETX | 45 11.25% 11.25% | 58 14.50% 25.75% | 43 10.75% 36.50% | 53 13.25% 49.75% | 43 10.75% 60.50% | 45 11.25% 71.75% | 50 12.50% 84.25% | 63 15.75% 100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETX::total 400
+system.ruby.L1Cache_Controller.E.Fwd_GETS | 6 10.71% 10.71% | 8 14.29% 25.00% | 7 12.50% 37.50% | 5 8.93% 46.43% | 10 17.86% 64.29% | 6 10.71% 75.00% | 5 8.93% 83.93% | 9 16.07% 100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETS::total 56
+system.ruby.L1Cache_Controller.M.Load | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.M.Load::total 1
+system.ruby.L1Cache_Controller.M.Inv | 13143 12.49% 12.49% | 13204 12.55% 25.04% | 13192 12.54% 37.57% | 13169 12.51% 50.09% | 13209 12.55% 62.64% | 13024 12.38% 75.01% | 13141 12.49% 87.50% | 13152 12.50% 100.00%
+system.ruby.L1Cache_Controller.M.Inv::total 105234
+system.ruby.L1Cache_Controller.M.L1_Replacement | 14808 12.58% 12.58% | 14737 12.52% 25.09% | 14554 12.36% 37.45% | 14768 12.54% 49.99% | 14555 12.36% 62.36% | 14815 12.58% 74.94% | 14695 12.48% 87.42% | 14815 12.58% 100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total 117747
+system.ruby.L1Cache_Controller.M.Fwd_GETX | 28 10.57% 10.57% | 45 16.98% 27.55% | 23 8.68% 36.23% | 29 10.94% 47.17% | 27 10.19% 57.36% | 50 18.87% 76.23% | 29 10.94% 87.17% | 34 12.83% 100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total 265
+system.ruby.L1Cache_Controller.M.Fwd_GETS | 60 12.50% 12.50% | 65 13.54% 26.04% | 56 11.67% 37.71% | 64 13.33% 51.04% | 59 12.29% 63.33% | 62 12.92% 76.25% | 60 12.50% 88.75% | 54 11.25% 100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total 480
+system.ruby.L1Cache_Controller.IS.Inv | 40 12.27% 12.27% | 42 12.88% 25.15% | 42 12.88% 38.04% | 43 13.19% 51.23% | 36 11.04% 62.27% | 40 12.27% 74.54% | 41 12.58% 87.12% | 42 12.88% 100.00%
+system.ruby.L1Cache_Controller.IS.Inv::total 326
+system.ruby.L1Cache_Controller.IS.L1_Replacement | 304582 12.48% 12.48% | 306242 12.55% 25.03% | 304848 12.49% 37.52% | 305151 12.51% 50.03% | 305139 12.50% 62.53% | 305447 12.52% 75.05% | 304421 12.48% 87.53% | 304369 12.47% 100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2440199
+system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49564 12.51% 12.51% | 49570 12.51% 25.02% | 49411 12.47% 37.49% | 49662 12.53% 50.02% | 49589 12.51% 62.53% | 49661 12.53% 75.07% | 49353 12.45% 87.52% | 49453 12.48% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 396263
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 167 12.66% 12.66% | 162 12.28% 24.94% | 164 12.43% 37.38% | 179 13.57% 50.95% | 170 12.89% 63.84% | 150 11.37% 75.21% | 153 11.60% 86.81% | 174 13.19% 100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1319
+system.ruby.L1Cache_Controller.IS.Data_all_Acks | 614 13.06% 13.06% | 587 12.48% 25.54% | 557 11.85% 37.39% | 577 12.27% 49.66% | 574 12.21% 61.87% | 581 12.36% 74.22% | 582 12.38% 86.60% | 630 13.40% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4702
+system.ruby.L1Cache_Controller.IM.L1_Replacement | 169338 12.50% 12.50% | 169448 12.50% 25.00% | 168164 12.41% 37.41% | 169394 12.50% 49.91% | 169430 12.50% 62.41% | 169994 12.54% 74.96% | 169132 12.48% 87.44% | 170269 12.56% 100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1355169
+system.ruby.L1Cache_Controller.IM.Data | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.IM.Data::total 10
+system.ruby.L1Cache_Controller.IM.Data_all_Acks | 28036 12.53% 12.53% | 28049 12.54% 25.07% | 27824 12.44% 37.51% | 28028 12.53% 50.04% | 27847 12.45% 62.48% | 27950 12.49% 74.98% | 27924 12.48% 87.46% | 28055 12.54% 100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 223713
+system.ruby.L1Cache_Controller.SM.Ack | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total 10
+system.ruby.L1Cache_Controller.SM.Ack_all | 2 20.00% 20.00% | 1 10.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total 10
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 40 12.27% 12.27% | 42 12.88% 25.15% | 42 12.88% 38.04% | 43 13.19% 51.23% | 36 11.04% 62.27% | 40 12.27% 74.54% | 41 12.58% 87.12% | 42 12.88% 100.00%
+system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 326
+system.ruby.L1Cache_Controller.M_I.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.M_I.Load::total 2
+system.ruby.L1Cache_Controller.M_I.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.M_I.Store::total 1
+system.ruby.L1Cache_Controller.M_I.Inv | 38961 12.55% 12.55% | 38942 12.54% 25.09% | 38456 12.39% 37.48% | 39054 12.58% 50.06% | 38676 12.46% 62.51% | 39041 12.57% 75.09% | 38589 12.43% 87.52% | 38751 12.48% 100.00%
+system.ruby.L1Cache_Controller.M_I.Inv::total 310470
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 162 14.10% 14.10% | 130 11.31% 25.41% | 140 12.18% 37.60% | 147 12.79% 50.39% | 159 13.84% 64.23% | 129 11.23% 75.46% | 148 12.88% 88.34% | 134 11.66% 100.00%
+system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1149
+system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 89 11.37% 11.37% | 106 13.54% 24.90% | 95 12.13% 37.04% | 98 12.52% 49.55% | 90 11.49% 61.05% | 118 15.07% 76.12% | 89 11.37% 87.48% | 98 12.52% 100.00%
+system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 783
+system.ruby.L1Cache_Controller.M_I.WB_Ack | 1685 11.79% 11.79% | 1791 12.53% 24.32% | 1802 12.61% 36.93% | 1792 12.54% 49.46% | 1742 12.19% 61.65% | 1766 12.36% 74.01% | 1802 12.61% 86.62% | 1913 13.38% 100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total 14293
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 1 10.00% 10.00% | 2 20.00% 30.00% | 2 20.00% 50.00% | 0 0.00% 50.00% | 2 20.00% 70.00% | 2 20.00% 90.00% | 0 0.00% 90.00% | 1 10.00% 100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 10
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 4
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 23 12.50% 12.50% | 20 10.87% 23.37% | 28 15.22% 38.59% | 24 13.04% 51.63% | 19 10.33% 61.96% | 24 13.04% 75.00% | 26 14.13% 89.13% | 20 10.87% 100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 184
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 39212 12.55% 12.55% | 39176 12.54% 25.09% | 38688 12.38% 37.48% | 39295 12.58% 50.06% | 38922 12.46% 62.52% | 39287 12.58% 75.09% | 38824 12.43% 87.52% | 38981 12.48% 100.00%
+system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 312385
+system.ruby.L2Cache_Controller.L1_GETS 404349 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 226057 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 16561 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX_old 317938 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 6824 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean 4940882 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Data 620662 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Ack 620658 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data 217651 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean 199372 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack 3831 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack_all 190668 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 1319 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 619985 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 398766 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 221900 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_PUTX_old 308113 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX 10 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_PUTX 604 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_PUTX_old 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement 1242 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2573 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 5399 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8887 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS 1319 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX 1814 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 14293 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX_old 864 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 602549 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.L1_GETS 16 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.L1_GETX 22 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 2197 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 620658 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.Ack_all 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_GETS 70 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_GETX 61 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 6155 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 216395 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 199302 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 186852 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack 2585 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 2573 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack 1246 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all 1242 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.L1_GETS 2506 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.L1_GETX 1362 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 291 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2164243 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 396259 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.L1_GETS 12 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.L1_GETX 2 0.00% 0.00%
system.ruby.L2Cache_Controller.IS.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14164 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 2534 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L1_GETS 1405 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L1_GETX 765 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L1_PUTX_old 299 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1198508 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 219825 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 13776 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 2506 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.L1_GETS 1516 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.L1_GETX 804 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.L1_PUTX_old 310 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1208415 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 221897 0.00% 0.00%
system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS 129 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETX 76 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 921 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 940845 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 617300 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 598 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2788 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data 1020 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 64 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock 202 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 10 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS 132 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETX 72 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 992 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 937127 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 619975 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 668 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 3309 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data 1048 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 49 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock 222 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_IB.L1_PUTX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data 182 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 20 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 204 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.L2_Replacement_clean 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock 1084 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data 201 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 21 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_SB.L1_PUTX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 175 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock 1097 0.00% 0.00%
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.007401 # Number of seconds simulated
-sim_ticks 7400590 # Number of ticks simulated
-final_tick 7400590 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.007434 # Number of seconds simulated
+sim_ticks 7434347 # Number of ticks simulated
+final_tick 7434347 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 58553 # Simulator tick rate (ticks/s)
-host_mem_usage 666564 # Number of bytes of host memory used
-host_seconds 126.39 # Real time elapsed on the host
+host_tick_rate 60462 # Simulator tick rate (ticks/s)
+host_mem_usage 481612 # Number of bytes of host memory used
+host_seconds 122.96 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39203584 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 39203584 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14074880 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 14074880 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 612556 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 612556 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 219920 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 219920 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 5297359265 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 5297359265 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1901859176 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1901859176 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 7199218441 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 7199218441 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 612559 # Number of read requests accepted
-system.mem_ctrls.writeReqs 219920 # Number of write requests accepted
-system.mem_ctrls.readBursts 612559 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 219920 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 38724800 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 478976 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 13992640 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 39203776 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 14074880 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 7484 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 1262 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39396928 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 39396928 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14155776 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 14155776 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 615577 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 615577 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 221184 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 221184 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 5299312502 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 5299312502 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1904104826 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1904104826 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 7203417328 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 7203417328 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 615577 # Number of read requests accepted
+system.mem_ctrls.writeReqs 221184 # Number of write requests accepted
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+system.mem_ctrls.writeBursts 221184 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 38921664 # Total number of bytes read from DRAM
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+system.mem_ctrls.bytesWritten 14074624 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 39396928 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 14155776 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 7426 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 1246 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 75565 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
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system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 7400487 # Total gap between requests
+system.mem_ctrls.totGap 7434244 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 612559 # Read request sizes (log2)
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system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
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system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 219920 # Write request sizes (log2)
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-system.mem_ctrls.bytesPerActivate::samples 216410 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 243.595398 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 202.266425 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 149.425218 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 27460 12.69% 12.69% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 89166 41.20% 53.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 57358 26.50% 80.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 25806 11.92% 92.32% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 10676 4.93% 97.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 3981 1.84% 99.09% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1348 0.62% 99.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 415 0.19% 99.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 200 0.09% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 216410 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 13179 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 45.909705 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 42.812250 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 16.207292 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-7 27 0.20% 0.20% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-15 28 0.21% 0.42% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23 98 0.74% 1.16% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-31 4703 35.69% 36.85% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-39 1350 10.24% 47.09% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-47 197 1.49% 48.58% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-55 669 5.08% 53.66% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-63 5402 40.99% 94.65% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-71 338 2.56% 97.22% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79 90 0.68% 97.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87 138 1.05% 98.95% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-95 137 1.04% 99.98% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::112-119 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::168-175 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 13179 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 13179 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.589650 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.545210 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.294736 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 10247 77.75% 77.75% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 437 3.32% 81.07% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 1119 8.49% 89.56% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 908 6.89% 96.45% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 245 1.86% 98.31% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 119 0.90% 99.21% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 43 0.33% 99.54% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 23 0.17% 99.71% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 15 0.11% 99.83% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 8 0.06% 99.89% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26 5 0.04% 99.92% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27 4 0.03% 99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30 3 0.02% 99.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31 1 0.01% 99.98% # Writes before turning the bus around for reads
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+system.mem_ctrls.rdPerTurnAround::160-167 1 0.01% 100.00% # Reads before turning the bus around for writes
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+system.mem_ctrls.wrPerTurnAround::26 1 0.01% 99.90% # Writes before turning the bus around for reads
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+system.mem_ctrls.wrPerTurnAround::29 1 0.01% 99.95% # Writes before turning the bus around for reads
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system.mem_ctrls.wrPerTurnAround::33 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::34 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 13179 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 69321327 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 80817752 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3025375 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 114.57 # Average queueing delay per DRAM burst
+system.mem_ctrls.wrPerTurnAround::35 1 0.01% 100.00% # Writes before turning the bus around for reads
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+system.mem_ctrls.totQLat 69684050 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 81238919 # Total ticks spent from burst creation until serviced by the DRAM
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+system.mem_ctrls.avgQLat 114.58 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 133.57 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 5232.66 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1890.75 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 5297.39 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1901.86 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 133.58 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 5235.38 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 1893.19 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 5299.31 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1904.10 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 55.65 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 40.88 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 14.77 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 55.69 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 40.90 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 14.79 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 20.94 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 27.75 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 395351 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 211942 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 65.34 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 96.93 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 8.89 # Average gap between requests
-system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1635250680 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 908472600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7547392320 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 2265584256 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 483132000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 5041113516 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 16166400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 17897111772 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 2419.511790 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 159 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 247000 # Time in different power states
+system.mem_ctrls.readRowHits 397850 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 213011 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 65.42 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 96.85 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 8.88 # Average gap between requests
+system.mem_ctrls.pageHitRate 73.77 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 1640640960 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 911467200 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7583122560 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 2278088064 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 485166240 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 5062396176 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 16183800 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 17977065000 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 2420.131050 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 130 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 248040 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 7149848 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 7179981 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 483132000 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 159850800 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 4297947600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 4940930400 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.968970 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 7149960 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 247000 # Time in different power states
+system.mem_ctrls_1.refreshEnergy 485166240 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 160523856 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 4316043600 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 4961733696 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 667.968979 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 7180064 # Time in different power states
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system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.num_reads 99122 # number of read accesses completed
-system.cpu0.num_writes 55082 # number of write accesses completed
-system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 98934 # number of read accesses completed
-system.cpu1.num_writes 54848 # number of write accesses completed
-system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 98977 # number of read accesses completed
-system.cpu2.num_writes 54560 # number of write accesses completed
-system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 99417 # number of read accesses completed
-system.cpu3.num_writes 55431 # number of write accesses completed
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 100000 # number of read accesses completed
-system.cpu4.num_writes 54903 # number of write accesses completed
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 98481 # number of read accesses completed
-system.cpu5.num_writes 55109 # number of write accesses completed
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 98951 # number of read accesses completed
-system.cpu6.num_writes 54779 # number of write accesses completed
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 98318 # number of read accesses completed
-system.cpu7.num_writes 55002 # number of write accesses completed
-system.cpu7.num_copies 0 # number of copy accesses completed
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+system.cpu0.num_writes 54827 # number of write accesses completed
+system.cpu1.num_reads 100000 # number of read accesses completed
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+system.cpu2.num_reads 99662 # number of read accesses completed
+system.cpu2.num_writes 55209 # number of write accesses completed
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+system.cpu3.num_writes 55448 # number of write accesses completed
+system.cpu4.num_reads 99249 # number of read accesses completed
+system.cpu4.num_writes 55511 # number of write accesses completed
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+system.cpu5.num_writes 55584 # number of write accesses completed
+system.cpu6.num_reads 99773 # number of read accesses completed
+system.cpu6.num_writes 55692 # number of write accesses completed
+system.cpu7.num_reads 99764 # number of read accesses completed
+system.cpu7.num_writes 55297 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 623953
-system.ruby.outstanding_req_hist::mean 15.998445
-system.ruby.outstanding_req_hist::gmean 15.997175
-system.ruby.outstanding_req_hist::stdev 0.126144
-system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 26 0.00% 0.02% | 623823 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 623953
+system.ruby.outstanding_req_hist::samples 627101
+system.ruby.outstanding_req_hist::mean 15.998452
+system.ruby.outstanding_req_hist::gmean 15.997188
+system.ruby.outstanding_req_hist::stdev 0.125833
+system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 27 0.00% 0.02% | 626970 99.98% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 627101
system.ruby.latency_hist::bucket_size 2048
system.ruby.latency_hist::max_bucket 20479
-system.ruby.latency_hist::samples 623825
-system.ruby.latency_hist::mean 1518.158580
-system.ruby.latency_hist::gmean 1023.158557
-system.ruby.latency_hist::stdev 1495.268071
-system.ruby.latency_hist | 471692 75.61% 75.61% | 109137 17.49% 93.11% | 31197 5.00% 98.11% | 8878 1.42% 99.53% | 2243 0.36% 99.89% | 516 0.08% 99.97% | 127 0.02% 99.99% | 29 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00%
-system.ruby.latency_hist::total 623825
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+system.ruby.latency_hist::gmean 1021.259356
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+system.ruby.latency_hist | 474274 75.65% 75.65% | 109211 17.42% 93.06% | 31636 5.05% 98.11% | 9009 1.44% 99.55% | 2159 0.34% 99.89% | 565 0.09% 99.98% | 99 0.02% 100.00% | 20 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 626973
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
-system.ruby.hit_latency_hist::samples 108
+system.ruby.hit_latency_hist::samples 124
system.ruby.hit_latency_hist::mean 3
system.ruby.hit_latency_hist::gmean 3.000000
-system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 108 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist::total 108
+system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 124 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist::total 124
system.ruby.miss_latency_hist::bucket_size 2048
system.ruby.miss_latency_hist::max_bucket 20479
-system.ruby.miss_latency_hist::samples 623717
-system.ruby.miss_latency_hist::mean 1518.420938
-system.ruby.miss_latency_hist::gmean 1024.192315
-system.ruby.miss_latency_hist::stdev 1495.264581
-system.ruby.miss_latency_hist | 471584 75.61% 75.61% | 109137 17.50% 93.11% | 31197 5.00% 98.11% | 8878 1.42% 99.53% | 2243 0.36% 99.89% | 516 0.08% 99.97% | 127 0.02% 99.99% | 29 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00%
-system.ruby.miss_latency_hist::total 623717
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 12 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 78021 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78033 # Number of cache demand accesses
+system.ruby.miss_latency_hist::samples 626849
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+system.ruby.miss_latency_hist::gmean 1022.437850
+system.ruby.miss_latency_hist::stdev 1496.119562
+system.ruby.miss_latency_hist | 474150 75.64% 75.64% | 109211 17.42% 93.06% | 31636 5.05% 98.11% | 9009 1.44% 99.55% | 2159 0.34% 99.89% | 565 0.09% 99.98% | 99 0.02% 100.00% | 20 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist::total 626849
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system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
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-system.ruby.l2_cntrl0.L2cache.demand_misses 619174 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 623734 # Number of cache demand accesses
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system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers00.percent_links_utilized 5.796616
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system.ruby.LD.latency_hist::max_bucket 20479
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system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
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system.ruby.LD.hit_latency_hist::mean 3
system.ruby.LD.hit_latency_hist::gmean 3.000000
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system.ruby.LD.miss_latency_hist::bucket_size 2048
system.ruby.LD.miss_latency_hist::max_bucket 20479
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-system.ruby.LD.miss_latency_hist | 303925 75.63% 75.63% | 70241 17.48% 93.11% | 20001 4.98% 98.08% | 5818 1.45% 99.53% | 1467 0.37% 99.90% | 321 0.08% 99.98% | 81 0.02% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00%
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-system.ruby.ST.latency_hist | 167683 75.58% 75.58% | 38896 17.53% 93.11% | 11196 5.05% 98.16% | 3060 1.38% 99.53% | 776 0.35% 99.88% | 195 0.09% 99.97% | 46 0.02% 99.99% | 13 0.01% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
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system.ruby.ST.hit_latency_hist::mean 3
system.ruby.ST.hit_latency_hist::gmean 3.000000
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system.ruby.ST.miss_latency_hist::bucket_size 2048
system.ruby.ST.miss_latency_hist::max_bucket 20479
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-system.ruby.ST.miss_latency_hist | 167659 75.58% 75.58% | 38896 17.53% 93.11% | 11196 5.05% 98.16% | 3060 1.38% 99.53% | 776 0.35% 99.88% | 195 0.09% 99.97% | 46 0.02% 99.99% | 13 0.01% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Directory_Controller.MIS.Dirty_Writeback 100 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50198 12.49% 12.49% | 50329 12.52% 25.01% | 50260 12.50% 37.51% | 50323 12.52% 50.03% | 50663 12.60% 62.63% | 49920 12.42% 75.04% | 50235 12.50% 87.54% | 50089 12.46% 100.00%
-system.ruby.L1Cache_Controller.Load::total 402017
-system.ruby.L1Cache_Controller.Store | 27854 12.55% 12.55% | 27614 12.45% 25.00% | 27687 12.48% 37.48% | 27880 12.57% 50.04% | 27728 12.50% 62.54% | 27882 12.57% 75.10% | 27494 12.39% 87.49% | 27747 12.51% 100.00%
-system.ruby.L1Cache_Controller.Store::total 221886
-system.ruby.L1Cache_Controller.L1_Replacement | 9386167 12.50% 12.50% | 9387429 12.50% 25.00% | 9388272 12.50% 37.51% | 9379351 12.49% 50.00% | 9374313 12.49% 62.48% | 9387856 12.50% 74.99% | 9392579 12.51% 87.50% | 9387972 12.50% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 75083939
-system.ruby.L1Cache_Controller.Fwd_GETX | 167 12.69% 12.69% | 158 12.01% 24.70% | 171 12.99% 37.69% | 153 11.63% 49.32% | 166 12.61% 61.93% | 175 13.30% 75.23% | 168 12.77% 87.99% | 158 12.01% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETX::total 1316
-system.ruby.L1Cache_Controller.Fwd_GETS | 655 11.67% 11.67% | 742 13.22% 24.90% | 703 12.53% 37.43% | 638 11.37% 48.80% | 733 13.06% 61.86% | 704 12.55% 74.41% | 700 12.48% 86.88% | 736 13.12% 100.00%
-system.ruby.L1Cache_Controller.Fwd_GETS::total 5611
-system.ruby.L1Cache_Controller.Inv | 242 13.16% 13.16% | 233 12.67% 25.83% | 235 12.78% 38.61% | 199 10.82% 49.43% | 237 12.89% 62.32% | 244 13.27% 75.58% | 205 11.15% 86.73% | 244 13.27% 100.00%
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-system.ruby.L1Cache_Controller.Data | 49948 12.48% 12.48% | 50137 12.52% 25.00% | 50041 12.50% 37.50% | 50122 12.52% 50.02% | 50438 12.60% 62.62% | 49723 12.42% 75.04% | 50036 12.50% 87.54% | 49872 12.46% 100.00%
-system.ruby.L1Cache_Controller.Data::total 400317
-system.ruby.L1Cache_Controller.Exclusive_Data | 28070 12.56% 12.56% | 27790 12.44% 25.00% | 27889 12.48% 37.49% | 28061 12.56% 50.05% | 27929 12.50% 62.55% | 28056 12.56% 75.11% | 27675 12.39% 87.50% | 27930 12.50% 100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total 223400
-system.ruby.L1Cache_Controller.Writeback_Ack | 678 13.27% 13.27% | 610 11.94% 25.22% | 601 11.77% 36.98% | 683 13.37% 50.35% | 619 12.12% 62.47% | 623 12.20% 74.67% | 633 12.39% 87.06% | 661 12.94% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total 5108
-system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77051 12.50% 12.50% | 77032 12.50% 25.00% | 77045 12.50% 37.50% | 77265 12.54% 50.03% | 77446 12.56% 62.60% | 76863 12.47% 75.07% | 76819 12.46% 87.53% | 76844 12.47% 100.00%
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-system.ruby.L1Cache_Controller.Writeback_Nack | 249 13.13% 13.13% | 248 13.07% 26.20% | 252 13.28% 39.48% | 203 10.70% 50.18% | 240 12.65% 62.84% | 250 13.18% 76.01% | 210 11.07% 87.08% | 245 12.92% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Nack::total 1897
-system.ruby.L1Cache_Controller.All_acks | 27848 12.55% 12.55% | 27610 12.45% 25.00% | 27682 12.48% 37.48% | 27874 12.56% 50.04% | 27725 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00%
-system.ruby.L1Cache_Controller.All_acks::total 221844
-system.ruby.L1Cache_Controller.Use_Timeout | 28069 12.56% 12.56% | 27790 12.44% 25.00% | 27888 12.48% 37.49% | 28061 12.56% 50.05% | 27928 12.50% 62.55% | 28056 12.56% 75.11% | 27675 12.39% 87.50% | 27930 12.50% 100.00%
-system.ruby.L1Cache_Controller.Use_Timeout::total 223397
-system.ruby.L1Cache_Controller.I.Load | 50172 12.48% 12.48% | 50319 12.52% 25.00% | 50249 12.50% 37.51% | 50309 12.52% 50.03% | 50643 12.60% 62.63% | 49905 12.42% 75.05% | 50224 12.50% 87.54% | 50066 12.46% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 401887
-system.ruby.L1Cache_Controller.I.Store | 27846 12.55% 12.55% | 27607 12.45% 25.00% | 27681 12.48% 37.48% | 27875 12.57% 50.04% | 27723 12.50% 62.54% | 27875 12.57% 75.11% | 27487 12.39% 87.50% | 27734 12.50% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 221828
-system.ruby.L1Cache_Controller.I.L1_Replacement | 49 11.45% 11.45% | 54 12.62% 24.07% | 52 12.15% 36.21% | 38 8.88% 45.09% | 71 16.59% 61.68% | 55 12.85% 74.53% | 53 12.38% 86.92% | 56 13.08% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 428
-system.ruby.L1Cache_Controller.S.Load | 4 13.33% 13.33% | 4 13.33% 26.67% | 4 13.33% 40.00% | 2 6.67% 46.67% | 1 3.33% 50.00% | 7 23.33% 73.33% | 1 3.33% 76.67% | 7 23.33% 100.00%
-system.ruby.L1Cache_Controller.S.Load::total 30
-system.ruby.L1Cache_Controller.S.Store | 3 13.64% 13.64% | 3 13.64% 27.27% | 2 9.09% 36.36% | 1 4.55% 40.91% | 2 9.09% 50.00% | 2 9.09% 59.09% | 4 18.18% 77.27% | 5 22.73% 100.00%
-system.ruby.L1Cache_Controller.S.Store::total 22
-system.ruby.L1Cache_Controller.S.L1_Replacement | 49939 12.48% 12.48% | 50125 12.52% 25.00% | 50030 12.50% 37.50% | 50115 12.52% 50.02% | 50424 12.60% 62.62% | 49714 12.42% 75.04% | 50028 12.50% 87.54% | 49858 12.46% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 400233
-system.ruby.L1Cache_Controller.S.Fwd_GETS | 43 12.72% 12.72% | 41 12.13% 24.85% | 42 12.43% 37.28% | 41 12.13% 49.41% | 37 10.95% 60.36% | 43 12.72% 73.08% | 48 14.20% 87.28% | 43 12.72% 100.00%
-system.ruby.L1Cache_Controller.S.Fwd_GETS::total 338
-system.ruby.L1Cache_Controller.S.Inv | 6 11.11% 11.11% | 7 12.96% 24.07% | 8 14.81% 38.89% | 5 9.26% 48.15% | 10 18.52% 66.67% | 6 11.11% 77.78% | 4 7.41% 85.19% | 8 14.81% 100.00%
-system.ruby.L1Cache_Controller.S.Inv::total 54
-system.ruby.L1Cache_Controller.O.L1_Replacement | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 1
-system.ruby.L1Cache_Controller.M.L1_Replacement | 221 14.26% 14.26% | 179 11.55% 25.81% | 205 13.23% 39.03% | 187 12.06% 51.10% | 204 13.16% 64.26% | 181 11.68% 75.94% | 182 11.74% 87.68% | 191 12.32% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 1550
-system.ruby.L1Cache_Controller.M.Fwd_GETS | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total 5
-system.ruby.L1Cache_Controller.M_W.L1_Replacement | 591 14.10% 14.10% | 590 14.08% 28.18% | 722 17.23% 45.41% | 352 8.40% 53.81% | 599 14.29% 68.10% | 348 8.30% 76.40% | 686 16.37% 92.77% | 303 7.23% 100.00%
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-system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 2
-system.ruby.L1Cache_Controller.M_W.Use_Timeout | 222 14.27% 14.27% | 180 11.57% 25.84% | 207 13.30% 39.14% | 187 12.02% 51.16% | 204 13.11% 64.27% | 181 11.63% 75.90% | 184 11.83% 87.72% | 191 12.28% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1556
-system.ruby.L1Cache_Controller.MM.Load | 2 8.70% 8.70% | 2 8.70% 17.39% | 3 13.04% 30.43% | 5 21.74% 52.17% | 3 13.04% 65.22% | 2 8.70% 73.91% | 2 8.70% 82.61% | 4 17.39% 100.00%
-system.ruby.L1Cache_Controller.MM.Load::total 23
-system.ruby.L1Cache_Controller.MM.Store | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 2 28.57% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00%
-system.ruby.L1Cache_Controller.MM.Store::total 7
-system.ruby.L1Cache_Controller.MM.L1_Replacement | 27804 12.55% 12.55% | 27563 12.45% 25.00% | 27637 12.48% 37.48% | 27840 12.57% 50.05% | 27663 12.49% 62.54% | 27826 12.56% 75.11% | 27443 12.39% 87.50% | 27691 12.50% 100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total 221467
-system.ruby.L1Cache_Controller.MM.Fwd_GETX | 17 14.41% 14.41% | 16 13.56% 27.97% | 14 11.86% 39.83% | 14 11.86% 51.69% | 20 16.95% 68.64% | 11 9.32% 77.97% | 15 12.71% 90.68% | 11 9.32% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 118
-system.ruby.L1Cache_Controller.MM.Fwd_GETS | 26 10.16% 10.16% | 31 12.11% 22.27% | 30 11.72% 33.98% | 19 7.42% 41.41% | 41 16.02% 57.42% | 38 14.84% 72.27% | 34 13.28% 85.55% | 37 14.45% 100.00%
-system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 256
-system.ruby.L1Cache_Controller.MM_W.Load | 3 9.68% 9.68% | 4 12.90% 22.58% | 2 6.45% 29.03% | 4 12.90% 41.94% | 5 16.13% 58.06% | 3 9.68% 67.74% | 4 12.90% 80.65% | 6 19.35% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total 31
-system.ruby.L1Cache_Controller.MM_W.Store | 2 12.50% 12.50% | 1 6.25% 18.75% | 2 12.50% 31.25% | 1 6.25% 37.50% | 0 0.00% 37.50% | 4 25.00% 62.50% | 2 12.50% 75.00% | 4 25.00% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Store::total 16
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 611213 12.52% 12.52% | 604769 12.39% 24.91% | 614347 12.59% 37.50% | 608910 12.48% 49.98% | 611746 12.53% 62.51% | 610049 12.50% 75.01% | 610144 12.50% 87.51% | 609423 12.49% 100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4880601
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 13 11.61% 11.61% | 15 13.39% 25.00% | 19 16.96% 41.96% | 10 8.93% 50.89% | 18 16.07% 66.96% | 16 14.29% 81.25% | 11 9.82% 91.07% | 10 8.93% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 112
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 20 10.10% 10.10% | 22 11.11% 21.21% | 21 10.61% 31.82% | 20 10.10% 41.92% | 29 14.65% 56.57% | 28 14.14% 70.71% | 32 16.16% 86.87% | 26 13.13% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 198
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27847 12.55% 12.55% | 27610 12.45% 25.00% | 27681 12.48% 37.48% | 27874 12.56% 50.04% | 27724 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 221841
-system.ruby.L1Cache_Controller.IM.L1_Replacement | 3117685 12.52% 12.52% | 3071171 12.34% 24.86% | 3120650 12.54% 37.40% | 3140383 12.62% 50.02% | 3099421 12.45% 62.47% | 3146089 12.64% 75.11% | 3088522 12.41% 87.51% | 3108221 12.49% 100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total 24892142
-system.ruby.L1Cache_Controller.IM.Ack | 144 12.04% 12.04% | 147 12.29% 24.33% | 138 11.54% 35.87% | 150 12.54% 48.41% | 150 12.54% 60.95% | 142 11.87% 72.83% | 153 12.79% 85.62% | 172 14.38% 100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total 1196
-system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27845 12.55% 12.55% | 27607 12.45% 25.00% | 27680 12.48% 37.48% | 27873 12.57% 50.04% | 27723 12.50% 62.54% | 27873 12.57% 75.11% | 27487 12.39% 87.50% | 27734 12.50% 100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 221822
-system.ruby.L1Cache_Controller.SM.L1_Replacement | 733 19.03% 19.03% | 966 25.08% 44.11% | 395 10.25% 54.36% | 251 6.52% 60.88% | 202 5.24% 66.12% | 281 7.29% 73.42% | 679 17.63% 91.04% | 345 8.96% 100.00%
-system.ruby.L1Cache_Controller.SM.L1_Replacement::total 3852
-system.ruby.L1Cache_Controller.SM.Exclusive_Data | 3 13.64% 13.64% | 3 13.64% 27.27% | 2 9.09% 36.36% | 1 4.55% 40.91% | 2 9.09% 50.00% | 2 9.09% 59.09% | 4 18.18% 77.27% | 5 22.73% 100.00%
-system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 22
-system.ruby.L1Cache_Controller.OM.L1_Replacement | 22520 12.98% 12.98% | 21779 12.56% 25.54% | 21024 12.12% 37.66% | 21826 12.58% 50.25% | 21159 12.20% 62.45% | 22530 12.99% 75.44% | 21258 12.26% 87.70% | 21336 12.30% 100.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement::total 173432
-system.ruby.L1Cache_Controller.OM.Ack | 220 11.91% 11.91% | 222 12.02% 23.93% | 215 11.64% 35.57% | 244 13.21% 48.78% | 236 12.78% 61.56% | 247 13.37% 74.93% | 218 11.80% 86.74% | 245 13.26% 100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total 1847
-system.ruby.L1Cache_Controller.OM.All_acks | 27848 12.55% 12.55% | 27610 12.45% 25.00% | 27682 12.48% 37.48% | 27874 12.56% 50.04% | 27725 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00%
-system.ruby.L1Cache_Controller.OM.All_acks::total 221844
-system.ruby.L1Cache_Controller.IS.L1_Replacement | 5555411 12.48% 12.48% | 5610232 12.61% 25.09% | 5553208 12.48% 37.57% | 5529449 12.42% 49.99% | 5562824 12.50% 62.49% | 5530783 12.43% 74.92% | 5593583 12.57% 87.48% | 5570548 12.52% 100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44506038
-system.ruby.L1Cache_Controller.IS.Data | 49948 12.48% 12.48% | 50137 12.52% 25.00% | 50041 12.50% 37.50% | 50122 12.52% 50.02% | 50438 12.60% 62.62% | 49723 12.42% 75.04% | 50036 12.50% 87.54% | 49872 12.46% 100.00%
-system.ruby.L1Cache_Controller.IS.Data::total 400317
-system.ruby.L1Cache_Controller.IS.Exclusive_Data | 222 14.27% 14.27% | 180 11.57% 25.84% | 207 13.30% 39.14% | 187 12.02% 51.16% | 204 13.11% 64.27% | 181 11.63% 75.90% | 184 11.83% 87.72% | 191 12.28% 100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1556
-system.ruby.L1Cache_Controller.SI.Load | 12 37.50% 37.50% | 0 0.00% 37.50% | 2 6.25% 43.75% | 0 0.00% 43.75% | 11 34.38% 78.12% | 3 9.38% 87.50% | 3 9.38% 96.88% | 1 3.12% 100.00%
-system.ruby.L1Cache_Controller.SI.Load::total 32
-system.ruby.L1Cache_Controller.SI.Store | 0 0.00% 0.00% | 3 42.86% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00%
-system.ruby.L1Cache_Controller.SI.Store::total 7
-system.ruby.L1Cache_Controller.SI.Fwd_GETS | 329 11.65% 11.65% | 363 12.85% 24.50% | 347 12.29% 36.79% | 329 11.65% 48.44% | 389 13.77% 62.22% | 358 12.68% 74.89% | 337 11.93% 86.83% | 372 13.17% 100.00%
-system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2824
-system.ruby.L1Cache_Controller.SI.Inv | 236 13.22% 13.22% | 226 12.66% 25.88% | 227 12.72% 38.60% | 194 10.87% 49.47% | 227 12.72% 62.18% | 238 13.33% 75.52% | 201 11.26% 86.78% | 236 13.22% 100.00%
-system.ruby.L1Cache_Controller.SI.Inv::total 1785
-system.ruby.L1Cache_Controller.SI.Writeback_Ack | 675 13.24% 13.24% | 609 11.95% 25.19% | 601 11.79% 36.98% | 683 13.40% 50.37% | 618 12.12% 62.50% | 620 12.16% 74.66% | 632 12.40% 87.05% | 660 12.95% 100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5098
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49027 12.46% 12.46% | 49290 12.53% 24.99% | 49202 12.51% 37.50% | 49238 12.52% 50.02% | 49579 12.60% 62.63% | 48856 12.42% 75.05% | 49193 12.51% 87.55% | 48962 12.45% 100.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 393347
-system.ruby.L1Cache_Controller.OI.Fwd_GETX | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 6
-system.ruby.L1Cache_Controller.OI.Fwd_GETS | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 6
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 233 11.76% 11.76% | 285 14.39% 26.15% | 263 13.28% 39.42% | 227 11.46% 50.88% | 236 11.91% 62.80% | 234 11.81% 74.61% | 247 12.47% 87.08% | 256 12.92% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1981
-system.ruby.L1Cache_Controller.OI.Writeback_Nack | 14 11.86% 11.86% | 22 18.64% 30.51% | 24 20.34% 50.85% | 9 7.63% 58.47% | 14 11.86% 70.34% | 15 12.71% 83.05% | 10 8.47% 91.53% | 10 8.47% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 118
-system.ruby.L1Cache_Controller.MI.Load | 5 35.71% 35.71% | 0 0.00% 35.71% | 0 0.00% 35.71% | 3 21.43% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 1 7.14% 64.29% | 5 35.71% 100.00%
-system.ruby.L1Cache_Controller.MI.Load::total 14
-system.ruby.L1Cache_Controller.MI.Store | 2 50.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.MI.Store::total 4
-system.ruby.L1Cache_Controller.MI.Fwd_GETX | 136 12.59% 12.59% | 127 11.76% 24.35% | 138 12.78% 37.13% | 128 11.85% 48.98% | 128 11.85% 60.83% | 147 13.61% 74.44% | 141 13.06% 87.50% | 135 12.50% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1080
-system.ruby.L1Cache_Controller.MI.Fwd_GETS | 233 11.76% 11.76% | 284 14.33% 26.08% | 261 13.17% 39.25% | 228 11.50% 50.76% | 236 11.91% 62.66% | 235 11.86% 74.52% | 247 12.46% 86.98% | 258 13.02% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1982
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27656 12.57% 12.57% | 27331 12.43% 25.00% | 27443 12.48% 37.48% | 27671 12.58% 50.06% | 27503 12.50% 62.56% | 27625 12.56% 75.12% | 27237 12.38% 87.50% | 27489 12.50% 100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 219955
-system.ruby.L1Cache_Controller.II.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.II.Store::total 1
-system.ruby.L1Cache_Controller.II.Writeback_Ack | 3 30.00% 30.00% | 1 10.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack::total 10
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 135 12.48% 12.48% | 126 11.65% 24.12% | 137 12.66% 36.78% | 129 11.92% 48.71% | 128 11.83% 60.54% | 148 13.68% 74.21% | 142 13.12% 87.34% | 137 12.66% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1082
-system.ruby.L1Cache_Controller.II.Writeback_Nack | 235 13.21% 13.21% | 226 12.70% 25.91% | 228 12.82% 38.73% | 194 10.91% 49.63% | 226 12.70% 62.34% | 235 13.21% 75.55% | 200 11.24% 86.79% | 235 13.21% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1779
-system.ruby.L2Cache_Controller.L1_GETS 499463 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 277459 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTO 132 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 259037 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 475631 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS 24927 0.00% 0.00%
-system.ruby.L2Cache_Controller.All_Acks 219934 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 612544 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 393347 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 221936 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Ack 219920 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 406502 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 223397 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 683777 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 392621 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 216702 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETS 3162 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_GETX 1833 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 390198 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS 3149 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETS 2243 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_GETX 1198 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTX 221036 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILX.L1_PUTS 1768 0.00% 0.00%
+system.ruby.ST.miss_latency_hist::samples 223117
+system.ruby.ST.miss_latency_hist::mean 1521.385390
+system.ruby.ST.miss_latency_hist::gmean 1028.276933
+system.ruby.ST.miss_latency_hist::stdev 1494.530566
+system.ruby.ST.miss_latency_hist | 168705 75.61% 75.61% | 38961 17.46% 93.07% | 11269 5.05% 98.13% | 3169 1.42% 99.55% | 770 0.35% 99.89% | 204 0.09% 99.98% | 34 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist::total 223117
+system.ruby.Directory_Controller.GETX 221210 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 394374 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 221085 0.00% 0.00%
+system.ruby.Directory_Controller.PUTO_SHARERS 105 0.00% 0.00%
+system.ruby.Directory_Controller.Unblock 143614 0.00% 0.00%
+system.ruby.Directory_Controller.Last_Unblock 250750 0.00% 0.00%
+system.ruby.Directory_Controller.Exclusive_Unblock 221198 0.00% 0.00%
+system.ruby.Directory_Controller.Dirty_Writeback 221184 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 615577 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 221184 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 78802 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETS 143619 0.00% 0.00%
+system.ruby.Directory_Controller.I.Memory_Ack 220913 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETX 142401 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETS 250755 0.00% 0.00%
+system.ruby.Directory_Controller.S.Memory_Ack 105 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 221085 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTO_SHARERS 105 0.00% 0.00%
+system.ruby.Directory_Controller.IS.GETX 3 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Unblock 143614 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Memory_Data 143619 0.00% 0.00%
+system.ruby.Directory_Controller.IS.Memory_Ack 100 0.00% 0.00%
+system.ruby.Directory_Controller.SS.GETX 3 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock 250750 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Memory_Data 250755 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock 221198 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Memory_Data 221203 0.00% 0.00%
+system.ruby.Directory_Controller.MM.Memory_Ack 66 0.00% 0.00%
+system.ruby.Directory_Controller.MI.GETX 1 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback 221079 0.00% 0.00%
+system.ruby.Directory_Controller.MIS.Dirty_Writeback 105 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load | 50428 12.48% 12.48% | 50682 12.55% 25.03% | 50615 12.53% 37.56% | 50552 12.51% 50.08% | 50377 12.47% 62.55% | 50216 12.43% 74.98% | 50557 12.52% 87.49% | 50520 12.51% 100.00%
+system.ruby.L1Cache_Controller.Load::total 403947
+system.ruby.L1Cache_Controller.Store | 27645 12.39% 12.39% | 27771 12.44% 24.83% | 27753 12.44% 37.27% | 27971 12.53% 49.80% | 28068 12.58% 62.38% | 28075 12.58% 74.96% | 28004 12.55% 87.50% | 27887 12.50% 100.00%
+system.ruby.L1Cache_Controller.Store::total 223174
+system.ruby.L1Cache_Controller.L1_Replacement | 9437024 12.51% 12.51% | 9428542 12.50% 25.01% | 9430070 12.50% 37.51% | 9427922 12.50% 50.01% | 9423979 12.49% 62.50% | 9433022 12.51% 75.01% | 9422446 12.49% 87.50% | 9430776 12.50% 100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total 75433781
+system.ruby.L1Cache_Controller.Fwd_GETX | 160 12.60% 12.60% | 161 12.68% 25.28% | 194 15.28% 40.55% | 145 11.42% 51.97% | 163 12.83% 64.80% | 138 10.87% 75.67% | 160 12.60% 88.27% | 149 11.73% 100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total 1270
+system.ruby.L1Cache_Controller.Fwd_GETS | 733 12.79% 12.79% | 762 13.29% 26.08% | 712 12.42% 38.50% | 692 12.07% 50.58% | 706 12.32% 62.89% | 717 12.51% 75.40% | 715 12.47% 87.88% | 695 12.12% 100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total 5732
+system.ruby.L1Cache_Controller.Inv | 240 13.36% 13.36% | 243 13.52% 26.88% | 208 11.57% 38.45% | 215 11.96% 50.42% | 211 11.74% 62.16% | 209 11.63% 73.79% | 218 12.13% 85.92% | 253 14.08% 100.00%
+system.ruby.L1Cache_Controller.Inv::total 1797
+system.ruby.L1Cache_Controller.Ack | 356 11.97% 11.97% | 379 12.75% 24.72% | 377 12.68% 37.40% | 373 12.55% 49.95% | 365 12.28% 62.23% | 398 13.39% 75.61% | 364 12.24% 87.86% | 361 12.14% 100.00%
+system.ruby.L1Cache_Controller.Ack::total 2973
+system.ruby.L1Cache_Controller.Data | 50238 12.49% 12.49% | 50469 12.55% 25.04% | 50418 12.54% 37.57% | 50300 12.51% 50.08% | 50156 12.47% 62.55% | 49994 12.43% 74.98% | 50340 12.52% 87.50% | 50293 12.50% 100.00%
+system.ruby.L1Cache_Controller.Data::total 402208
+system.ruby.L1Cache_Controller.Exclusive_Data | 27794 12.37% 12.37% | 27962 12.45% 24.82% | 27928 12.43% 37.25% | 28156 12.53% 49.79% | 28263 12.58% 62.37% | 28254 12.58% 74.94% | 28204 12.56% 87.50% | 28080 12.50% 100.00%
+system.ruby.L1Cache_Controller.Exclusive_Data::total 224641
+system.ruby.L1Cache_Controller.Writeback_Ack | 665 12.82% 12.82% | 665 12.82% 25.64% | 683 13.16% 38.80% | 624 12.03% 50.83% | 614 11.84% 62.66% | 679 13.09% 75.75% | 631 12.16% 87.91% | 627 12.09% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total 5188
+system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77086 12.44% 12.44% | 77469 12.51% 24.95% | 77398 12.49% 37.44% | 77574 12.52% 49.97% | 77552 12.52% 62.49% | 77313 12.48% 74.97% | 77638 12.53% 87.50% | 77435 12.50% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 619465
+system.ruby.L1Cache_Controller.Writeback_Nack | 247 13.53% 13.53% | 243 13.31% 26.83% | 211 11.56% 38.39% | 220 12.05% 50.44% | 211 11.56% 61.99% | 217 11.88% 73.88% | 226 12.38% 86.25% | 251 13.75% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Nack::total 1826
+system.ruby.L1Cache_Controller.All_acks | 27633 12.38% 12.38% | 27766 12.44% 24.83% | 27743 12.43% 37.26% | 27965 12.53% 49.80% | 28063 12.58% 62.38% | 28062 12.58% 74.95% | 28003 12.55% 87.50% | 27882 12.50% 100.00%
+system.ruby.L1Cache_Controller.All_acks::total 223117
+system.ruby.L1Cache_Controller.Use_Timeout | 27792 12.37% 12.37% | 27962 12.45% 24.82% | 27928 12.43% 37.25% | 28155 12.53% 49.79% | 28263 12.58% 62.37% | 28254 12.58% 74.94% | 28204 12.56% 87.50% | 28079 12.50% 100.00%
+system.ruby.L1Cache_Controller.Use_Timeout::total 224637
+system.ruby.L1Cache_Controller.I.Load | 50399 12.48% 12.48% | 50665 12.55% 25.03% | 50603 12.53% 37.57% | 50491 12.51% 50.07% | 50359 12.47% 62.54% | 50188 12.43% 74.97% | 50544 12.52% 87.49% | 50494 12.51% 100.00%
+system.ruby.L1Cache_Controller.I.Load::total 403743
+system.ruby.L1Cache_Controller.I.Store | 27633 12.39% 12.39% | 27766 12.45% 24.83% | 27743 12.43% 37.27% | 27964 12.53% 49.80% | 28062 12.58% 62.38% | 28062 12.58% 74.95% | 27999 12.55% 87.50% | 27879 12.50% 100.00%
+system.ruby.L1Cache_Controller.I.Store::total 223108
+system.ruby.L1Cache_Controller.I.L1_Replacement | 48 11.03% 11.03% | 61 14.02% 25.06% | 58 13.33% 38.39% | 46 10.57% 48.97% | 52 11.95% 60.92% | 51 11.72% 72.64% | 54 12.41% 85.06% | 65 14.94% 100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total 435
+system.ruby.L1Cache_Controller.S.Load | 6 11.76% 11.76% | 6 11.76% 23.53% | 5 9.80% 33.33% | 6 11.76% 45.10% | 6 11.76% 56.86% | 11 21.57% 78.43% | 6 11.76% 90.20% | 5 9.80% 100.00%
+system.ruby.L1Cache_Controller.S.Load::total 51
+system.ruby.L1Cache_Controller.S.Store | 0 0.00% 0.00% | 2 12.50% 12.50% | 3 18.75% 31.25% | 2 12.50% 43.75% | 1 6.25% 50.00% | 1 6.25% 56.25% | 4 25.00% 81.25% | 3 18.75% 100.00%
+system.ruby.L1Cache_Controller.S.Store::total 16
+system.ruby.L1Cache_Controller.S.L1_Replacement | 50228 12.49% 12.49% | 50453 12.55% 25.04% | 50408 12.54% 37.57% | 50291 12.51% 50.08% | 50143 12.47% 62.55% | 49984 12.43% 74.98% | 50328 12.52% 87.50% | 50277 12.50% 100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total 402112
+system.ruby.L1Cache_Controller.S.Fwd_GETS | 45 11.94% 11.94% | 60 15.92% 27.85% | 56 14.85% 42.71% | 42 11.14% 53.85% | 40 10.61% 64.46% | 39 10.34% 74.80% | 55 14.59% 89.39% | 40 10.61% 100.00%
+system.ruby.L1Cache_Controller.S.Fwd_GETS::total 377
+system.ruby.L1Cache_Controller.S.Inv | 9 12.50% 12.50% | 12 16.67% 29.17% | 6 8.33% 37.50% | 5 6.94% 44.44% | 12 16.67% 61.11% | 8 11.11% 72.22% | 7 9.72% 81.94% | 13 18.06% 100.00%
+system.ruby.L1Cache_Controller.S.Inv::total 72
+system.ruby.L1Cache_Controller.M.L1_Replacement | 160 10.53% 10.53% | 195 12.83% 23.36% | 185 12.17% 35.53% | 191 12.57% 48.09% | 199 13.09% 61.18% | 192 12.63% 73.82% | 200 13.16% 86.97% | 198 13.03% 100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total 1520
+system.ruby.L1Cache_Controller.M.Fwd_GETX | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4
+system.ruby.L1Cache_Controller.M_W.L1_Replacement | 465 10.98% 10.98% | 530 12.51% 23.49% | 698 16.48% 39.98% | 505 11.92% 51.90% | 529 12.49% 64.39% | 418 9.87% 74.26% | 568 13.41% 87.67% | 522 12.33% 100.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 4235
+system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 4
+system.ruby.L1Cache_Controller.M_W.Use_Timeout | 161 10.56% 10.56% | 196 12.86% 23.43% | 185 12.14% 35.56% | 191 12.53% 48.10% | 200 13.12% 61.22% | 192 12.60% 73.82% | 201 13.19% 87.01% | 198 12.99% 100.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1524
+system.ruby.L1Cache_Controller.MM.Load | 1 7.69% 7.69% | 2 15.38% 23.08% | 3 23.08% 46.15% | 3 23.08% 69.23% | 0 0.00% 69.23% | 2 15.38% 84.62% | 0 0.00% 84.62% | 2 15.38% 100.00%
+system.ruby.L1Cache_Controller.MM.Load::total 13
+system.ruby.L1Cache_Controller.MM.Store | 2 18.18% 18.18% | 0 0.00% 18.18% | 4 36.36% 54.55% | 3 27.27% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.MM.Store::total 11
+system.ruby.L1Cache_Controller.MM.L1_Replacement | 27592 12.39% 12.39% | 27718 12.44% 24.83% | 27691 12.43% 37.26% | 27923 12.54% 49.80% | 28023 12.58% 62.38% | 28019 12.58% 74.96% | 27957 12.55% 87.51% | 27829 12.49% 100.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222752
+system.ruby.L1Cache_Controller.MM.Fwd_GETX | 12 9.92% 9.92% | 20 16.53% 26.45% | 26 21.49% 47.93% | 11 9.09% 57.02% | 13 10.74% 67.77% | 8 6.61% 74.38% | 16 13.22% 87.60% | 15 12.40% 100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 121
+system.ruby.L1Cache_Controller.MM.Fwd_GETS | 26 10.92% 10.92% | 28 11.76% 22.69% | 26 10.92% 33.61% | 30 12.61% 46.22% | 26 10.92% 57.14% | 35 14.71% 71.85% | 30 12.61% 84.45% | 37 15.55% 100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 238
+system.ruby.L1Cache_Controller.MM_W.Load | 3 8.82% 8.82% | 5 14.71% 23.53% | 3 8.82% 32.35% | 6 17.65% 50.00% | 3 8.82% 58.82% | 6 17.65% 76.47% | 5 14.71% 91.18% | 3 8.82% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total 34
+system.ruby.L1Cache_Controller.MM_W.Store | 2 13.33% 13.33% | 3 20.00% 33.33% | 2 13.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 1 6.67% 80.00% | 1 6.67% 86.67% | 2 13.33% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Store::total 15
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 613663 12.48% 12.48% | 608323 12.37% 24.85% | 616946 12.54% 37.39% | 613237 12.47% 49.86% | 617680 12.56% 62.42% | 618886 12.58% 75.01% | 616731 12.54% 87.55% | 612440 12.45% 100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4917906
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 15 16.67% 16.67% | 9 10.00% 26.67% | 17 18.89% 45.56% | 3 3.33% 48.89% | 8 8.89% 57.78% | 13 14.44% 72.22% | 18 20.00% 92.22% | 7 7.78% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 90
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 18 8.18% 8.18% | 34 15.45% 23.64% | 35 15.91% 39.55% | 19 8.64% 48.18% | 25 11.36% 59.55% | 28 12.73% 72.27% | 28 12.73% 85.00% | 33 15.00% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 220
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27631 12.38% 12.38% | 27766 12.44% 24.83% | 27743 12.43% 37.26% | 27964 12.53% 49.80% | 28063 12.58% 62.38% | 28062 12.58% 74.95% | 28003 12.55% 87.50% | 27881 12.50% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 223113
+system.ruby.L1Cache_Controller.IM.L1_Replacement | 3100083 12.39% 12.39% | 3100594 12.39% 24.78% | 3114295 12.44% 37.22% | 3131272 12.51% 49.73% | 3172501 12.68% 62.41% | 3140503 12.55% 74.95% | 3129364 12.50% 87.46% | 3139161 12.54% 100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total 25027773
+system.ruby.L1Cache_Controller.IM.Ack | 130 11.00% 11.00% | 152 12.86% 23.86% | 136 11.51% 35.36% | 148 12.52% 47.88% | 143 12.10% 59.98% | 166 14.04% 74.03% | 155 13.11% 87.14% | 152 12.86% 100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total 1182
+system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27633 12.39% 12.39% | 27764 12.44% 24.83% | 27740 12.43% 37.26% | 27963 12.53% 49.80% | 28062 12.58% 62.38% | 28061 12.58% 74.95% | 27999 12.55% 87.50% | 27879 12.50% 100.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 223101
+system.ruby.L1Cache_Controller.SM.L1_Replacement | 0 0.00% 0.00% | 577 21.47% 21.47% | 301 11.20% 32.66% | 296 11.01% 43.68% | 399 14.84% 58.52% | 0 0.00% 58.52% | 838 31.18% 89.69% | 277 10.31% 100.00%
+system.ruby.L1Cache_Controller.SM.L1_Replacement::total 2688
+system.ruby.L1Cache_Controller.SM.Exclusive_Data | 0 0.00% 0.00% | 2 12.50% 12.50% | 3 18.75% 31.25% | 2 12.50% 43.75% | 1 6.25% 50.00% | 1 6.25% 56.25% | 4 25.00% 81.25% | 3 18.75% 100.00%
+system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 16
+system.ruby.L1Cache_Controller.OM.L1_Replacement | 21719 12.56% 12.56% | 21417 12.39% 24.95% | 21539 12.46% 37.42% | 21504 12.44% 49.86% | 22297 12.90% 62.76% | 21631 12.51% 75.27% | 21846 12.64% 87.91% | 20903 12.09% 100.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement::total 172856
+system.ruby.L1Cache_Controller.OM.Ack | 226 12.62% 12.62% | 227 12.67% 25.29% | 241 13.46% 38.75% | 225 12.56% 51.31% | 222 12.40% 63.71% | 232 12.95% 76.66% | 209 11.67% 88.33% | 209 11.67% 100.00%
+system.ruby.L1Cache_Controller.OM.Ack::total 1791
+system.ruby.L1Cache_Controller.OM.All_acks | 27633 12.38% 12.38% | 27766 12.44% 24.83% | 27743 12.43% 37.26% | 27965 12.53% 49.80% | 28063 12.58% 62.38% | 28062 12.58% 74.95% | 28003 12.55% 87.50% | 27882 12.50% 100.00%
+system.ruby.L1Cache_Controller.OM.All_acks::total 223117
+system.ruby.L1Cache_Controller.IS.L1_Replacement | 5623066 12.58% 12.58% | 5618674 12.57% 25.16% | 5597949 12.53% 37.69% | 5582657 12.49% 50.18% | 5532156 12.38% 62.56% | 5573338 12.47% 75.04% | 5574560 12.48% 87.51% | 5579104 12.49% 100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44681504
+system.ruby.L1Cache_Controller.IS.Data | 50238 12.49% 12.49% | 50469 12.55% 25.04% | 50418 12.54% 37.57% | 50300 12.51% 50.08% | 50156 12.47% 62.55% | 49994 12.43% 74.98% | 50340 12.52% 87.50% | 50293 12.50% 100.00%
+system.ruby.L1Cache_Controller.IS.Data::total 402208
+system.ruby.L1Cache_Controller.IS.Exclusive_Data | 161 10.56% 10.56% | 196 12.86% 23.43% | 185 12.14% 35.56% | 191 12.53% 48.10% | 200 13.12% 61.22% | 192 12.60% 73.82% | 201 13.19% 87.01% | 198 12.99% 100.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1524
+system.ruby.L1Cache_Controller.SI.Load | 17 18.09% 18.09% | 2 2.13% 20.21% | 1 1.06% 21.28% | 46 48.94% 70.21% | 3 3.19% 73.40% | 8 8.51% 81.91% | 1 1.06% 82.98% | 16 17.02% 100.00%
+system.ruby.L1Cache_Controller.SI.Load::total 94
+system.ruby.L1Cache_Controller.SI.Store | 1 6.25% 6.25% | 0 0.00% 6.25% | 0 0.00% 6.25% | 1 6.25% 12.50% | 1 6.25% 18.75% | 10 62.50% 81.25% | 0 0.00% 81.25% | 3 18.75% 100.00%
+system.ruby.L1Cache_Controller.SI.Store::total 16
+system.ruby.L1Cache_Controller.SI.Fwd_GETS | 393 13.54% 13.54% | 384 13.23% 26.77% | 337 11.61% 38.39% | 357 12.30% 50.69% | 382 13.16% 63.85% | 357 12.30% 76.15% | 346 11.92% 88.08% | 346 11.92% 100.00%
+system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2902
+system.ruby.L1Cache_Controller.SI.Inv | 231 13.39% 13.39% | 231 13.39% 26.78% | 202 11.71% 38.49% | 210 12.17% 50.67% | 199 11.54% 62.20% | 201 11.65% 73.86% | 211 12.23% 86.09% | 240 13.91% 100.00%
+system.ruby.L1Cache_Controller.SI.Inv::total 1725
+system.ruby.L1Cache_Controller.SI.Writeback_Ack | 663 12.81% 12.81% | 663 12.81% 25.61% | 681 13.15% 38.77% | 621 12.00% 50.76% | 614 11.86% 62.62% | 678 13.10% 75.72% | 630 12.17% 87.89% | 627 12.11% 100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5177
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49334 12.48% 12.48% | 49558 12.54% 25.02% | 49523 12.53% 37.55% | 49460 12.52% 50.07% | 49330 12.48% 62.55% | 49103 12.42% 74.98% | 49485 12.52% 87.50% | 49409 12.50% 100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 395202
+system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.OI.Load::total 1
+system.ruby.L1Cache_Controller.OI.Fwd_GETX | 1 25.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 4
+system.ruby.L1Cache_Controller.OI.Fwd_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 42.86% 42.86% | 3 42.86% 85.71% | 1 14.29% 100.00%
+system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 7
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 250 12.60% 12.60% | 256 12.90% 25.50% | 257 12.95% 38.46% | 243 12.25% 50.71% | 233 11.74% 62.45% | 254 12.80% 75.25% | 253 12.75% 88.00% | 238 12.00% 100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1984
+system.ruby.L1Cache_Controller.OI.Writeback_Nack | 18 16.82% 16.82% | 13 12.15% 28.97% | 11 10.28% 39.25% | 13 12.15% 51.40% | 12 11.21% 62.62% | 16 14.95% 77.57% | 13 12.15% 89.72% | 11 10.28% 100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 107
+system.ruby.L1Cache_Controller.MI.Load | 2 18.18% 18.18% | 2 18.18% 36.36% | 0 0.00% 36.36% | 0 0.00% 36.36% | 6 54.55% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.MI.Load::total 11
+system.ruby.L1Cache_Controller.MI.Store | 7 87.50% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.MI.Store::total 8
+system.ruby.L1Cache_Controller.MI.Fwd_GETX | 131 12.51% 12.51% | 131 12.51% 25.02% | 150 14.33% 39.35% | 130 12.42% 51.77% | 139 13.28% 65.04% | 116 11.08% 76.12% | 123 11.75% 87.87% | 127 12.13% 100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1047
+system.ruby.L1Cache_Controller.MI.Fwd_GETS | 251 12.63% 12.63% | 256 12.88% 25.50% | 258 12.98% 38.48% | 244 12.27% 50.75% | 233 11.72% 62.47% | 255 12.83% 75.30% | 253 12.73% 88.03% | 238 11.97% 100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1988
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27370 12.37% 12.37% | 27525 12.44% 24.81% | 27467 12.42% 37.23% | 27740 12.54% 49.77% | 27850 12.59% 62.36% | 27840 12.58% 74.94% | 27780 12.56% 87.50% | 27661 12.50% 100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 221233
+system.ruby.L1Cache_Controller.II.Writeback_Ack | 2 18.18% 18.18% | 2 18.18% 36.36% | 2 18.18% 54.55% | 3 27.27% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack::total 11
+system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 132 12.62% 12.62% | 130 12.43% 25.05% | 151 14.44% 39.48% | 131 12.52% 52.01% | 139 13.29% 65.30% | 116 11.09% 76.39% | 120 11.47% 87.86% | 127 12.14% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1046
+system.ruby.L1Cache_Controller.II.Writeback_Nack | 229 13.32% 13.32% | 230 13.38% 26.70% | 200 11.63% 38.34% | 207 12.04% 50.38% | 199 11.58% 61.95% | 201 11.69% 73.65% | 213 12.39% 86.04% | 240 13.96% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1719
+system.ruby.L2Cache_Controller.L1_GETS 504171 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 275912 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTO 107 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 259606 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 476434 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS 25911 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 221202 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 615574 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 395202 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 223217 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 221184 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 408438 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 224639 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 691372 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 394374 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 218066 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETS 3279 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETX 1785 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 391942 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS 3260 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETS 2226 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETX 1172 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 222279 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTS 1711 0.00% 0.00%
system.ruby.L2Cache_Controller.ILOX.L1_GETS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_GETX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTO 119 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTX 118 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOX.L1_PUTS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_GETS 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_PUTO 107 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_PUTX 107 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_GETS 6 0.00% 0.00%
system.ruby.L2Cache_Controller.ILOSX.L1_GETX 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1859 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 122 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 12 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS 2531 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETX 1394 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 389456 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_GETS 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1877 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 108 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS 2539 0.00% 0.00%
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+system.ruby.L2Cache_Controller.OLSX.L1_GETS 7 0.00% 0.00%
system.ruby.L2Cache_Controller.OLSX.L1_GETX 6 0.00% 0.00%
system.ruby.L2Cache_Controller.OLSX.L1_PUTX 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1756 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L1_PUTS 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSX.L2_Replacement 100 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETS 18 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_GETX 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3189 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L1_PUTS 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLS.L2_Replacement 2482 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1300 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 701 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_PUTX 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_PUTS 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 219827 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_GETS 17 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_GETX 29 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1686 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_PUTS 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 119 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOXW.Unblock 122 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 50 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 86 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4049 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 30 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1862 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILOSXW.Unblock 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.L1_PUTS 112 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.Unblock 22 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSW.L2_Replacement 161 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1766 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTS 14 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L2_Replacement 105 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETS 19 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETX 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3262 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L2_Replacement 2529 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1286 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 733 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_PUTX 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_PUTS 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 221085 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_GETS 16 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1506 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 107 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.Unblock 108 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 63 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 22 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 51 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4580 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 40 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1877 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.Unblock 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSW.L1_PUTS 181 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSW.Unblock 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSW.L2_Replacement 216 0.00% 0.00%
system.ruby.L2Cache_Controller.ILSW.L1_GETS 182 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_GETX 82 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_PUTS 11381 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3149 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_GETS 16447 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_GETX 9062 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 390198 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L1_GETS 110 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L1_GETX 77 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.Unblock 3189 0.00% 0.00%
-system.ruby.L2Cache_Controller.SW.L2_Replacement 21395 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L1_GETS 57 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L1_GETX 14 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L1_PUTS 9 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.Unblock 1756 0.00% 0.00%
-system.ruby.L2Cache_Controller.OXW.L2_Replacement 8852 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.Unblock 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 25 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETS 6054 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_GETX 3511 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1623 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_PUTS 74 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 219955 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILXW.Unblock 1081 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_GETS 208 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_GETX 115 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28820 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.L1_PUTS 125 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLS.Unblock 3162 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 58 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILSW.L1_GETX 38 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILSW.L1_PUTS 12129 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3260 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_GETS 17001 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_GETX 8674 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 391942 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.L1_GETS 85 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.L1_GETX 48 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.Unblock 3262 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.L2_Replacement 23310 0.00% 0.00%
+system.ruby.L2Cache_Controller.OXW.L1_GETS 53 0.00% 0.00%
+system.ruby.L2Cache_Controller.OXW.L1_GETX 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.OXW.Unblock 1766 0.00% 0.00%
+system.ruby.L2Cache_Controller.OXW.L2_Replacement 9523 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 36 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXW.Unblock 14 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 30 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETS 5974 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETX 3491 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1648 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_PUTS 55 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 221233 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.Unblock 1046 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.L1_GETS 334 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.L1_GETX 125 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28471 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.L1_PUTS 247 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.Unblock 3279 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 52 0.00% 0.00%
system.ruby.L2Cache_Controller.IFLOX.Unblock 1 0.00% 0.00%
system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 6 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 110 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 197 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 32397 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 242 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Unblock 1987 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1456 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 63 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 56 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLOSX.Unblock 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 34 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 176 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 102 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 31904 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 233 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.Unblock 1988 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1410 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 66 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 27 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOSX.Unblock 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 52 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_PUTS_only 27 0.00% 0.00%
system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.L1_GETS 46072 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.L1_GETX 26880 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.L1_PUTS 7566 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 392610 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 392604 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.L1_GETS 21372 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.L1_GETX 11875 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGM.Data 218092 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_GETS 349 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_GETX 222 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 30376 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 232 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMLS.Data 1842 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_GETS 5603 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_GETX 3146 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTX 121 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16651 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.L1_PUTS 147 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.All_Acks 219934 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 219930 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.L1_GETS 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.L1_GETX 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 701 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 52 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 25 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_PUTS 27 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.Unblock 2531 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement 30081 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.L1_GETS 46 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1300 0.00% 0.00%
-system.ruby.L2Cache_Controller.OO.L2_Replacement 11341 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 14 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSXS.Unblock 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 74 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.Unblock 18 0.00% 0.00%
-system.ruby.L2Cache_Controller.SLSS.L2_Replacement 57 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.L1_GETS 845 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.L1_GETX 345 0.00% 0.00%
-system.ruby.L2Cache_Controller.MI.Writeback_Ack 219820 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 268 0.00% 0.00%
-system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 100 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.L1_GETS 48391 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.L1_GETX 25584 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.L1_PUTS 7638 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 394372 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 394365 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.L1_GETS 21742 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.L1_GETX 11283 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 219409 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.L1_GETS 259 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.L1_GETX 100 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 29748 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 186 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.Data 1793 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_GETS 5594 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_GETX 2911 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_PUTX 103 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16081 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_PUTS 139 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 221202 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 221200 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 733 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS 42 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_PUTS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.Unblock 2539 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement 31218 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.L1_GETX 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.L1_PUTX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1286 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.L2_Replacement 11948 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXS.Unblock 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 44 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSS.Unblock 19 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSS.L2_Replacement 93 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.L1_GETS 522 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.L1_GETX 392 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 221079 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 326 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 105 0.00% 0.00%
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.005881 # Number of seconds simulated
-sim_ticks 5881067 # Number of ticks simulated
-final_tick 5881067 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.005861 # Number of seconds simulated
+sim_ticks 5861055 # Number of ticks simulated
+final_tick 5861055 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 67797 # Simulator tick rate (ticks/s)
-host_mem_usage 666544 # Number of bytes of host memory used
-host_seconds 86.75 # Real time elapsed on the host
+host_tick_rate 95295 # Simulator tick rate (ticks/s)
+host_mem_usage 485672 # Number of bytes of host memory used
+host_seconds 61.50 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39867264 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 39867264 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 15562240 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 15562240 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 622926 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 622926 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 243160 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 243160 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 6778916819 # Total read bandwidth from this memory (bytes/s)
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-system.mem_ctrls.bytesPerActivate::mean 216.889807 # Bytes accessed per row activation
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-system.mem_ctrls.bytesPerActivate::256-383 54326 21.57% 84.42% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 23433 9.30% 93.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 9848 3.91% 97.63% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 3794 1.51% 99.14% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1414 0.56% 99.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 496 0.20% 99.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 265 0.11% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 251857 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 14692 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 41.747345 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 38.046520 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 17.572329 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-7 293 1.99% 1.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-15 32 0.22% 2.21% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23 40 0.27% 2.48% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-31 3171 21.58% 24.07% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-39 6167 41.98% 66.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::40-47 1682 11.45% 77.49% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-55 182 1.24% 78.73% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::56-63 909 6.19% 84.92% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-71 1233 8.39% 93.31% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79 536 3.65% 96.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87 119 0.81% 97.77% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::88-95 74 0.50% 98.27% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::96-103 108 0.74% 99.01% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::104-111 74 0.50% 99.51% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::112-119 42 0.29% 99.80% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::120-127 16 0.11% 99.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::128-135 8 0.05% 99.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::136-143 4 0.03% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::144-151 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::152-159 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 14692 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 14692 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.343929 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.300692 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.322873 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 13317 90.64% 90.64% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 342 2.33% 92.97% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 211 1.44% 94.41% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 210 1.43% 95.83% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 177 1.20% 97.04% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 136 0.93% 97.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 103 0.70% 98.67% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 66 0.45% 99.12% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 56 0.38% 99.50% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 38 0.26% 99.75% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26 17 0.12% 99.87% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27 7 0.05% 99.92% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28 6 0.04% 99.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29 3 0.02% 99.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30 2 0.01% 99.99% # Writes before turning the bus around for reads
+system.mem_ctrls.wrQLenPdf::62 1 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::63 1 # What write queue length does an incoming req see
+system.mem_ctrls.bytesPerActivate::samples 250748 # Bytes accessed per row activation
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+system.mem_ctrls.bytesPerActivate::0-127 50160 20.00% 20.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 107083 42.71% 62.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 54285 21.65% 84.36% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 23329 9.30% 93.66% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 9881 3.94% 97.60% # Bytes accessed per row activation
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+system.mem_ctrls.bytesPerActivate::1024-1151 290 0.12% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 250748 # Bytes accessed per row activation
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+system.mem_ctrls.rdPerTurnAround::0-7 305 2.08% 2.08% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::8-15 32 0.22% 2.30% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23 27 0.18% 2.48% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-31 3189 21.72% 24.20% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::32-39 6160 41.95% 66.15% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::40-47 1671 11.38% 77.53% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::48-55 181 1.23% 78.76% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::56-63 914 6.22% 84.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-71 1223 8.33% 93.32% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::72-79 546 3.72% 97.04% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87 109 0.74% 97.78% # Reads before turning the bus around for writes
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+system.mem_ctrls.rdPerTurnAround::96-103 107 0.73% 99.13% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::104-111 71 0.48% 99.61% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::112-119 20 0.14% 99.75% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::120-127 25 0.17% 99.92% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::128-135 9 0.06% 99.98% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::136-143 2 0.01% 99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::144-151 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 14683 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 14683 # Writes before turning the bus around for reads
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+system.mem_ctrls.wrPerTurnAround::16 13340 90.85% 90.85% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 298 2.03% 92.88% # Writes before turning the bus around for reads
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+system.mem_ctrls.wrPerTurnAround::20 179 1.22% 97.15% # Writes before turning the bus around for reads
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+system.mem_ctrls.wrPerTurnAround::22 82 0.56% 98.70% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23 86 0.59% 99.28% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24 47 0.32% 99.60% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25 28 0.19% 99.80% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26 10 0.07% 99.86% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::27 9 0.06% 99.93% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28 5 0.03% 99.96% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::29 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::30 4 0.03% 99.99% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 14692 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 62376294 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 74030970 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3067020 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 101.69 # Average queueing delay per DRAM burst
+system.mem_ctrls.wrPerTurnAround::total 14683 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 62104397 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 73728103 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3058870 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 101.52 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 120.69 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 6675.29 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 2613.13 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 6779.06 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 2646.16 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 120.52 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 6680.29 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 2618.80 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 6784.73 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 2652.79 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 72.57 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 52.15 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 20.42 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 72.65 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 52.19 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 20.46 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 15.37 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 29.97 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 367104 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 234563 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 59.85 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 97.67 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 6.79 # Average gap between requests
-system.mem_ctrls.pageHitRate 70.49 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1903252680 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 1057362600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7652062080 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 2488610304 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 383962800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 4006574460 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 12703200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 17504528124 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 2977.600142 # Core power per rank (mW)
+system.mem_ctrls.avgWrQLen 30.05 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 366603 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 234242 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 59.92 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 97.66 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 6.78 # Average gap between requests
+system.mem_ctrls.pageHitRate 70.55 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 1894029480 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 1052238600 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 7627626240 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 2483809920 # Energy for write commands per rank (pJ)
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+system.mem_ctrls_0.actBackEnergy 3990635208 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 12680400 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 17443456968 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 2979.039670 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 196300 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 195520 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 5682429 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 5659868 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 383962800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 127039320 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3415767600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 3926769720 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.968386 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5682390 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 196300 # Time in different power states
+system.mem_ctrls_1.refreshEnergy 382437120 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 126534528 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 3402195600 # Energy for precharge background per rank (pJ)
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+system.mem_ctrls_1.averagePower 667.968375 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 5659812 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 195520 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.num_reads 99830 # number of read accesses completed
-system.cpu0.num_writes 55806 # number of write accesses completed
-system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 99618 # number of read accesses completed
-system.cpu1.num_writes 55383 # number of write accesses completed
-system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 99329 # number of read accesses completed
-system.cpu2.num_writes 55521 # number of write accesses completed
-system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 99531 # number of read accesses completed
-system.cpu3.num_writes 55301 # number of write accesses completed
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 99485 # number of read accesses completed
-system.cpu4.num_writes 55398 # number of write accesses completed
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 99702 # number of read accesses completed
-system.cpu5.num_writes 55198 # number of write accesses completed
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 99965 # number of read accesses completed
-system.cpu6.num_writes 55754 # number of write accesses completed
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 100000 # number of read accesses completed
-system.cpu7.num_writes 54827 # number of write accesses completed
-system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 98982 # number of read accesses completed
+system.cpu0.num_writes 55308 # number of write accesses completed
+system.cpu1.num_reads 100000 # number of read accesses completed
+system.cpu1.num_writes 55392 # number of write accesses completed
+system.cpu2.num_reads 99114 # number of read accesses completed
+system.cpu2.num_writes 55497 # number of write accesses completed
+system.cpu3.num_reads 99168 # number of read accesses completed
+system.cpu3.num_writes 55352 # number of write accesses completed
+system.cpu4.num_reads 99493 # number of read accesses completed
+system.cpu4.num_writes 54983 # number of write accesses completed
+system.cpu5.num_reads 99075 # number of read accesses completed
+system.cpu5.num_writes 55346 # number of write accesses completed
+system.cpu6.num_reads 99096 # number of read accesses completed
+system.cpu6.num_writes 54949 # number of write accesses completed
+system.cpu7.num_reads 99018 # number of read accesses completed
+system.cpu7.num_writes 54930 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 627379
-system.ruby.outstanding_req_hist::mean 15.998465
-system.ruby.outstanding_req_hist::gmean 15.997202
-system.ruby.outstanding_req_hist::stdev 0.125755
-system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 19 0.00% 0.02% | 627256 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 627379
+system.ruby.outstanding_req_hist::samples 625828
+system.ruby.outstanding_req_hist::mean 15.998460
+system.ruby.outstanding_req_hist::gmean 15.997194
+system.ruby.outstanding_req_hist::stdev 0.125917
+system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 20 0.00% 0.02% | 625704 99.98% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 625828
system.ruby.latency_hist::bucket_size 512
system.ruby.latency_hist::max_bucket 5119
-system.ruby.latency_hist::samples 627251
-system.ruby.latency_hist::mean 1199.957633
-system.ruby.latency_hist::gmean 899.316988
-system.ruby.latency_hist::stdev 764.936546
-system.ruby.latency_hist | 169441 27.01% 27.01% | 117906 18.80% 45.81% | 113026 18.02% 63.83% | 119501 19.05% 82.88% | 85523 13.63% 96.52% | 20392 3.25% 99.77% | 1432 0.23% 100.00% | 30 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 627251
+system.ruby.latency_hist::samples 625700
+system.ruby.latency_hist::mean 1198.832377
+system.ruby.latency_hist::gmean 899.836581
+system.ruby.latency_hist::stdev 764.001734
+system.ruby.latency_hist | 168514 26.93% 26.93% | 119446 19.09% 46.02% | 111629 17.84% 63.86% | 119695 19.13% 82.99% | 84495 13.50% 96.50% | 20461 3.27% 99.77% | 1425 0.23% 99.99% | 34 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 625700
system.ruby.hit_latency_hist::bucket_size 512
system.ruby.hit_latency_hist::max_bucket 5119
-system.ruby.hit_latency_hist::samples 2844
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-system.ruby.hit_latency_hist::gmean 516.362786
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system.ruby.miss_latency_hist::bucket_size 512
system.ruby.miss_latency_hist::max_bucket 5119
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system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
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system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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system.ruby.network.routers01.msg_count.Response_Control::4 88
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system.ruby.network.routers01.msg_bytes.Response_Control::4 704
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system.ruby.LD.hit_latency_hist::bucket_size 512
system.ruby.LD.hit_latency_hist::max_bucket 5119
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system.ruby.LD.miss_latency_hist::bucket_size 512
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system.ruby.ST.hit_latency_hist::bucket_size 512
system.ruby.ST.hit_latency_hist::max_bucket 5119
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system.ruby.ST.miss_latency_hist::max_bucket 5119
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system.ruby.L1Cache.hit_mach_latency_hist::mean 2
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system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119
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system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
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system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9
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system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119
-system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 401461
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-system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 903.160221
-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 764.822834
-system.ruby.LD.Directory.miss_type_mach_latency_hist | 107915 26.88% 26.88% | 75783 18.88% 45.76% | 72421 18.04% 63.80% | 76331 19.01% 82.81% | 54919 13.68% 96.49% | 13153 3.28% 99.77% | 921 0.23% 100.00% | 18 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
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system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2
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system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119
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-system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 136 31.26% 31.26% | 85 19.54% 50.80% | 71 16.32% 67.13% | 76 17.47% 84.60% | 49 11.26% 95.86% | 16 3.68% 99.54% | 2 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512
system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119
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system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119
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-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 764.240219
-system.ruby.ST.Directory.miss_type_mach_latency_hist | 60155 27.14% 27.14% | 41367 18.66% 45.80% | 39942 18.02% 63.82% | 42449 19.15% 82.97% | 30108 13.58% 96.56% | 7121 3.21% 99.77% | 501 0.23% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Directory_Controller.GETX 237437 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 430203 0.00% 0.00%
-system.ruby.Directory_Controller.Lockdown 44403 0.00% 0.00%
-system.ruby.Directory_Controller.Unlockdown 44053 0.00% 0.00%
-system.ruby.Directory_Controller.Data_Owner 298 0.00% 0.00%
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-system.ruby.Directory_Controller.Ack_Owner 529 0.00% 0.00%
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-system.ruby.Directory_Controller.Tokens 147 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_All_Tokens 777 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 622922 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 243159 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETX 220129 0.00% 0.00%
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+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 763.843702
+system.ruby.ST.Directory.miss_type_mach_latency_hist | 59416 26.81% 26.81% | 42205 19.04% 45.85% | 39630 17.88% 63.73% | 42500 19.17% 82.90% | 30120 13.59% 96.49% | 7261 3.28% 99.77% | 504 0.23% 99.99% | 12 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.Directory_Controller.O.Data_All_Tokens 60 0.00% 0.00%
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-system.ruby.Directory_Controller.NO.Lockdown 17540 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Data_Owner 298 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Data_All_Tokens 242862 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner 529 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 378819 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Tokens 139 0.00% 0.00%
-system.ruby.Directory_Controller.L.GETX 127 0.00% 0.00%
-system.ruby.Directory_Controller.L.GETS 205 0.00% 0.00%
-system.ruby.Directory_Controller.L.Lockdown 318 0.00% 0.00%
-system.ruby.Directory_Controller.L.Unlockdown 44051 0.00% 0.00%
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system.ruby.Directory_Controller.L.Tokens 2 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.GETX 72 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.GETS 89 0.00% 0.00%
-system.ruby.Directory_Controller.O_W.Lockdown 106 0.00% 0.00%
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system.ruby.Directory_Controller.O_W.Tokens 1 0.00% 0.00%
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-system.ruby.Directory_Controller.O_W.Memory_Ack 243053 0.00% 0.00%
-system.ruby.Directory_Controller.L_O_W.GETX 48 0.00% 0.00%
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-system.ruby.Directory_Controller.L_O_W.Lockdown 4 0.00% 0.00%
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-system.ruby.Directory_Controller.L_O_W.Memory_Data 4229 0.00% 0.00%
-system.ruby.Directory_Controller.L_O_W.Memory_Ack 106 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.GETX 466 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.GETS 814 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.Lockdown 28 0.00% 0.00%
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-system.ruby.Directory_Controller.NO_W.GETS 26409 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown 22674 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 15 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data 596017 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50549 12.51% 12.51% | 50655 12.53% 25.04% | 50543 12.51% 37.55% | 50433 12.48% 50.03% | 50597 12.52% 62.55% | 50378 12.47% 75.01% | 50321 12.45% 87.46% | 50661 12.54% 100.00%
-system.ruby.L1Cache_Controller.Load::total 404137
-system.ruby.L1Cache_Controller.Store | 28221 12.65% 12.65% | 27757 12.44% 25.09% | 28028 12.56% 37.65% | 27656 12.39% 50.04% | 27664 12.40% 62.44% | 27998 12.55% 74.99% | 28169 12.62% 87.61% | 27643 12.39% 100.00%
-system.ruby.L1Cache_Controller.Store::total 223136
-system.ruby.L1Cache_Controller.L1_Replacement | 1480088 12.55% 12.55% | 1475888 12.52% 25.07% | 1476913 12.53% 37.60% | 1470392 12.47% 50.07% | 1471389 12.48% 62.55% | 1471572 12.48% 75.03% | 1471675 12.48% 87.51% | 1472167 12.49% 100.00%
-system.ruby.L1Cache_Controller.L1_Replacement::total 11790084
-system.ruby.L1Cache_Controller.Data_Shared | 197 12.48% 12.48% | 200 12.67% 25.14% | 199 12.60% 37.75% | 194 12.29% 50.03% | 203 12.86% 62.89% | 182 11.53% 74.41% | 203 12.86% 87.27% | 201 12.73% 100.00%
-system.ruby.L1Cache_Controller.Data_Shared::total 1579
-system.ruby.L1Cache_Controller.Data_Owner | 29 10.03% 10.03% | 45 15.57% 25.61% | 42 14.53% 40.14% | 29 10.03% 50.17% | 39 13.49% 63.67% | 26 9.00% 72.66% | 40 13.84% 86.51% | 39 13.49% 100.00%
+system.ruby.Directory_Controller.O_W.Ack_All_Tokens 2 0.00% 0.00%
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+system.ruby.Directory_Controller.L_O_W.Memory_Data 4224 0.00% 0.00%
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+system.ruby.Directory_Controller.L_NO_W.GETX 495 0.00% 0.00%
+system.ruby.Directory_Controller.L_NO_W.GETS 954 0.00% 0.00%
+system.ruby.Directory_Controller.L_NO_W.Lockdown 35 0.00% 0.00%
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+system.ruby.Directory_Controller.NO_W.Memory_Data 594537 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load | 50092 12.44% 12.44% | 50720 12.60% 25.04% | 50362 12.51% 37.55% | 50243 12.48% 50.03% | 50550 12.56% 62.59% | 50015 12.42% 75.01% | 50346 12.51% 87.52% | 50237 12.48% 100.00%
+system.ruby.L1Cache_Controller.Load::total 402565
+system.ruby.L1Cache_Controller.Store | 28010 12.55% 12.55% | 28064 12.58% 25.13% | 28024 12.56% 37.69% | 27802 12.46% 50.14% | 27671 12.40% 62.54% | 28081 12.58% 75.13% | 27742 12.43% 87.56% | 27760 12.44% 100.00%
+system.ruby.L1Cache_Controller.Store::total 223154
+system.ruby.L1Cache_Controller.L1_Replacement | 1468380 12.49% 12.49% | 1481332 12.60% 25.08% | 1472761 12.52% 37.61% | 1468524 12.49% 50.09% | 1470130 12.50% 62.59% | 1467500 12.48% 75.07% | 1468017 12.48% 87.55% | 1463638 12.45% 100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total 11760282
+system.ruby.L1Cache_Controller.Data_Shared | 197 12.64% 12.64% | 195 12.52% 25.16% | 194 12.45% 37.61% | 178 11.42% 49.04% | 190 12.20% 61.23% | 196 12.58% 73.81% | 203 13.03% 86.84% | 205 13.16% 100.00%
+system.ruby.L1Cache_Controller.Data_Shared::total 1558
+system.ruby.L1Cache_Controller.Data_Owner | 28 9.69% 9.69% | 43 14.88% 24.57% | 30 10.38% 34.95% | 39 13.49% 48.44% | 33 11.42% 59.86% | 38 13.15% 73.01% | 33 11.42% 84.43% | 45 15.57% 100.00%
system.ruby.L1Cache_Controller.Data_Owner::total 289
-system.ruby.L1Cache_Controller.Data_All_Tokens | 82668 12.56% 12.56% | 82207 12.49% 25.06% | 82439 12.53% 37.59% | 81884 12.44% 50.03% | 82153 12.49% 62.52% | 82236 12.50% 75.02% | 82293 12.51% 87.52% | 82094 12.48% 100.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens::total 657974
-system.ruby.L1Cache_Controller.Ack | 2 20.00% 20.00% | 2 20.00% 40.00% | 1 10.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 10
-system.ruby.L1Cache_Controller.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens | 81911 12.48% 12.48% | 82621 12.59% 25.08% | 82201 12.53% 37.61% | 81831 12.47% 50.08% | 82005 12.50% 62.58% | 81869 12.48% 75.05% | 81876 12.48% 87.53% | 81790 12.47% 100.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens::total 656104
+system.ruby.L1Cache_Controller.Ack | 0 0.00% 0.00% | 2 16.67% 16.67% | 0 0.00% 16.67% | 3 25.00% 41.67% | 1 8.33% 50.00% | 0 0.00% 50.00% | 2 16.67% 66.67% | 4 33.33% 100.00%
+system.ruby.L1Cache_Controller.Ack::total 12
+system.ruby.L1Cache_Controller.Ack_All_Tokens | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
system.ruby.L1Cache_Controller.Ack_All_Tokens::total 3
-system.ruby.L1Cache_Controller.Transient_Local_GETX | 194854 12.48% 12.48% | 195320 12.51% 24.99% | 195053 12.49% 37.48% | 195420 12.52% 49.99% | 195412 12.51% 62.51% | 195080 12.49% 75.00% | 194909 12.48% 87.48% | 195435 12.52% 100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1561483
-system.ruby.L1Cache_Controller.Transient_Local_GETS | 353483 12.50% 12.50% | 353371 12.49% 24.99% | 353489 12.50% 37.49% | 353602 12.50% 50.00% | 353436 12.50% 62.49% | 353654 12.50% 75.00% | 353706 12.51% 87.50% | 353373 12.50% 100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2828114
-system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
-system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 5
-system.ruby.L1Cache_Controller.Persistent_GETX | 13783 12.49% 12.49% | 13801 12.51% 25.00% | 13756 12.47% 37.47% | 13761 12.47% 49.95% | 13777 12.49% 62.43% | 13755 12.47% 74.90% | 13894 12.59% 87.49% | 13796 12.51% 100.00%
-system.ruby.L1Cache_Controller.Persistent_GETX::total 110323
-system.ruby.L1Cache_Controller.Persistent_GETS | 24943 12.44% 12.44% | 25035 12.49% 24.93% | 25044 12.49% 37.42% | 25123 12.53% 49.95% | 25028 12.48% 62.43% | 25059 12.50% 74.93% | 25085 12.51% 87.44% | 25178 12.56% 100.00%
-system.ruby.L1Cache_Controller.Persistent_GETS::total 200495
-system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 4
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 49729 12.53% 12.53% | 49620 12.50% 25.04% | 49656 12.51% 37.55% | 49571 12.49% 50.04% | 49651 12.51% 62.55% | 49641 12.51% 75.06% | 49476 12.47% 87.53% | 49482 12.47% 100.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 396826
-system.ruby.L1Cache_Controller.Request_Timeout | 33619 12.37% 12.37% | 34306 12.62% 24.99% | 34435 12.67% 37.65% | 33457 12.31% 49.96% | 34654 12.75% 62.71% | 33427 12.30% 75.00% | 34346 12.63% 87.64% | 33609 12.36% 100.00%
-system.ruby.L1Cache_Controller.Request_Timeout::total 271853
-system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 6 10.71% 10.71% | 5 8.93% 19.64% | 6 10.71% 30.36% | 7 12.50% 42.86% | 8 14.29% 57.14% | 6 10.71% 67.86% | 8 14.29% 82.14% | 10 17.86% 100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 56
-system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 7 5.15% 5.15% | 17 12.50% 17.65% | 15 11.03% 28.68% | 13 9.56% 38.24% | 12 8.82% 47.06% | 25 18.38% 65.44% | 23 16.91% 82.35% | 24 17.65% 100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 136
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78528 12.56% 12.56% | 78156 12.50% 25.06% | 78311 12.53% 37.59% | 77846 12.45% 50.04% | 78001 12.48% 62.51% | 78123 12.50% 75.01% | 78233 12.51% 87.52% | 78034 12.48% 100.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 625232
-system.ruby.L1Cache_Controller.NP.Load | 50509 12.51% 12.51% | 50627 12.54% 25.04% | 50510 12.51% 37.55% | 50389 12.48% 50.03% | 50551 12.52% 62.55% | 50342 12.47% 75.02% | 50285 12.45% 87.47% | 50606 12.53% 100.00%
-system.ruby.L1Cache_Controller.NP.Load::total 403819
-system.ruby.L1Cache_Controller.NP.Store | 28202 12.65% 12.65% | 27742 12.44% 25.09% | 28001 12.56% 37.65% | 27633 12.39% 50.04% | 27642 12.40% 62.44% | 27971 12.55% 74.99% | 28144 12.62% 87.61% | 27623 12.39% 100.00%
-system.ruby.L1Cache_Controller.NP.Store::total 222958
-system.ruby.L1Cache_Controller.NP.Data_Shared | 11 8.59% 8.59% | 18 14.06% 22.66% | 19 14.84% 37.50% | 14 10.94% 48.44% | 16 12.50% 60.94% | 8 6.25% 67.19% | 23 17.97% 85.16% | 19 14.84% 100.00%
-system.ruby.L1Cache_Controller.NP.Data_Shared::total 128
-system.ruby.L1Cache_Controller.NP.Data_Owner | 6 7.14% 7.14% | 14 16.67% 23.81% | 11 13.10% 36.90% | 10 11.90% 48.81% | 12 14.29% 63.10% | 5 5.95% 69.05% | 13 15.48% 84.52% | 13 15.48% 100.00%
-system.ruby.L1Cache_Controller.NP.Data_Owner::total 84
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 4108 12.67% 12.67% | 4005 12.35% 25.02% | 4095 12.63% 37.64% | 3999 12.33% 49.97% | 4120 12.70% 62.68% | 4067 12.54% 75.22% | 4023 12.40% 87.62% | 4014 12.38% 100.00%
-system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 32431
-system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 2 50.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.NP.Ack::total 4
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194378 12.48% 12.48% | 194859 12.51% 24.99% | 194607 12.49% 37.48% | 194968 12.52% 49.99% | 194930 12.51% 62.51% | 194649 12.49% 75.00% | 194495 12.48% 87.48% | 194975 12.52% 100.00%
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1557861
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 352691 12.50% 12.50% | 352515 12.49% 24.99% | 352621 12.50% 37.49% | 352784 12.50% 50.00% | 352579 12.50% 62.49% | 352819 12.50% 75.00% | 352925 12.51% 87.51% | 352525 12.49% 100.00%
-system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2821459
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 43402 12.49% 12.49% | 43438 12.50% 24.98% | 43495 12.51% 37.49% | 43450 12.50% 49.99% | 43468 12.50% 62.50% | 43442 12.50% 75.00% | 43468 12.50% 87.50% | 43449 12.50% 100.00%
-system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 347612
-system.ruby.L1Cache_Controller.I.L1_Replacement | 83 12.46% 12.46% | 85 12.76% 25.23% | 90 13.51% 38.74% | 71 10.66% 49.40% | 86 12.91% 62.31% | 92 13.81% 76.13% | 74 11.11% 87.24% | 85 12.76% 100.00%
-system.ruby.L1Cache_Controller.I.L1_Replacement::total 666
-system.ruby.L1Cache_Controller.I.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
-system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 2
-system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 2
-system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 2
-system.ruby.L1Cache_Controller.I.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.I.Persistent_GETX::total 2
-system.ruby.L1Cache_Controller.S.L1_Replacement | 197 12.19% 12.19% | 208 12.87% 25.06% | 195 12.07% 37.13% | 202 12.50% 49.63% | 209 12.93% 62.56% | 196 12.13% 74.69% | 206 12.75% 87.44% | 203 12.56% 100.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement::total 1616
-system.ruby.L1Cache_Controller.S.Data_Shared | 4 21.05% 21.05% | 2 10.53% 31.58% | 2 10.53% 42.11% | 4 21.05% 63.16% | 2 10.53% 73.68% | 2 10.53% 84.21% | 1 5.26% 89.47% | 2 10.53% 100.00%
-system.ruby.L1Cache_Controller.S.Data_Shared::total 19
-system.ruby.L1Cache_Controller.S.Data_All_Tokens | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 2 40.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
-system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 5
-system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 3
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
-system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 5
-system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETX::total 1
-system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 4
-system.ruby.L1Cache_Controller.O.L1_Replacement | 63 11.98% 11.98% | 79 15.02% 27.00% | 69 13.12% 40.11% | 63 11.98% 52.09% | 69 13.12% 65.21% | 55 10.46% 75.67% | 56 10.65% 86.31% | 72 13.69% 100.00%
-system.ruby.L1Cache_Controller.O.L1_Replacement::total 526
-system.ruby.L1Cache_Controller.O.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 2
-system.ruby.L1Cache_Controller.O.Ack | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETX | 195106 12.49% 12.49% | 195050 12.49% 24.98% | 195093 12.49% 37.47% | 195313 12.51% 49.98% | 195440 12.51% 62.49% | 195030 12.49% 74.98% | 195367 12.51% 87.49% | 195357 12.51% 100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1561756
+system.ruby.L1Cache_Controller.Transient_Local_GETS | 352347 12.51% 12.51% | 351718 12.49% 24.99% | 352073 12.50% 37.49% | 352195 12.50% 50.00% | 351891 12.49% 62.49% | 352426 12.51% 75.00% | 352090 12.50% 87.50% | 352196 12.50% 100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2816936
+system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00%
+system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 4
+system.ruby.L1Cache_Controller.Persistent_GETX | 13616 12.50% 12.50% | 13644 12.52% 25.02% | 13615 12.50% 37.52% | 13572 12.46% 49.97% | 13607 12.49% 62.46% | 13620 12.50% 74.96% | 13688 12.56% 87.53% | 13592 12.47% 100.00%
+system.ruby.L1Cache_Controller.Persistent_GETX::total 108954
+system.ruby.L1Cache_Controller.Persistent_GETS | 24975 12.49% 12.49% | 24920 12.47% 24.96% | 24971 12.49% 37.45% | 24992 12.50% 49.96% | 25025 12.52% 62.48% | 25035 12.52% 75.00% | 25004 12.51% 87.51% | 24964 12.49% 100.00%
+system.ruby.L1Cache_Controller.Persistent_GETS::total 199886
+system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 3
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 49211 12.50% 12.50% | 49238 12.51% 25.01% | 49216 12.50% 37.52% | 49238 12.51% 50.03% | 49170 12.49% 62.52% | 49145 12.49% 75.01% | 49110 12.48% 87.49% | 49245 12.51% 100.00%
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 393573
+system.ruby.L1Cache_Controller.Request_Timeout | 33208 12.52% 12.52% | 33841 12.76% 25.27% | 33107 12.48% 37.75% | 32943 12.42% 50.17% | 33071 12.47% 62.64% | 33150 12.50% 75.14% | 33269 12.54% 87.68% | 32690 12.32% 100.00%
+system.ruby.L1Cache_Controller.Request_Timeout::total 265279
+system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 5 5.95% 5.95% | 11 13.10% 19.05% | 8 9.52% 28.57% | 9 10.71% 39.29% | 15 17.86% 57.14% | 10 11.90% 69.05% | 10 11.90% 80.95% | 16 19.05% 100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 84
+system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 9 7.26% 7.26% | 6 4.84% 12.10% | 13 10.48% 22.58% | 12 9.68% 32.26% | 24 19.35% 51.61% | 23 18.55% 70.16% | 18 14.52% 84.68% | 19 15.32% 100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 124
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 77853 12.48% 12.48% | 78535 12.59% 25.08% | 78143 12.53% 37.60% | 77810 12.48% 50.08% | 77949 12.50% 62.58% | 77828 12.48% 75.06% | 77835 12.48% 87.54% | 77726 12.46% 100.00%
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 623679
+system.ruby.L1Cache_Controller.NP.Load | 50055 12.44% 12.44% | 50685 12.60% 25.04% | 50318 12.51% 37.55% | 50200 12.48% 50.03% | 50501 12.55% 62.59% | 49984 12.43% 75.01% | 50303 12.51% 87.52% | 50198 12.48% 100.00%
+system.ruby.L1Cache_Controller.NP.Load::total 402244
+system.ruby.L1Cache_Controller.NP.Store | 27993 12.55% 12.55% | 28040 12.57% 25.13% | 28001 12.56% 37.68% | 27785 12.46% 50.14% | 27658 12.40% 62.54% | 28065 12.58% 75.13% | 27732 12.44% 87.56% | 27741 12.44% 100.00%
+system.ruby.L1Cache_Controller.NP.Store::total 223015
+system.ruby.L1Cache_Controller.NP.Data_Shared | 14 11.86% 11.86% | 17 14.41% 26.27% | 16 13.56% 39.83% | 13 11.02% 50.85% | 8 6.78% 57.63% | 14 11.86% 69.49% | 17 14.41% 83.90% | 19 16.10% 100.00%
+system.ruby.L1Cache_Controller.NP.Data_Shared::total 118
+system.ruby.L1Cache_Controller.NP.Data_Owner | 6 6.38% 6.38% | 15 15.96% 22.34% | 12 12.77% 35.11% | 12 12.77% 47.87% | 8 8.51% 56.38% | 12 12.77% 69.15% | 11 11.70% 80.85% | 18 19.15% 100.00%
+system.ruby.L1Cache_Controller.NP.Data_Owner::total 94
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 4014 12.52% 12.52% | 4049 12.63% 25.15% | 4005 12.49% 37.64% | 3980 12.41% 50.05% | 3998 12.47% 62.52% | 3995 12.46% 74.98% | 4003 12.48% 87.46% | 4021 12.54% 100.00%
+system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 32065
+system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 2 40.00% 100.00%
+system.ruby.L1Cache_Controller.NP.Ack::total 5
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194672 12.49% 12.49% | 194611 12.49% 24.98% | 194621 12.49% 37.47% | 194855 12.51% 49.98% | 195006 12.52% 62.49% | 194570 12.49% 74.98% | 194932 12.51% 87.49% | 194889 12.51% 100.00%
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1558156
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 351505 12.51% 12.51% | 350885 12.49% 24.99% | 351223 12.50% 37.49% | 351366 12.50% 49.99% | 351081 12.49% 62.49% | 351596 12.51% 75.00% | 351307 12.50% 87.50% | 351400 12.50% 100.00%
+system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2810363
+system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 43131 12.51% 12.51% | 43109 12.51% 25.02% | 43069 12.50% 37.52% | 43054 12.49% 50.01% | 43044 12.49% 62.50% | 43094 12.50% 75.00% | 43053 12.49% 87.49% | 43119 12.51% 100.00%
+system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 344673
+system.ruby.L1Cache_Controller.I.Load | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.I.Load::total 1
+system.ruby.L1Cache_Controller.I.L1_Replacement | 84 12.37% 12.37% | 83 12.22% 24.59% | 95 13.99% 38.59% | 78 11.49% 50.07% | 80 11.78% 61.86% | 95 13.99% 75.85% | 77 11.34% 87.19% | 87 12.81% 100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total 679
+system.ruby.L1Cache_Controller.I.Data_All_Tokens | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 3
+system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
+system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 1
+system.ruby.L1Cache_Controller.S.L1_Replacement | 202 12.72% 12.72% | 192 12.09% 24.81% | 201 12.66% 37.47% | 180 11.34% 48.80% | 203 12.78% 61.59% | 202 12.72% 74.31% | 204 12.85% 87.15% | 204 12.85% 100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total 1588
+system.ruby.L1Cache_Controller.S.Data_Shared | 1 6.25% 6.25% | 1 6.25% 12.50% | 2 12.50% 25.00% | 4 25.00% 50.00% | 1 6.25% 56.25% | 0 0.00% 56.25% | 4 25.00% 81.25% | 3 18.75% 100.00%
+system.ruby.L1Cache_Controller.S.Data_Shared::total 16
+system.ruby.L1Cache_Controller.S.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.S.Data_Owner::total 1
+system.ruby.L1Cache_Controller.S.Data_All_Tokens | 1 9.09% 9.09% | 0 0.00% 9.09% | 1 9.09% 18.18% | 2 18.18% 36.36% | 2 18.18% 54.55% | 3 27.27% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
+system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 11
+system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 2
+system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00%
+system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 4
+system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.S.Persistent_GETX::total 3
+system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 3
+system.ruby.L1Cache_Controller.O.L1_Replacement | 56 11.86% 11.86% | 64 13.56% 25.42% | 50 10.59% 36.02% | 70 14.83% 50.85% | 61 12.92% 63.77% | 57 12.08% 75.85% | 51 10.81% 86.65% | 63 13.35% 100.00%
+system.ruby.L1Cache_Controller.O.L1_Replacement::total 472
+system.ruby.L1Cache_Controller.O.Data_All_Tokens | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 3
+system.ruby.L1Cache_Controller.O.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
system.ruby.L1Cache_Controller.O.Ack::total 1
-system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 1
-system.ruby.L1Cache_Controller.O.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Persistent_GETX::total 1
-system.ruby.L1Cache_Controller.O.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.O.Persistent_GETS::total 4
-system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 8 14.81% 14.81% | 7 12.96% 27.78% | 7 12.96% 40.74% | 2 3.70% 44.44% | 5 9.26% 53.70% | 9 16.67% 70.37% | 7 12.96% 83.33% | 9 16.67% 100.00%
-system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 54
-system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 2 6.90% 6.90% | 7 24.14% 31.03% | 5 17.24% 48.28% | 5 17.24% 65.52% | 3 10.34% 75.86% | 2 6.90% 82.76% | 5 17.24% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 29
-system.ruby.L1Cache_Controller.M.Store | 1 6.67% 6.67% | 2 13.33% 20.00% | 3 20.00% 40.00% | 2 13.33% 53.33% | 1 6.67% 60.00% | 3 20.00% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 15
-system.ruby.L1Cache_Controller.M.L1_Replacement | 50241 12.51% 12.51% | 50317 12.53% 25.04% | 50222 12.51% 37.55% | 50111 12.48% 50.03% | 50241 12.51% 62.54% | 50069 12.47% 75.01% | 50018 12.46% 87.46% | 50338 12.54% 100.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement::total 401557
-system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 17 11.18% 11.18% | 18 11.84% 23.03% | 22 14.47% 37.50% | 20 13.16% 50.66% | 33 21.71% 72.37% | 19 12.50% 84.87% | 8 5.26% 90.13% | 15 9.87% 100.00%
-system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 152
-system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 41 12.39% 12.39% | 48 14.50% 26.89% | 41 12.39% 39.27% | 44 13.29% 52.57% | 45 13.60% 66.16% | 35 10.57% 76.74% | 30 9.06% 85.80% | 47 14.20% 100.00%
-system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 331
-system.ruby.L1Cache_Controller.M.Persistent_GETX | 8 12.12% 12.12% | 9 13.64% 25.76% | 6 9.09% 34.85% | 10 15.15% 50.00% | 11 16.67% 66.67% | 9 13.64% 80.30% | 7 10.61% 90.91% | 6 9.09% 100.00%
+system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 2
+system.ruby.L1Cache_Controller.O.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.O.Persistent_GETX::total 2
+system.ruby.L1Cache_Controller.O.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.O.Persistent_GETS::total 1
+system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 8 16.33% 16.33% | 8 16.33% 32.65% | 3 6.12% 38.78% | 7 14.29% 53.06% | 7 14.29% 67.35% | 5 10.20% 77.55% | 7 14.29% 91.84% | 4 8.16% 100.00%
+system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 49
+system.ruby.L1Cache_Controller.M.Load | 5 16.67% 16.67% | 3 10.00% 26.67% | 0 0.00% 26.67% | 6 20.00% 46.67% | 3 10.00% 56.67% | 5 16.67% 73.33% | 4 13.33% 86.67% | 4 13.33% 100.00%
+system.ruby.L1Cache_Controller.M.Load::total 30
+system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 28.57% 28.57% | 3 42.86% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00%
+system.ruby.L1Cache_Controller.M.Store::total 7
+system.ruby.L1Cache_Controller.M.L1_Replacement | 49776 12.44% 12.44% | 50403 12.60% 25.04% | 50051 12.51% 37.55% | 49936 12.48% 50.04% | 50218 12.55% 62.59% | 49702 12.42% 75.01% | 50042 12.51% 87.52% | 49911 12.48% 100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total 400039
+system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 22 14.10% 14.10% | 21 13.46% 27.56% | 23 14.74% 42.31% | 18 11.54% 53.85% | 15 9.62% 63.46% | 15 9.62% 73.08% | 21 13.46% 86.54% | 21 13.46% 100.00%
+system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 156
+system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 35 12.24% 12.24% | 37 12.94% 25.17% | 32 11.19% 36.36% | 44 15.38% 51.75% | 40 13.99% 65.73% | 32 11.19% 76.92% | 29 10.14% 87.06% | 37 12.94% 100.00%
+system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 286
+system.ruby.L1Cache_Controller.M.Persistent_GETX | 7 10.61% 10.61% | 10 15.15% 25.76% | 9 13.64% 39.39% | 8 12.12% 51.52% | 12 18.18% 69.70% | 7 10.61% 80.30% | 6 9.09% 89.39% | 7 10.61% 100.00%
system.ruby.L1Cache_Controller.M.Persistent_GETX::total 66
-system.ruby.L1Cache_Controller.M.Persistent_GETS | 14 13.86% 13.86% | 18 17.82% 31.68% | 6 5.94% 37.62% | 18 17.82% 55.45% | 15 14.85% 70.30% | 10 9.90% 80.20% | 10 9.90% 90.10% | 10 9.90% 100.00%
-system.ruby.L1Cache_Controller.M.Persistent_GETS::total 101
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 348 14.36% 14.36% | 327 13.50% 27.86% | 305 12.59% 40.45% | 299 12.34% 52.79% | 285 11.76% 64.55% | 303 12.51% 77.05% | 293 12.09% 89.15% | 263 10.85% 100.00%
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 2423
-system.ruby.L1Cache_Controller.MM.Load | 5 31.25% 31.25% | 1 6.25% 37.50% | 1 6.25% 43.75% | 4 25.00% 68.75% | 2 12.50% 81.25% | 0 0.00% 81.25% | 1 6.25% 87.50% | 2 12.50% 100.00%
-system.ruby.L1Cache_Controller.MM.Load::total 16
-system.ruby.L1Cache_Controller.MM.Store | 2 25.00% 25.00% | 0 0.00% 25.00% | 3 37.50% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00%
-system.ruby.L1Cache_Controller.MM.Store::total 8
-system.ruby.L1Cache_Controller.MM.L1_Replacement | 28161 12.65% 12.65% | 27700 12.44% 25.08% | 27964 12.56% 37.64% | 27614 12.40% 50.04% | 27628 12.41% 62.45% | 27935 12.54% 74.99% | 28113 12.62% 87.62% | 27575 12.38% 100.00%
-system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222690
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 8 9.20% 9.20% | 11 12.64% 21.84% | 14 16.09% 37.93% | 8 9.20% 47.13% | 6 6.90% 54.02% | 14 16.09% 70.11% | 14 16.09% 86.21% | 12 13.79% 100.00%
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 87
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 25 15.34% 15.34% | 22 13.50% 28.83% | 22 13.50% 42.33% | 17 10.43% 52.76% | 16 9.82% 62.58% | 25 15.34% 77.91% | 18 11.04% 88.96% | 18 11.04% 100.00%
-system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 163
-system.ruby.L1Cache_Controller.MM.Persistent_GETX | 5 13.16% 13.16% | 5 13.16% 26.32% | 8 21.05% 47.37% | 2 5.26% 52.63% | 3 7.89% 60.53% | 2 5.26% 65.79% | 5 13.16% 78.95% | 8 21.05% 100.00%
-system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 38
-system.ruby.L1Cache_Controller.MM.Persistent_GETS | 8 15.09% 15.09% | 8 15.09% 30.19% | 7 13.21% 43.40% | 4 7.55% 50.94% | 4 7.55% 58.49% | 7 13.21% 71.70% | 8 15.09% 86.79% | 7 13.21% 100.00%
-system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 53
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 173 13.08% 13.08% | 166 12.55% 25.62% | 133 10.05% 35.68% | 184 13.91% 49.58% | 170 12.85% 62.43% | 162 12.24% 74.68% | 142 10.73% 85.41% | 193 14.59% 100.00%
-system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 1323
-system.ruby.L1Cache_Controller.M_W.Load | 5 10.87% 10.87% | 4 8.70% 19.57% | 5 10.87% 30.43% | 6 13.04% 43.48% | 8 17.39% 60.87% | 7 15.22% 76.09% | 5 10.87% 86.96% | 6 13.04% 100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total 46
-system.ruby.L1Cache_Controller.M_W.Store | 1 3.45% 3.45% | 4 13.79% 17.24% | 3 10.34% 27.59% | 3 10.34% 37.93% | 5 17.24% 55.17% | 4 13.79% 68.97% | 6 20.69% 89.66% | 3 10.34% 100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total 29
-system.ruby.L1Cache_Controller.M_W.L1_Replacement | 370210 12.51% 12.51% | 372575 12.59% 25.10% | 370139 12.51% 37.61% | 371169 12.54% 50.15% | 368462 12.45% 62.61% | 368601 12.46% 75.06% | 366548 12.39% 87.45% | 371410 12.55% 100.00%
-system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2959114
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 56 12.70% 12.70% | 55 12.47% 25.17% | 58 13.15% 38.32% | 57 12.93% 51.25% | 61 13.83% 65.08% | 53 12.02% 77.10% | 46 10.43% 87.53% | 55 12.47% 100.00%
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 441
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 84 9.81% 9.81% | 131 15.30% 25.12% | 119 13.90% 39.02% | 124 14.49% 53.50% | 103 12.03% 65.54% | 97 11.33% 76.87% | 96 11.21% 88.08% | 102 11.92% 100.00%
-system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 856
-system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 3 10.00% 10.00% | 2 6.67% 16.67% | 4 13.33% 30.00% | 3 10.00% 40.00% | 7 23.33% 63.33% | 4 13.33% 76.67% | 5 16.67% 93.33% | 2 6.67% 100.00%
-system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 30
-system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 2 2.38% 2.38% | 11 13.10% 15.48% | 11 13.10% 28.57% | 10 11.90% 40.48% | 7 8.33% 48.81% | 13 15.48% 64.29% | 17 20.24% 84.52% | 13 15.48% 100.00%
-system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 84
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 440 12.63% 12.63% | 415 11.91% 24.53% | 440 12.63% 37.16% | 413 11.85% 49.01% | 428 12.28% 61.29% | 446 12.80% 74.09% | 472 13.54% 87.63% | 431 12.37% 100.00%
-system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3485
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 3 10.00% 10.00% | 2 6.67% 16.67% | 4 13.33% 30.00% | 3 10.00% 40.00% | 7 23.33% 63.33% | 4 13.33% 76.67% | 5 16.67% 93.33% | 2 6.67% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 30
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 2 2.20% 2.20% | 11 12.09% 14.29% | 11 12.09% 26.37% | 10 10.99% 37.36% | 9 9.89% 47.25% | 15 16.48% 63.74% | 18 19.78% 83.52% | 15 16.48% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 91
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50321 12.51% 12.51% | 50412 12.53% 25.04% | 50299 12.51% 37.55% | 50203 12.48% 50.03% | 50345 12.52% 62.55% | 50143 12.47% 75.02% | 50076 12.45% 87.47% | 50415 12.53% 100.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 402214
-system.ruby.L1Cache_Controller.MM_W.Load | 5 17.24% 17.24% | 4 13.79% 31.03% | 2 6.90% 37.93% | 3 10.34% 48.28% | 2 6.90% 55.17% | 6 20.69% 75.86% | 2 6.90% 82.76% | 5 17.24% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total 29
-system.ruby.L1Cache_Controller.MM_W.Store | 2 14.29% 14.29% | 2 14.29% 28.57% | 3 21.43% 50.00% | 0 0.00% 50.00% | 1 7.14% 57.14% | 2 14.29% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00%
+system.ruby.L1Cache_Controller.M.Persistent_GETS | 15 16.48% 16.48% | 10 10.99% 27.47% | 17 18.68% 46.15% | 14 15.38% 61.54% | 7 7.69% 69.23% | 11 12.09% 81.32% | 9 9.89% 91.21% | 8 8.79% 100.00%
+system.ruby.L1Cache_Controller.M.Persistent_GETS::total 91
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 294 12.03% 12.03% | 300 12.27% 24.30% | 315 12.89% 37.19% | 322 13.18% 50.37% | 304 12.44% 62.81% | 298 12.19% 75.00% | 316 12.93% 87.93% | 295 12.07% 100.00%
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 2444
+system.ruby.L1Cache_Controller.MM.Load | 4 23.53% 23.53% | 2 11.76% 35.29% | 3 17.65% 52.94% | 1 5.88% 58.82% | 2 11.76% 70.59% | 1 5.88% 76.47% | 2 11.76% 88.24% | 2 11.76% 100.00%
+system.ruby.L1Cache_Controller.MM.Load::total 17
+system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00%
+system.ruby.L1Cache_Controller.MM.Store::total 4
+system.ruby.L1Cache_Controller.MM.L1_Replacement | 27953 12.55% 12.55% | 28013 12.58% 25.13% | 27961 12.55% 37.68% | 27754 12.46% 50.14% | 27630 12.41% 62.55% | 28013 12.58% 75.13% | 27692 12.43% 87.56% | 27705 12.44% 100.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222721
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 14 17.07% 17.07% | 8 9.76% 26.83% | 13 15.85% 42.68% | 7 8.54% 51.22% | 8 9.76% 60.98% | 15 18.29% 79.27% | 8 9.76% 89.02% | 9 10.98% 100.00%
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 82
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 23 15.33% 15.33% | 21 14.00% 29.33% | 25 16.67% 46.00% | 19 12.67% 58.67% | 10 6.67% 65.33% | 19 12.67% 78.00% | 16 10.67% 88.67% | 17 11.33% 100.00%
+system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 150
+system.ruby.L1Cache_Controller.MM.Persistent_GETX | 5 15.15% 15.15% | 1 3.03% 18.18% | 6 18.18% 36.36% | 4 12.12% 48.48% | 2 6.06% 54.55% | 8 24.24% 78.79% | 6 18.18% 96.97% | 1 3.03% 100.00%
+system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 33
+system.ruby.L1Cache_Controller.MM.Persistent_GETS | 6 8.57% 8.57% | 11 15.71% 24.29% | 8 11.43% 35.71% | 9 12.86% 48.57% | 9 12.86% 61.43% | 10 14.29% 75.71% | 6 8.57% 84.29% | 11 15.71% 100.00%
+system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 70
+system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 152 11.86% 11.86% | 150 11.70% 23.56% | 155 12.09% 35.65% | 177 13.81% 49.45% | 183 14.27% 63.73% | 147 11.47% 75.20% | 173 13.49% 88.69% | 145 11.31% 100.00%
+system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 1282
+system.ruby.L1Cache_Controller.M_W.Load | 8 11.59% 11.59% | 10 14.49% 26.09% | 10 14.49% 40.58% | 5 7.25% 47.83% | 14 20.29% 68.12% | 7 10.14% 78.26% | 8 11.59% 89.86% | 7 10.14% 100.00%
+system.ruby.L1Cache_Controller.M_W.Load::total 69
+system.ruby.L1Cache_Controller.M_W.Store | 6 28.57% 28.57% | 2 9.52% 38.10% | 4 19.05% 57.14% | 1 4.76% 61.90% | 1 4.76% 66.67% | 2 9.52% 76.19% | 0 0.00% 76.19% | 5 23.81% 100.00%
+system.ruby.L1Cache_Controller.M_W.Store::total 21
+system.ruby.L1Cache_Controller.M_W.L1_Replacement | 361207 12.32% 12.32% | 368703 12.58% 24.90% | 366785 12.51% 37.41% | 366334 12.50% 49.91% | 368143 12.56% 62.47% | 365562 12.47% 74.94% | 366558 12.50% 87.44% | 368107 12.56% 100.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2931399
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 57 12.08% 12.08% | 59 12.50% 24.58% | 64 13.56% 38.14% | 52 11.02% 49.15% | 55 11.65% 60.81% | 72 15.25% 76.06% | 57 12.08% 88.14% | 56 11.86% 100.00%
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 472
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 105 12.95% 12.95% | 101 12.45% 25.40% | 104 12.82% 38.22% | 106 13.07% 51.29% | 91 11.22% 62.52% | 110 13.56% 76.08% | 95 11.71% 87.79% | 99 12.21% 100.00%
+system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 811
+system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 1 2.13% 2.13% | 6 12.77% 14.89% | 5 10.64% 25.53% | 6 12.77% 38.30% | 12 25.53% 63.83% | 6 12.77% 76.60% | 4 8.51% 85.11% | 7 14.89% 100.00%
+system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 47
+system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 8 9.20% 9.20% | 4 4.60% 13.79% | 10 11.49% 25.29% | 8 9.20% 34.48% | 16 18.39% 52.87% | 13 14.94% 67.82% | 14 16.09% 83.91% | 14 16.09% 100.00%
+system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 87
+system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 450 12.82% 12.82% | 461 13.13% 25.95% | 453 12.90% 38.85% | 452 12.87% 51.72% | 381 10.85% 62.57% | 401 11.42% 74.00% | 458 13.04% 87.04% | 455 12.96% 100.00%
+system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3511
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 1 2.08% 2.08% | 6 12.50% 14.58% | 5 10.42% 25.00% | 6 12.50% 37.50% | 12 25.00% 62.50% | 6 12.50% 75.00% | 4 8.33% 83.33% | 8 16.67% 100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 48
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 8 8.60% 8.60% | 5 5.38% 13.98% | 10 10.75% 24.73% | 10 10.75% 35.48% | 17 18.28% 53.76% | 13 13.98% 67.74% | 15 16.13% 83.87% | 15 16.13% 100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 93
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 49852 12.44% 12.44% | 50481 12.60% 25.04% | 50132 12.51% 37.56% | 50020 12.49% 50.04% | 50291 12.55% 62.60% | 49763 12.42% 75.02% | 50106 12.51% 87.52% | 49984 12.48% 100.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 400629
+system.ruby.L1Cache_Controller.MM_W.Load | 2 8.00% 8.00% | 3 12.00% 20.00% | 2 8.00% 28.00% | 4 16.00% 44.00% | 3 12.00% 56.00% | 7 28.00% 84.00% | 3 12.00% 96.00% | 1 4.00% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total 25
+system.ruby.L1Cache_Controller.MM_W.Store | 2 14.29% 14.29% | 3 21.43% 35.71% | 2 14.29% 50.00% | 3 21.43% 71.43% | 1 7.14% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00%
system.ruby.L1Cache_Controller.MM_W.Store::total 14
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 204288 12.51% 12.51% | 203606 12.47% 24.97% | 204500 12.52% 37.50% | 202849 12.42% 49.92% | 203274 12.45% 62.36% | 204548 12.52% 74.89% | 207925 12.73% 87.62% | 202241 12.38% 100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1633231
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 35 12.82% 12.82% | 24 8.79% 21.61% | 38 13.92% 35.53% | 36 13.19% 48.72% | 33 12.09% 60.81% | 33 12.09% 72.89% | 35 12.82% 85.71% | 39 14.29% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 273
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 50 10.35% 10.35% | 55 11.39% 21.74% | 62 12.84% 34.58% | 55 11.39% 45.96% | 64 13.25% 59.21% | 69 14.29% 73.50% | 61 12.63% 86.13% | 67 13.87% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 483
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 3 12.00% 12.00% | 3 12.00% 24.00% | 2 8.00% 32.00% | 4 16.00% 48.00% | 1 4.00% 52.00% | 2 8.00% 60.00% | 3 12.00% 72.00% | 7 28.00% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 25
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 5 11.36% 11.36% | 5 11.36% 22.73% | 4 9.09% 31.82% | 3 6.82% 38.64% | 3 6.82% 45.45% | 10 22.73% 68.18% | 5 11.36% 79.55% | 9 20.45% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 44
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 266 13.73% 13.73% | 227 11.72% 25.45% | 273 14.09% 39.55% | 235 12.13% 51.68% | 237 12.24% 63.91% | 234 12.08% 75.99% | 225 11.62% 87.61% | 240 12.39% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 1937
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 3 11.54% 11.54% | 3 11.54% 23.08% | 2 7.69% 30.77% | 4 15.38% 46.15% | 1 3.85% 50.00% | 2 7.69% 57.69% | 3 11.54% 69.23% | 8 30.77% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 26
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 5 11.11% 11.11% | 6 13.33% 24.44% | 4 8.89% 33.33% | 3 6.67% 40.00% | 3 6.67% 46.67% | 10 22.22% 68.89% | 5 11.11% 80.00% | 9 20.00% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 45
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 28207 12.65% 12.65% | 27744 12.44% 25.09% | 28012 12.56% 37.65% | 27643 12.39% 50.04% | 27656 12.40% 62.44% | 27980 12.55% 74.99% | 28157 12.63% 87.62% | 27619 12.38% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223018
-system.ruby.L1Cache_Controller.IM.L1_Replacement | 297233 12.73% 12.73% | 289886 12.42% 25.15% | 289674 12.41% 37.56% | 288888 12.37% 49.93% | 292575 12.53% 62.46% | 292468 12.53% 74.99% | 295557 12.66% 87.65% | 288386 12.35% 100.00%
-system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2334667
-system.ruby.L1Cache_Controller.IM.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 205695 12.56% 12.56% | 204042 12.46% 25.01% | 205541 12.55% 37.56% | 204063 12.46% 50.01% | 203908 12.45% 62.46% | 207650 12.68% 75.14% | 205078 12.52% 87.66% | 202224 12.34% 100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1638201
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 28 10.98% 10.98% | 23 9.02% 20.00% | 40 15.69% 35.69% | 41 16.08% 51.76% | 33 12.94% 64.71% | 35 13.73% 78.43% | 23 9.02% 87.45% | 32 12.55% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 255
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 61 13.17% 13.17% | 44 9.50% 22.68% | 64 13.82% 36.50% | 70 15.12% 51.62% | 76 16.41% 68.03% | 48 10.37% 78.40% | 51 11.02% 89.42% | 49 10.58% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 463
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 4 11.76% 11.76% | 5 14.71% 26.47% | 3 8.82% 35.29% | 3 8.82% 44.12% | 3 8.82% 52.94% | 4 11.76% 64.71% | 5 14.71% 79.41% | 7 20.59% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 34
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 1 3.57% 3.57% | 1 3.57% 7.14% | 3 10.71% 17.86% | 1 3.57% 21.43% | 6 21.43% 42.86% | 10 35.71% 78.57% | 2 7.14% 85.71% | 4 14.29% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 28
+system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 239 12.35% 12.35% | 242 12.51% 24.86% | 240 12.40% 37.26% | 257 13.28% 50.54% | 244 12.61% 63.15% | 254 13.13% 76.28% | 213 11.01% 87.29% | 246 12.71% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 1935
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 4 11.11% 11.11% | 5 13.89% 25.00% | 3 8.33% 33.33% | 3 8.33% 41.67% | 3 8.33% 50.00% | 4 11.11% 61.11% | 6 16.67% 77.78% | 8 22.22% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 36
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 1 3.23% 3.23% | 1 3.23% 6.45% | 3 9.68% 16.13% | 2 6.45% 22.58% | 7 22.58% 45.16% | 10 32.26% 77.42% | 3 9.68% 87.10% | 4 12.90% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 31
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 28001 12.55% 12.55% | 28054 12.58% 25.13% | 28011 12.56% 37.69% | 27790 12.46% 50.15% | 27658 12.40% 62.55% | 28065 12.58% 75.13% | 27729 12.43% 87.56% | 27742 12.44% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223050
+system.ruby.L1Cache_Controller.IM.L1_Replacement | 295093 12.61% 12.61% | 294925 12.61% 25.22% | 294016 12.57% 37.79% | 291033 12.44% 50.23% | 290166 12.40% 62.64% | 294109 12.57% 75.21% | 290971 12.44% 87.65% | 288911 12.35% 100.00%
+system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2339224
+system.ruby.L1Cache_Controller.IM.Data_Owner | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
system.ruby.L1Cache_Controller.IM.Data_Owner::total 3
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 28214 12.65% 12.65% | 27748 12.44% 25.09% | 28014 12.56% 37.65% | 27648 12.40% 50.04% | 27655 12.40% 62.44% | 27988 12.55% 74.99% | 28158 12.62% 87.61% | 27632 12.39% 100.00%
-system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223057
-system.ruby.L1Cache_Controller.IM.Ack | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total 5
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 97 13.80% 13.80% | 99 14.08% 27.88% | 72 10.24% 38.12% | 102 14.51% 52.63% | 79 11.24% 63.87% | 86 12.23% 76.10% | 72 10.24% 86.34% | 96 13.66% 100.00%
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 703
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 157 12.07% 12.07% | 146 11.22% 23.29% | 173 13.30% 36.59% | 141 10.84% 47.43% | 168 12.91% 60.34% | 186 14.30% 74.63% | 157 12.07% 86.70% | 173 13.30% 100.00%
-system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1301
-system.ruby.L1Cache_Controller.IM.Persistent_GETX | 6 12.00% 12.00% | 5 10.00% 22.00% | 5 10.00% 32.00% | 5 10.00% 42.00% | 6 12.00% 54.00% | 9 18.00% 72.00% | 9 18.00% 90.00% | 5 10.00% 100.00%
-system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 50
-system.ruby.L1Cache_Controller.IM.Persistent_GETS | 11 10.48% 10.48% | 13 12.38% 22.86% | 17 16.19% 39.05% | 10 9.52% 48.57% | 13 12.38% 60.95% | 15 14.29% 75.24% | 13 12.38% 87.62% | 13 12.38% 100.00%
-system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 105
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 1706 12.40% 12.40% | 1723 12.52% 24.92% | 1721 12.51% 37.43% | 1759 12.78% 50.21% | 1740 12.65% 62.86% | 1764 12.82% 75.68% | 1632 11.86% 87.54% | 1715 12.46% 100.00%
-system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 13760
-system.ruby.L1Cache_Controller.IM.Request_Timeout | 11760 12.12% 12.12% | 12506 12.89% 25.02% | 12482 12.87% 37.89% | 12270 12.65% 50.54% | 11911 12.28% 62.82% | 11774 12.14% 74.96% | 11971 12.34% 87.30% | 12321 12.70% 100.00%
-system.ruby.L1Cache_Controller.IM.Request_Timeout::total 96995
-system.ruby.L1Cache_Controller.OM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 24 63.16% 63.16% | 0 0.00% 63.16% | 0 0.00% 63.16% | 0 0.00% 63.16% | 2 5.26% 68.42% | 12 31.58% 100.00%
-system.ruby.L1Cache_Controller.OM.L1_Replacement::total 38
-system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 28000 12.55% 12.55% | 28057 12.58% 25.13% | 28014 12.56% 37.68% | 27793 12.46% 50.14% | 27665 12.40% 62.54% | 28078 12.59% 75.13% | 27738 12.43% 87.56% | 27748 12.44% 100.00%
+system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223093
+system.ruby.L1Cache_Controller.IM.Ack | 0 0.00% 0.00% | 1 16.67% 16.67% | 0 0.00% 16.67% | 2 33.33% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total 6
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 90 11.97% 11.97% | 100 13.30% 25.27% | 94 12.50% 37.77% | 98 13.03% 50.80% | 73 9.71% 60.51% | 97 12.90% 73.40% | 103 13.70% 87.10% | 97 12.90% 100.00%
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 752
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 161 12.28% 12.28% | 188 14.34% 26.62% | 172 13.12% 39.74% | 163 12.43% 52.17% | 159 12.13% 64.30% | 175 13.35% 77.65% | 133 10.14% 87.80% | 160 12.20% 100.00%
+system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1311
+system.ruby.L1Cache_Controller.IM.Persistent_GETX | 7 9.86% 9.86% | 13 18.31% 28.17% | 8 11.27% 39.44% | 11 15.49% 54.93% | 11 15.49% 70.42% | 8 11.27% 81.69% | 6 8.45% 90.14% | 7 9.86% 100.00%
+system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 71
+system.ruby.L1Cache_Controller.IM.Persistent_GETS | 12 10.34% 10.34% | 7 6.03% 16.38% | 16 13.79% 30.17% | 11 9.48% 39.66% | 15 12.93% 52.59% | 20 17.24% 69.83% | 18 15.52% 85.34% | 17 14.66% 100.00%
+system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 116
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 1699 12.54% 12.54% | 1672 12.34% 24.89% | 1699 12.54% 37.43% | 1727 12.75% 50.18% | 1702 12.57% 62.75% | 1679 12.40% 75.15% | 1654 12.21% 87.36% | 1712 12.64% 100.00%
+system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 13544
+system.ruby.L1Cache_Controller.IM.Request_Timeout | 11980 12.55% 12.55% | 12224 12.80% 25.35% | 11886 12.45% 37.80% | 11479 12.02% 49.82% | 11994 12.56% 62.39% | 12457 13.05% 75.43% | 12326 12.91% 88.35% | 11127 11.65% 100.00%
+system.ruby.L1Cache_Controller.IM.Request_Timeout::total 95473
+system.ruby.L1Cache_Controller.OM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 40 57.14% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 30 42.86% 100.00%
+system.ruby.L1Cache_Controller.OM.L1_Replacement::total 70
+system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total 3
-system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock::total 2
-system.ruby.L1Cache_Controller.OM.Request_Timeout | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.OM.Request_Timeout | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
system.ruby.L1Cache_Controller.OM.Request_Timeout::total 2
-system.ruby.L1Cache_Controller.IS.L1_Replacement | 529103 12.51% 12.51% | 530672 12.54% 25.05% | 533381 12.61% 37.66% | 528913 12.50% 50.16% | 528203 12.49% 62.65% | 526767 12.45% 75.10% | 522401 12.35% 87.45% | 531078 12.55% 100.00%
-system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4230518
-system.ruby.L1Cache_Controller.IS.Data_Shared | 182 12.74% 12.74% | 180 12.60% 25.33% | 177 12.39% 37.72% | 176 12.32% 50.03% | 184 12.88% 62.91% | 172 12.04% 74.95% | 179 12.53% 87.47% | 179 12.53% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Shared::total 1429
-system.ruby.L1Cache_Controller.IS.Data_Owner | 23 11.39% 11.39% | 31 15.35% 26.73% | 30 14.85% 41.58% | 19 9.41% 50.99% | 27 13.37% 64.36% | 21 10.40% 74.75% | 26 12.87% 87.62% | 25 12.38% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Owner::total 202
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50326 12.51% 12.51% | 50430 12.53% 25.04% | 50318 12.51% 37.55% | 50220 12.48% 50.03% | 50365 12.52% 62.55% | 50164 12.47% 75.01% | 50104 12.45% 87.47% | 50434 12.53% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 402361
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 166 13.17% 13.17% | 158 12.54% 25.71% | 158 12.54% 38.25% | 143 11.35% 49.60% | 183 14.52% 64.13% | 147 11.67% 75.79% | 148 11.75% 87.54% | 157 12.46% 100.00%
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1260
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 290 12.11% 12.11% | 316 13.19% 25.30% | 302 12.61% 37.91% | 301 12.57% 50.48% | 323 13.49% 63.97% | 281 11.73% 75.70% | 277 11.57% 87.27% | 305 12.73% 100.00%
-system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2395
-system.ruby.L1Cache_Controller.IS.Persistent_GETX | 7 6.93% 6.93% | 24 23.76% 30.69% | 15 14.85% 45.54% | 11 10.89% 56.44% | 13 12.87% 69.31% | 15 14.85% 84.16% | 9 8.91% 93.07% | 7 6.93% 100.00%
-system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 101
-system.ruby.L1Cache_Controller.IS.Persistent_GETS | 30 13.39% 13.39% | 30 13.39% 26.79% | 30 13.39% 40.18% | 19 8.48% 48.66% | 28 12.50% 61.16% | 24 10.71% 71.88% | 31 13.84% 85.71% | 32 14.29% 100.00%
-system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 224
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 3245 12.99% 12.99% | 3160 12.65% 25.63% | 3132 12.53% 38.17% | 3085 12.35% 50.51% | 3159 12.64% 63.15% | 3121 12.49% 75.64% | 3072 12.29% 87.94% | 3014 12.06% 100.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 24988
-system.ruby.L1Cache_Controller.IS.Request_Timeout | 21713 12.50% 12.50% | 21677 12.48% 24.98% | 21741 12.52% 37.50% | 21122 12.16% 49.66% | 22600 13.01% 62.67% | 21444 12.35% 75.02% | 22164 12.76% 87.78% | 21223 12.22% 100.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout::total 173684
-system.ruby.L1Cache_Controller.I_L.Load | 25 12.63% 12.63% | 17 8.59% 21.21% | 18 9.09% 30.30% | 26 13.13% 43.43% | 29 14.65% 58.08% | 20 10.10% 68.18% | 26 13.13% 81.31% | 37 18.69% 100.00%
-system.ruby.L1Cache_Controller.I_L.Load::total 198
-system.ruby.L1Cache_Controller.I_L.Store | 13 11.61% 11.61% | 7 6.25% 17.86% | 15 13.39% 31.25% | 17 15.18% 46.43% | 15 13.39% 59.82% | 18 16.07% 75.89% | 16 14.29% 90.18% | 11 9.82% 100.00%
-system.ruby.L1Cache_Controller.I_L.Store::total 112
-system.ruby.L1Cache_Controller.I_L.L1_Replacement | 95 7.85% 7.85% | 180 14.88% 22.73% | 131 10.83% 33.55% | 79 6.53% 40.08% | 151 12.48% 52.56% | 218 18.02% 70.58% | 150 12.40% 82.98% | 206 17.02% 100.00%
-system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1210
-system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 18 17.14% 17.14% | 23 21.90% 39.05% | 11 10.48% 49.52% | 15 14.29% 63.81% | 10 9.52% 73.33% | 12 11.43% 84.76% | 7 6.67% 91.43% | 9 8.57% 100.00%
-system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 105
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 97 13.84% 13.84% | 95 13.55% 27.39% | 83 11.84% 39.23% | 85 12.13% 51.36% | 87 12.41% 63.77% | 78 11.13% 74.89% | 90 12.84% 87.73% | 86 12.27% 100.00%
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 701
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 144 12.85% 12.85% | 138 12.31% 25.16% | 149 13.29% 38.45% | 135 12.04% 50.49% | 137 12.22% 62.71% | 142 12.67% 75.38% | 140 12.49% 87.87% | 136 12.13% 100.00%
-system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 1121
-system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 13750 12.50% 12.50% | 13751 12.50% 25.01% | 13711 12.47% 37.47% | 13722 12.48% 49.95% | 13734 12.49% 62.44% | 13710 12.47% 74.90% | 13851 12.59% 87.50% | 13752 12.50% 100.00%
-system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 109981
-system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 24873 12.45% 12.45% | 24947 12.49% 24.94% | 24964 12.50% 37.43% | 25049 12.54% 49.97% | 24936 12.48% 62.45% | 24961 12.49% 74.95% | 24980 12.50% 87.45% | 25073 12.55% 100.00%
-system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 199783
-system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 33 12.45% 12.45% | 33 12.45% 24.91% | 32 12.08% 36.98% | 27 10.19% 47.17% | 31 11.70% 58.87% | 35 13.21% 72.08% | 33 12.45% 84.53% | 41 15.47% 100.00%
-system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 265
-system.ruby.L1Cache_Controller.S_L.L1_Replacement | 38 11.55% 11.55% | 61 18.54% 30.09% | 26 7.90% 37.99% | 51 15.50% 53.50% | 62 18.84% 72.34% | 10 3.04% 75.38% | 62 18.84% 94.22% | 19 5.78% 100.00%
-system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 329
-system.ruby.L1Cache_Controller.S_L.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S_L.Data_All_Tokens::total 1
-system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 1 2.94% 2.94% | 2 5.88% 8.82% | 1 2.94% 11.76% | 7 20.59% 32.35% | 8 23.53% 55.88% | 9 26.47% 82.35% | 6 17.65% 100.00%
-system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 34
-system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 17 8.50% 8.50% | 29 14.50% 23.00% | 18 9.00% 32.00% | 29 14.50% 46.50% | 27 13.50% 60.00% | 26 13.00% 73.00% | 29 14.50% 87.50% | 25 12.50% 100.00%
-system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 200
-system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 166 11.01% 11.01% | 156 10.34% 21.35% | 235 15.58% 36.94% | 157 10.41% 47.35% | 147 9.75% 57.10% | 250 16.58% 73.67% | 227 15.05% 88.73% | 170 11.27% 100.00%
-system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 1508
-system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 2
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 4 57.14% 71.43% | 2 28.57% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 7
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 1 4.55% 4.55% | 1 4.55% 9.09% | 4 18.18% 27.27% | 1 4.55% 31.82% | 6 27.27% 59.09% | 3 13.64% 72.73% | 6 27.27% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 22
-system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 30 11.32% 11.32% | 24 9.06% 20.38% | 37 13.96% 34.34% | 32 12.08% 46.42% | 34 12.83% 59.25% | 42 15.85% 75.09% | 38 14.34% 89.43% | 28 10.57% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 265
-system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 24 6.11% 6.11% | 43 10.94% 17.05% | 48 12.21% 29.26% | 26 6.62% 35.88% | 18 4.58% 40.46% | 66 16.79% 57.25% | 138 35.11% 92.37% | 30 7.63% 100.00%
-system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 393
-system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 210 8.70% 8.70% | 363 15.04% 23.74% | 263 10.89% 34.63% | 225 9.32% 43.95% | 282 11.68% 55.63% | 363 15.04% 70.67% | 336 13.92% 84.59% | 372 15.41% 100.00%
-system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 2414
-system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 3
-system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 1 12.50% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 2 25.00% 37.50% | 2 25.00% 62.50% | 1 12.50% 75.00% | 2 25.00% 100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement | 527596 12.50% 12.50% | 534359 12.66% 25.17% | 527205 12.49% 37.66% | 528297 12.52% 50.18% | 528825 12.53% 62.71% | 521299 12.35% 75.07% | 526429 12.48% 87.54% | 525605 12.46% 100.00%
+system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4219615
+system.ruby.L1Cache_Controller.IS.Data_Shared | 181 12.75% 12.75% | 177 12.46% 25.21% | 176 12.39% 37.61% | 159 11.20% 48.80% | 181 12.75% 61.55% | 182 12.82% 74.37% | 182 12.82% 87.18% | 182 12.82% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_Shared::total 1420
+system.ruby.L1Cache_Controller.IS.Data_Owner | 22 11.52% 11.52% | 27 14.14% 25.65% | 18 9.42% 35.08% | 26 13.61% 48.69% | 24 12.57% 61.26% | 26 13.61% 74.87% | 22 11.52% 86.39% | 26 13.61% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_Owner::total 191
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 49867 12.44% 12.44% | 50496 12.60% 25.04% | 50150 12.51% 37.55% | 50036 12.48% 50.04% | 50320 12.56% 62.59% | 49785 12.42% 75.02% | 50124 12.51% 87.52% | 50011 12.48% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 400789
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 152 11.69% 11.69% | 159 12.23% 23.92% | 175 13.46% 37.38% | 167 12.85% 50.23% | 173 13.31% 63.54% | 154 11.85% 75.38% | 145 11.15% 86.54% | 175 13.46% 100.00%
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1300
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 325 12.87% 12.87% | 314 12.44% 25.31% | 332 13.15% 38.46% | 302 11.96% 50.42% | 305 12.08% 62.50% | 312 12.36% 74.85% | 322 12.75% 87.60% | 313 12.40% 100.00%
+system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2525
+system.ruby.L1Cache_Controller.IS.Persistent_GETX | 14 12.17% 12.17% | 10 8.70% 20.87% | 18 15.65% 36.52% | 14 12.17% 48.70% | 17 14.78% 63.48% | 12 10.43% 73.91% | 19 16.52% 90.43% | 11 9.57% 100.00%
+system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 115
+system.ruby.L1Cache_Controller.IS.Persistent_GETS | 28 11.72% 11.72% | 23 9.62% 21.34% | 32 13.39% 34.73% | 25 10.46% 45.19% | 35 14.64% 59.83% | 32 13.39% 73.22% | 39 16.32% 89.54% | 25 10.46% 100.00%
+system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 239
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 3103 12.48% 12.48% | 3161 12.72% 25.20% | 3104 12.49% 37.69% | 3090 12.43% 50.12% | 3120 12.55% 62.67% | 3099 12.47% 75.14% | 3066 12.34% 87.48% | 3113 12.52% 100.00%
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 24856
+system.ruby.L1Cache_Controller.IS.Request_Timeout | 21020 12.47% 12.47% | 21488 12.74% 25.21% | 21067 12.49% 37.70% | 21326 12.65% 50.35% | 20944 12.42% 62.77% | 20610 12.22% 74.99% | 20711 12.28% 87.27% | 21463 12.73% 100.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout::total 168629
+system.ruby.L1Cache_Controller.I_L.Load | 18 10.06% 10.06% | 16 8.94% 18.99% | 29 16.20% 35.20% | 27 15.08% 50.28% | 27 15.08% 65.36% | 11 6.15% 71.51% | 26 14.53% 86.03% | 25 13.97% 100.00%
+system.ruby.L1Cache_Controller.I_L.Load::total 179
+system.ruby.L1Cache_Controller.I_L.Store | 9 9.68% 9.68% | 18 19.35% 29.03% | 14 15.05% 44.09% | 10 10.75% 54.84% | 10 10.75% 65.59% | 13 13.98% 79.57% | 9 9.68% 89.25% | 10 10.75% 100.00%
+system.ruby.L1Cache_Controller.I_L.Store::total 93
+system.ruby.L1Cache_Controller.I_L.L1_Replacement | 125 9.36% 9.36% | 83 6.21% 15.57% | 178 13.32% 28.89% | 173 12.95% 41.84% | 239 17.89% 59.73% | 184 13.77% 73.50% | 192 14.37% 87.87% | 162 12.13% 100.00%
+system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1336
+system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 27 21.26% 21.26% | 18 14.17% 35.43% | 29 22.83% 58.27% | 16 12.60% 70.87% | 17 13.39% 84.25% | 7 5.51% 89.76% | 7 5.51% 95.28% | 6 4.72% 100.00%
+system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 127
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 69 11.94% 11.94% | 69 11.94% 23.88% | 63 10.90% 34.78% | 75 12.98% 47.75% | 76 13.15% 60.90% | 71 12.28% 73.18% | 78 13.49% 86.68% | 77 13.32% 100.00%
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 578
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 132 12.88% 12.88% | 128 12.49% 25.37% | 121 11.80% 37.17% | 125 12.20% 49.37% | 127 12.39% 61.76% | 134 13.07% 74.83% | 137 13.37% 88.20% | 121 11.80% 100.00%
+system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 1025
+system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 13578 12.51% 12.51% | 13598 12.53% 25.04% | 13560 12.49% 37.53% | 13520 12.46% 49.98% | 13540 12.47% 62.46% | 13571 12.50% 74.96% | 13635 12.56% 87.52% | 13544 12.48% 100.00%
+system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 108546
+system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 24905 12.51% 12.51% | 24862 12.48% 24.99% | 24875 12.49% 37.48% | 24914 12.51% 49.99% | 24915 12.51% 62.50% | 24926 12.52% 75.02% | 24887 12.50% 87.52% | 24855 12.48% 100.00%
+system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 199139
+system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 25 8.53% 8.53% | 34 11.60% 20.14% | 35 11.95% 32.08% | 35 11.95% 44.03% | 46 15.70% 59.73% | 46 15.70% 75.43% | 32 10.92% 86.35% | 40 13.65% 100.00%
+system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 293
+system.ruby.L1Cache_Controller.S_L.L1_Replacement | 46 14.37% 14.37% | 31 9.69% 24.06% | 38 11.88% 35.94% | 8 2.50% 38.44% | 52 16.25% 54.69% | 22 6.88% 61.56% | 48 15.00% 76.56% | 75 23.44% 100.00%
+system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 320
+system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 1 3.23% 3.23% | 3 9.68% 12.90% | 4 12.90% 25.81% | 7 22.58% 48.39% | 3 9.68% 58.06% | 7 22.58% 80.65% | 6 19.35% 100.00%
+system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 31
+system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 23 12.23% 12.23% | 15 7.98% 20.21% | 27 14.36% 34.57% | 24 12.77% 47.34% | 25 13.30% 60.64% | 26 13.83% 74.47% | 24 12.77% 87.23% | 24 12.77% 100.00%
+system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 188
+system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 143 9.18% 9.18% | 175 11.23% 20.41% | 168 10.78% 31.19% | 236 15.15% 46.34% | 181 11.62% 57.96% | 285 18.29% 76.25% | 169 10.85% 87.10% | 201 12.90% 100.00%
+system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 1558
+system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00%
+system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 5
+system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETX::total 2
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 1 10.00% 10.00% | 1 10.00% 20.00% | 2 20.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00%
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 10
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 16.13% 16.13% | 1 3.23% 19.35% | 4 12.90% 32.26% | 2 6.45% 38.71% | 8 25.81% 64.52% | 11 35.48% 100.00%
+system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 31
+system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 28 10.18% 10.18% | 38 13.82% 24.00% | 38 13.82% 37.82% | 31 11.27% 49.09% | 35 12.73% 61.82% | 41 14.91% 76.73% | 31 11.27% 88.00% | 33 12.00% 100.00%
+system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 275
+system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 22 5.98% 5.98% | 62 16.85% 22.83% | 33 8.97% 31.79% | 61 16.58% 48.37% | 42 11.41% 59.78% | 13 3.53% 63.32% | 89 24.18% 87.50% | 46 12.50% 100.00%
+system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 368
+system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 404 13.20% 13.20% | 259 8.46% 21.67% | 472 15.42% 37.09% | 362 11.83% 48.92% | 384 12.55% 61.47% | 320 10.46% 71.93% | 506 16.54% 88.46% | 353 11.54% 100.00%
+system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 3060
+system.ruby.L1Cache_Controller.IS_L.Data_Shared | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00%
+system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 4
+system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 0 0.00% 0.00% | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 1 12.50% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 2 25.00% 100.00%
system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 8
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 2
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 2 9.52% 9.52% | 4 19.05% 28.57% | 3 14.29% 42.86% | 1 4.76% 47.62% | 3 14.29% 61.90% | 1 4.76% 66.67% | 7 33.33% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 21
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 1 2.44% 2.44% | 1 2.44% 4.88% | 5 12.20% 17.07% | 11 26.83% 43.90% | 5 12.20% 56.10% | 9 21.95% 78.05% | 9 21.95% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 41
-system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 61 11.91% 11.91% | 71 13.87% 25.78% | 62 12.11% 37.89% | 56 10.94% 48.83% | 67 13.09% 61.91% | 57 11.13% 73.05% | 65 12.70% 85.74% | 73 14.26% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 512
-system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 122 15.66% 15.66% | 80 10.27% 25.93% | 163 20.92% 46.85% | 39 5.01% 51.86% | 125 16.05% 67.91% | 143 18.36% 86.26% | 73 9.37% 95.64% | 34 4.36% 100.00%
-system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 779
-system.ruby.L2Cache_Controller.L1_GETS 403983 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS_Last_Token 34 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 223069 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_INV 668 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 599911 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Shared_Data 988 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens 624946 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_Owned 455 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETX 15761 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS 28642 0.00% 0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 44053 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 402707 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 222334 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_INV 488 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 916 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 598635 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_Owned 368 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 36593 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_GETS 55 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_GETX 24 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L1_INV 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.L2_Replacement 7638 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 472 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Writeback_Owned 15 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Persistent_GETX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.I.Persistent_GETS 16 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 34 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 821 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 5 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 71 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.Writeback_Owned 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 14.81% 14.81% | 3 11.11% 25.93% | 6 22.22% 48.15% | 2 7.41% 55.56% | 6 22.22% 77.78% | 6 22.22% 100.00%
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 27
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 1 1.89% 1.89% | 2 3.77% 5.66% | 5 9.43% 15.09% | 10 18.87% 33.96% | 8 15.09% 49.06% | 14 26.42% 75.47% | 13 24.53% 100.00%
+system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 53
+system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 59 11.32% 11.32% | 48 9.21% 20.54% | 78 14.97% 35.51% | 62 11.90% 47.41% | 78 14.97% 62.38% | 55 10.56% 72.94% | 83 15.93% 88.87% | 58 11.13% 100.00%
+system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 521
+system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 186 23.05% 23.05% | 67 8.30% 31.35% | 121 14.99% 46.34% | 77 9.54% 55.89% | 90 11.15% 67.04% | 70 8.67% 75.71% | 143 17.72% 93.43% | 53 6.57% 100.00%
+system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 807
+system.ruby.L2Cache_Controller.L1_GETS 402399 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS_Last_Token 20 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 223106 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_INV 683 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 598575 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Shared_Data 975 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_All_Tokens 623413 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Owned 430 0.00% 0.00%
+system.ruby.L2Cache_Controller.Persistent_GETX 15565 0.00% 0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS 28553 0.00% 0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 43680 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 401075 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 222380 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_INV 492 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 901 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 597337 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_Owned 345 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 36371 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L1_GETS 61 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L1_GETX 35 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L1_INV 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L2_Replacement 7485 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 457 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.Writeback_Owned 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.Persistent_GETX 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.Persistent_GETS 15 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 20 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 848 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 42 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.Writeback_Owned 2 0.00% 0.00%
system.ruby.L2Cache_Controller.S.Persistent_GETX 1 0.00% 0.00%
system.ruby.L2Cache_Controller.S.Persistent_GETS 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.L1_GETS 21 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.Persistent_GETS_Last_Token 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.L1_GETS 20 0.00% 0.00%
system.ruby.L2Cache_Controller.O.L1_GETX 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.L2_Replacement 877 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 1 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 628 0.00% 0.00%
-system.ruby.L2Cache_Controller.O.Persistent_GETS 8 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1132 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 659 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 589830 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETX 2834 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.Persistent_GETS 5343 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.L1_GETS 68 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.L1_GETX 49 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.L1_INV 178 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.L2_Replacement 745 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.L2_Replacement 895 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 613 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.Persistent_GETX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.O.Persistent_GETS 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1170 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 655 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 588544 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Persistent_GETX 2903 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Persistent_GETS 5169 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.L1_GETS 73 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.L1_GETX 33 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.L1_INV 188 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.L2_Replacement 800 0.00% 0.00%
system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 62 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 25140 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Writeback_Owned 71 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETX 12924 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS 23274 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 7451 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 24964 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Writeback_Owned 75 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETX 12653 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETS 23355 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 7296 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_L.L2_Replacement 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_L.Writeback_Shared_Data 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_L.Persistent_GETS_Last_Token 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 13 0.00% 0.00%
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.004718 # Number of seconds simulated
-sim_ticks 4717737 # Number of ticks simulated
-final_tick 4717737 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.004710 # Number of seconds simulated
+sim_ticks 4710288 # Number of ticks simulated
+final_tick 4710288 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 46146 # Simulator tick rate (ticks/s)
-host_mem_usage 663608 # Number of bytes of host memory used
-host_seconds 102.24 # Real time elapsed on the host
+host_tick_rate 49486 # Simulator tick rate (ticks/s)
+host_mem_usage 481348 # Number of bytes of host memory used
+host_seconds 95.18 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38891008 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 38891008 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14178496 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 14178496 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 607672 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 607672 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 221539 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 221539 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 8243572713 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 8243572713 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 3005359561 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 3005359561 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 11248932274 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 11248932274 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 607686 # Number of read requests accepted
-system.mem_ctrls.writeReqs 221539 # Number of write requests accepted
-system.mem_ctrls.readBursts 607686 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 221539 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 37901760 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 989888 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 13990016 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 38891904 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 14178496 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 15467 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 2896 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38770176 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 38770176 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14150080 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 14150080 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 605784 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 605784 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 221095 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 221095 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 8230956578 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 8230956578 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 3004079581 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 3004079581 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 11235036159 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 11235036159 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 605795 # Number of read requests accepted
+system.mem_ctrls.writeReqs 221095 # Number of write requests accepted
+system.mem_ctrls.readBursts 605795 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 221095 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 37774848 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 995776 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 13961856 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 38770880 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 14150080 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 15559 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 2886 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 74248 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 73965 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 74362 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 73718 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 73629 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 74182 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 74198 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 73913 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 74027 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 73691 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 74048 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 73659 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 73761 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 73677 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6 73634 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 73735 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 27580 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 27153 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 27465 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 27217 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 27251 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 27223 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 27298 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 27407 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 27260 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 27309 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 27417 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 27165 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 27317 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 27153 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6 27104 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 27429 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 341 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 4717717 # Total gap between requests
+system.mem_ctrls.numWrRetry 409 # Number of times write queue was full causing retry
+system.mem_ctrls.totGap 4710276 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 607686 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 605795 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 221539 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 173 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::1 425 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::2 892 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::3 1471 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::4 2214 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::5 3131 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::6 4313 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::7 5653 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::8 7328 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::9 9462 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::10 12392 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::11 16826 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::12 24221 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::13 34718 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::14 47678 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::15 60525 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::16 68415 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::17 69451 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::18 61971 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::19 48773 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::20 34538 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::21 23158 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::22 15821 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::23 11733 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::24 9215 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::25 7008 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::26 4874 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::27 3036 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::28 1729 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::29 772 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::30 260 # What read queue length does an incoming req see
-system.mem_ctrls.rdQLenPdf::31 43 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 221095 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 191 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::1 460 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::2 934 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::3 1567 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::4 2278 # What read queue length does an incoming req see
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-system.mem_ctrls.bytesPerActivate::samples 217832 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 238.215138 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 188.366987 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 172.557799 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 37638 17.28% 17.28% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 92585 42.50% 59.78% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 45398 20.84% 80.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 21076 9.68% 90.30% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 10973 5.04% 95.33% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 5549 2.55% 97.88% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 2719 1.25% 99.13% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1199 0.55% 99.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 695 0.32% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 217832 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 13655 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 43.367704 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 31.670415 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 25.872524 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-15 3074 22.51% 22.51% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-31 1792 13.12% 35.64% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-47 2254 16.51% 52.14% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::48-63 2805 20.54% 72.68% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::64-79 2763 20.23% 92.92% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-95 909 6.66% 99.58% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::96-111 55 0.40% 99.98% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::112-127 2 0.01% 99.99% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::256-271 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 13655 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 13655 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.008349 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.007193 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.215662 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 13627 99.79% 99.79% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 6 0.04% 99.84% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 3 0.02% 99.86% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 5 0.04% 99.90% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 2 0.01% 99.91% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 4 0.03% 99.94% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 4 0.03% 99.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 2 0.01% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 13655 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 74136636 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 85388721 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 2961075 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 125.18 # Average queueing delay per DRAM burst
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+system.mem_ctrls.bytesPerActivate::0-127 37866 17.43% 17.43% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 92203 42.44% 59.87% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 44887 20.66% 80.53% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 21105 9.71% 90.24% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 10935 5.03% 95.27% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 5805 2.67% 97.95% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 2648 1.22% 99.17% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 1064 0.49% 99.65% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 750 0.35% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 217263 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 13625 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 43.319780 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 31.150642 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 26.199447 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::0-7 1380 10.13% 10.13% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::8-15 1829 13.42% 23.55% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23 675 4.95% 28.51% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::24-31 992 7.28% 35.79% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::32-39 1096 8.04% 43.83% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::40-47 1136 8.34% 52.17% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::48-55 1294 9.50% 61.67% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::56-63 1412 10.36% 72.03% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-71 1517 11.13% 83.16% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::72-79 1303 9.56% 92.73% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87 700 5.14% 97.86% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::88-95 229 1.68% 99.54% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::96-103 55 0.40% 99.95% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::104-111 6 0.04% 99.99% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::248-255 1 0.01% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 13625 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 13624 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.012405 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.010105 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.322047 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 13591 99.76% 99.76% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 6 0.04% 99.80% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 7 0.05% 99.85% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 3 0.02% 99.88% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20 1 0.01% 99.88% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::21 4 0.03% 99.91% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::22 1 0.01% 99.92% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23 3 0.02% 99.94% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25 3 0.02% 99.97% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::30 2 0.01% 99.99% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 13624 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 73947917 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 85162325 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 2951160 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 125.29 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 144.18 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 8033.89 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 2965.41 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 8243.76 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 3005.36 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 144.29 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 8019.65 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 2964.12 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 8231.11 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 3004.08 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 85.93 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 62.76 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 23.17 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 19.65 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 50.35 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 380729 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 212242 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 64.29 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 97.07 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 5.69 # Average gap between requests
-system.mem_ctrls.pageHitRate 73.13 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1644443640 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 913579800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7379698560 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 2262898944 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 307678800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 3210618024 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 10162200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 15729079968 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 3338.923999 # Core power per rank (mW)
+system.mem_ctrls.busUtil 85.81 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 62.65 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 23.16 # Data bus utilization in percentage for writes
+system.mem_ctrls.avgRdQLen 19.64 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 50.37 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 379240 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 211876 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 64.25 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 97.10 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 5.70 # Average gap between requests
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system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states
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system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
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system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
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system.cpu7.num_reads 100000 # number of read accesses completed
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system.ruby.clk_domain.clock 1 # Clock period in ticks
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system.ruby.network.routers6.msg_count.Request_Control::3 131
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system.ruby.network.routers6.msg_bytes.Request_Control::3 1048
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system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128
system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279
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-system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 139.401669
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 223 61.43% 61.43% | 89 24.52% 85.95% | 32 8.82% 94.77% | 8 2.20% 96.97% | 5 1.38% 98.35% | 3 0.83% 99.17% | 3 0.83% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119
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-system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 671.046581
-system.ruby.LD.Directory.miss_type_mach_latency_hist | 145651 37.27% 37.27% | 72310 18.50% 55.77% | 73205 18.73% 74.50% | 76232 19.51% 94.01% | 21851 5.59% 99.60% | 1527 0.39% 99.99% | 44 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9
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system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2
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system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119
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-system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 4046 40.15% 40.15% | 1748 17.34% 57.49% | 1882 18.67% 76.17% | 1911 18.96% 95.13% | 462 4.58% 99.71% | 27 0.27% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10078
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 128
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-system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 117 65.00% 65.00% | 42 23.33% 88.33% | 18 10.00% 98.33% | 2 1.11% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 180
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+system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 169.763754
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 160 89.39% 89.39% | 14 7.82% 97.21% | 4 2.23% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119
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-system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 669.356252
-system.ruby.ST.Directory.miss_type_mach_latency_hist | 79862 37.31% 37.31% | 39618 18.51% 55.81% | 40238 18.80% 74.61% | 41777 19.52% 94.12% | 11700 5.47% 99.59% | 865 0.40% 99.99% | 13 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.Directory_Controller.GETX 228066 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 409919 0.00% 0.00%
-system.ruby.Directory_Controller.PUT 606117 0.00% 0.00%
-system.ruby.Directory_Controller.Unblock 1478 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockS 26200 0.00% 0.00%
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-system.ruby.Directory_Controller.Writeback_Dirty 1462 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean 361520 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220077 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 607668 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 221538 0.00% 0.00%
-system.ruby.Directory_Controller.All_Unblocks 1073 0.00% 0.00%
-system.ruby.Directory_Controller.NX.GETX 64 0.00% 0.00%
-system.ruby.Directory_Controller.NX.GETS 111 0.00% 0.00%
-system.ruby.Directory_Controller.NX.PUT 10889 0.00% 0.00%
-system.ruby.Directory_Controller.NO.GETX 7240 0.00% 0.00%
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-system.ruby.Directory_Controller.NO.PUT 581636 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETX 9346 0.00% 0.00%
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-system.ruby.Directory_Controller.E.GETS 374265 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.GETX 569 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.GETS 1073 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.PUT 13366 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.UnblockS 8495 0.00% 0.00%
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-system.ruby.Directory_Controller.NO_B_S.GETS 3 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S.PUT 33 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S.UnblockS 42 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_S.UnblockM 1031 0.00% 0.00%
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-system.ruby.Directory_Controller.NO_B_S_W.PUT 121 0.00% 0.00%
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-system.ruby.Directory_Controller.O_B.GETS 15 0.00% 0.00%
-system.ruby.Directory_Controller.O_B.UnblockS 16568 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_W.GETX 1985 0.00% 0.00%
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-system.ruby.Directory_Controller.O_B_W.Memory_Data 16568 0.00% 0.00%
-system.ruby.Directory_Controller.WB.GETX 1246 0.00% 0.00%
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-system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220076 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load | 50385 12.45% 12.45% | 50687 12.52% 24.97% | 50468 12.47% 37.44% | 50666 12.52% 49.96% | 50623 12.51% 62.47% | 50650 12.51% 74.98% | 50545 12.49% 87.47% | 50723 12.53% 100.00%
-system.ruby.L1Cache_Controller.Load::total 404747
-system.ruby.L1Cache_Controller.Store | 28072 12.50% 12.50% | 28228 12.57% 25.07% | 28321 12.61% 37.69% | 27699 12.34% 50.02% | 28273 12.59% 62.61% | 28020 12.48% 75.09% | 28027 12.48% 87.57% | 27908 12.43% 100.00%
-system.ruby.L1Cache_Controller.Store::total 224548
-system.ruby.L1Cache_Controller.L2_Replacement | 78299 12.47% 12.47% | 78765 12.54% 25.01% | 78648 12.52% 37.53% | 78211 12.45% 49.98% | 78724 12.53% 62.52% | 78526 12.50% 75.02% | 78393 12.48% 87.51% | 78471 12.49% 100.00%
-system.ruby.L1Cache_Controller.L2_Replacement::total 628037
-system.ruby.L1Cache_Controller.L1_to_L2 | 979507 12.50% 12.50% | 981167 12.52% 25.01% | 980052 12.50% 37.51% | 977154 12.47% 49.98% | 982076 12.53% 62.51% | 980285 12.51% 75.01% | 977927 12.48% 87.49% | 980636 12.51% 100.00%
-system.ruby.L1Cache_Controller.L1_to_L2::total 7838804
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 67 11.90% 11.90% | 65 11.55% 23.45% | 63 11.19% 34.64% | 70 12.43% 47.07% | 72 12.79% 59.86% | 62 11.01% 70.87% | 85 15.10% 85.97% | 79 14.03% 100.00%
-system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 563
-system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 67 11.90% 11.90% | 65 11.55% 23.45% | 63 11.19% 34.64% | 70 12.43% 47.07% | 72 12.79% 59.86% | 62 11.01% 70.87% | 85 15.10% 85.97% | 79 14.03% 100.00%
-system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 563
-system.ruby.L1Cache_Controller.Other_GETX | 196134 12.50% 12.50% | 195975 12.49% 24.99% | 195874 12.48% 37.47% | 196504 12.52% 50.00% | 195940 12.49% 62.48% | 196190 12.50% 74.99% | 196188 12.50% 87.49% | 196280 12.51% 100.00%
-system.ruby.L1Cache_Controller.Other_GETX::total 1569085
-system.ruby.L1Cache_Controller.Other_GETS | 352746 12.51% 12.51% | 352417 12.50% 25.00% | 352660 12.50% 37.51% | 352467 12.50% 50.01% | 352524 12.50% 62.50% | 352468 12.50% 75.00% | 352590 12.50% 87.50% | 352421 12.50% 100.00%
-system.ruby.L1Cache_Controller.Other_GETS::total 2820293
-system.ruby.L1Cache_Controller.Merged_GETS | 136 12.67% 12.67% | 148 13.79% 26.47% | 126 11.74% 38.21% | 132 12.30% 50.51% | 123 11.46% 61.98% | 138 12.86% 74.84% | 131 12.21% 87.05% | 139 12.95% 100.00%
-system.ruby.L1Cache_Controller.Merged_GETS::total 1073
-system.ruby.L1Cache_Controller.Ack | 544749 12.47% 12.47% | 548151 12.54% 25.01% | 547200 12.52% 37.53% | 544104 12.45% 49.99% | 547634 12.53% 62.52% | 546228 12.50% 75.02% | 545522 12.48% 87.50% | 545987 12.50% 100.00%
-system.ruby.L1Cache_Controller.Ack::total 4369575
-system.ruby.L1Cache_Controller.Shared_Ack | 44 10.38% 10.38% | 64 15.09% 25.47% | 49 11.56% 37.03% | 55 12.97% 50.00% | 58 13.68% 63.68% | 62 14.62% 78.30% | 48 11.32% 89.62% | 44 10.38% 100.00%
-system.ruby.L1Cache_Controller.Shared_Ack::total 424
-system.ruby.L1Cache_Controller.Data | 3431 12.51% 12.51% | 3478 12.68% 25.20% | 3487 12.72% 37.91% | 3316 12.09% 50.00% | 3463 12.63% 62.63% | 3469 12.65% 75.28% | 3357 12.24% 87.52% | 3421 12.48% 100.00%
-system.ruby.L1Cache_Controller.Data::total 27422
-system.ruby.L1Cache_Controller.Shared_Data | 1205 12.51% 12.51% | 1184 12.29% 24.80% | 1195 12.41% 37.21% | 1186 12.31% 49.52% | 1199 12.45% 61.97% | 1238 12.85% 74.82% | 1198 12.44% 87.26% | 1227 12.74% 100.00%
-system.ruby.L1Cache_Controller.Shared_Data::total 9632
-system.ruby.L1Cache_Controller.Exclusive_Data | 73671 12.46% 12.46% | 74114 12.54% 25.00% | 73974 12.52% 37.52% | 73718 12.47% 49.99% | 74071 12.53% 62.52% | 73826 12.49% 75.01% | 73849 12.49% 87.51% | 73835 12.49% 100.00%
-system.ruby.L1Cache_Controller.Exclusive_Data::total 591058
-system.ruby.L1Cache_Controller.Writeback_Ack | 73966 12.48% 12.48% | 74272 12.53% 25.02% | 74193 12.52% 37.54% | 73799 12.46% 49.99% | 74240 12.53% 62.52% | 73997 12.49% 75.01% | 73995 12.49% 87.50% | 74059 12.50% 100.00%
-system.ruby.L1Cache_Controller.Writeback_Ack::total 592521
-system.ruby.L1Cache_Controller.All_acks | 1242 12.43% 12.43% | 1233 12.34% 24.77% | 1238 12.39% 37.16% | 1235 12.36% 49.52% | 1246 12.47% 61.99% | 1291 12.92% 74.91% | 1239 12.40% 87.31% | 1268 12.69% 100.00%
-system.ruby.L1Cache_Controller.All_acks::total 9992
-system.ruby.L1Cache_Controller.All_acks_no_sharers | 77066 12.47% 12.47% | 77544 12.55% 25.01% | 77418 12.52% 37.54% | 76985 12.45% 49.99% | 77487 12.54% 62.53% | 77242 12.50% 75.02% | 77165 12.48% 87.51% | 77215 12.49% 100.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers::total 618122
-system.ruby.L1Cache_Controller.I.Load | 50288 12.45% 12.45% | 50598 12.53% 24.97% | 50377 12.47% 37.44% | 50572 12.52% 49.96% | 50518 12.51% 62.47% | 50570 12.52% 74.99% | 50439 12.49% 87.47% | 50607 12.53% 100.00%
-system.ruby.L1Cache_Controller.I.Load::total 403969
-system.ruby.L1Cache_Controller.I.Store | 28021 12.50% 12.50% | 28176 12.57% 25.07% | 28281 12.62% 37.69% | 27649 12.34% 50.02% | 28214 12.59% 62.61% | 27965 12.48% 75.09% | 27964 12.48% 87.56% | 27875 12.44% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 224145
-system.ruby.L1Cache_Controller.I.L2_Replacement | 1108 11.60% 11.60% | 1263 13.22% 24.81% | 1214 12.71% 37.52% | 1261 13.20% 50.72% | 1167 12.21% 62.93% | 1204 12.60% 75.53% | 1194 12.50% 88.03% | 1144 11.97% 100.00%
-system.ruby.L1Cache_Controller.I.L2_Replacement::total 9555
-system.ruby.L1Cache_Controller.I.L1_to_L2 | 85 10.98% 10.98% | 100 12.92% 23.90% | 96 12.40% 36.30% | 96 12.40% 48.71% | 85 10.98% 59.69% | 104 13.44% 73.13% | 117 15.12% 88.24% | 91 11.76% 100.00%
-system.ruby.L1Cache_Controller.I.L1_to_L2::total 774
-system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 1 10.00% 10.00% | 1 10.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 3 30.00% 100.00%
-system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total 10
-system.ruby.L1Cache_Controller.I.Other_GETX | 195054 12.50% 12.50% | 194813 12.49% 24.99% | 194750 12.48% 37.47% | 195324 12.52% 49.99% | 194790 12.49% 62.48% | 195048 12.50% 74.98% | 195089 12.51% 87.49% | 195205 12.51% 100.00%
-system.ruby.L1Cache_Controller.I.Other_GETX::total 1560073
-system.ruby.L1Cache_Controller.I.Other_GETS | 350845 12.51% 12.51% | 350506 12.49% 25.00% | 350840 12.51% 37.51% | 350591 12.50% 50.01% | 350672 12.50% 62.51% | 350617 12.50% 75.00% | 350657 12.50% 87.50% | 350525 12.50% 100.00%
-system.ruby.L1Cache_Controller.I.Other_GETS::total 2805253
-system.ruby.L1Cache_Controller.S.Load | 2 22.22% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 4 44.44% 77.78% | 2 22.22% 100.00%
-system.ruby.L1Cache_Controller.S.Load::total 9
-system.ruby.L1Cache_Controller.S.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.S.Store::total 2
-system.ruby.L1Cache_Controller.S.L2_Replacement | 3221 12.41% 12.41% | 3230 12.44% 24.85% | 3241 12.49% 37.34% | 3151 12.14% 49.48% | 3317 12.78% 62.26% | 3324 12.81% 75.07% | 3203 12.34% 87.41% | 3268 12.59% 100.00%
-system.ruby.L1Cache_Controller.S.L2_Replacement::total 25955
-system.ruby.L1Cache_Controller.S.L1_to_L2 | 3248 12.40% 12.40% | 3268 12.48% 24.88% | 3269 12.48% 37.36% | 3185 12.16% 49.53% | 3341 12.76% 62.28% | 3367 12.86% 75.14% | 3224 12.31% 87.45% | 3286 12.55% 100.00%
-system.ruby.L1Cache_Controller.S.L1_to_L2::total 26188
-system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 2 7.14% 7.14% | 7 25.00% 32.14% | 2 7.14% 39.29% | 6 21.43% 60.71% | 4 14.29% 75.00% | 3 10.71% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00%
-system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 28
-system.ruby.L1Cache_Controller.S.Other_GETX | 28 12.07% 12.07% | 35 15.09% 27.16% | 28 12.07% 39.22% | 33 14.22% 53.45% | 23 9.91% 63.36% | 45 19.40% 82.76% | 20 8.62% 91.38% | 20 8.62% 100.00%
-system.ruby.L1Cache_Controller.S.Other_GETX::total 232
-system.ruby.L1Cache_Controller.S.Other_GETS | 62 14.62% 14.62% | 53 12.50% 27.12% | 44 10.38% 37.50% | 42 9.91% 47.41% | 54 12.74% 60.14% | 47 11.08% 71.23% | 67 15.80% 87.03% | 55 12.97% 100.00%
-system.ruby.L1Cache_Controller.S.Other_GETS::total 424
-system.ruby.L1Cache_Controller.O.L2_Replacement | 838 12.35% 12.35% | 856 12.62% 24.97% | 806 11.88% 36.86% | 859 12.66% 49.52% | 821 12.10% 61.62% | 862 12.71% 74.33% | 851 12.55% 86.88% | 890 13.12% 100.00%
-system.ruby.L1Cache_Controller.O.L2_Replacement::total 6783
-system.ruby.L1Cache_Controller.O.L1_to_L2 | 81 13.92% 13.92% | 64 11.00% 24.91% | 74 12.71% 37.63% | 70 12.03% 49.66% | 59 10.14% 59.79% | 67 11.51% 71.31% | 86 14.78% 86.08% | 81 13.92% 100.00%
-system.ruby.L1Cache_Controller.O.L1_to_L2::total 582
-system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 1 11.11% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 9
-system.ruby.L1Cache_Controller.O.Other_GETX | 5 16.67% 16.67% | 2 6.67% 23.33% | 5 16.67% 40.00% | 6 20.00% 60.00% | 7 23.33% 83.33% | 1 3.33% 86.67% | 3 10.00% 96.67% | 1 3.33% 100.00%
-system.ruby.L1Cache_Controller.O.Other_GETX::total 30
-system.ruby.L1Cache_Controller.O.Other_GETS | 11 16.42% 16.42% | 8 11.94% 28.36% | 6 8.96% 37.31% | 10 14.93% 52.24% | 9 13.43% 65.67% | 9 13.43% 79.10% | 5 7.46% 86.57% | 9 13.43% 100.00%
-system.ruby.L1Cache_Controller.O.Other_GETS::total 67
-system.ruby.L1Cache_Controller.O.Merged_GETS | 0 0.00% 0.00% | 2 11.11% 11.11% | 3 16.67% 27.78% | 1 5.56% 33.33% | 4 22.22% 55.56% | 4 22.22% 77.78% | 1 5.56% 83.33% | 3 16.67% 100.00%
-system.ruby.L1Cache_Controller.O.Merged_GETS::total 18
-system.ruby.L1Cache_Controller.M.Load | 7 21.21% 21.21% | 3 9.09% 30.30% | 7 21.21% 51.52% | 1 3.03% 54.55% | 5 15.15% 69.70% | 4 12.12% 81.82% | 2 6.06% 87.88% | 4 12.12% 100.00%
-system.ruby.L1Cache_Controller.M.Load::total 33
-system.ruby.L1Cache_Controller.M.Store | 2 13.33% 13.33% | 0 0.00% 13.33% | 1 6.67% 20.00% | 3 20.00% 40.00% | 4 26.67% 66.67% | 2 13.33% 80.00% | 3 20.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.M.Store::total 15
-system.ruby.L1Cache_Controller.M.L2_Replacement | 45788 12.46% 12.46% | 46023 12.52% 24.98% | 45848 12.48% 37.46% | 46041 12.53% 49.99% | 45893 12.49% 62.48% | 45908 12.49% 74.97% | 45944 12.50% 87.48% | 46021 12.52% 100.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement::total 367466
-system.ruby.L1Cache_Controller.M.L1_to_L2 | 46942 12.45% 12.45% | 47247 12.53% 24.98% | 47018 12.47% 37.45% | 47302 12.54% 49.99% | 47109 12.49% 62.48% | 47115 12.49% 74.98% | 47118 12.50% 87.47% | 47240 12.53% 100.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2::total 377091
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 39 12.30% 12.30% | 35 11.04% 23.34% | 34 10.73% 34.07% | 45 14.20% 48.26% | 36 11.36% 59.62% | 34 10.73% 70.35% | 43 13.56% 83.91% | 51 16.09% 100.00%
-system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 317
-system.ruby.L1Cache_Controller.M.Other_GETX | 426 11.63% 11.63% | 469 12.80% 24.43% | 474 12.94% 37.36% | 499 13.62% 50.98% | 473 12.91% 63.89% | 454 12.39% 76.28% | 433 11.82% 88.10% | 436 11.90% 100.00%
-system.ruby.L1Cache_Controller.M.Other_GETX::total 3664
-system.ruby.L1Cache_Controller.M.Other_GETS | 726 12.31% 12.31% | 735 12.46% 24.77% | 709 12.02% 36.79% | 751 12.73% 49.52% | 725 12.29% 61.81% | 746 12.65% 74.45% | 739 12.53% 86.98% | 768 13.02% 100.00%
-system.ruby.L1Cache_Controller.M.Other_GETS::total 5899
-system.ruby.L1Cache_Controller.M.Merged_GETS | 78 13.59% 13.59% | 87 15.16% 28.75% | 57 9.93% 38.68% | 69 12.02% 50.70% | 61 10.63% 61.32% | 73 12.72% 74.04% | 73 12.72% 86.76% | 76 13.24% 100.00%
-system.ruby.L1Cache_Controller.M.Merged_GETS::total 574
-system.ruby.L1Cache_Controller.MM.Load | 1 5.56% 5.56% | 2 11.11% 16.67% | 1 5.56% 22.22% | 6 33.33% 55.56% | 3 16.67% 72.22% | 1 5.56% 77.78% | 1 5.56% 83.33% | 3 16.67% 100.00%
-system.ruby.L1Cache_Controller.MM.Load::total 18
-system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 42.86% 42.86% | 0 0.00% 42.86% | 2 28.57% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00%
-system.ruby.L1Cache_Controller.MM.Store::total 7
-system.ruby.L1Cache_Controller.MM.L2_Replacement | 27344 12.53% 12.53% | 27393 12.55% 25.08% | 27539 12.62% 37.69% | 26899 12.32% 50.02% | 27526 12.61% 62.63% | 27228 12.47% 75.10% | 27201 12.46% 87.56% | 27148 12.44% 100.00%
-system.ruby.L1Cache_Controller.MM.L2_Replacement::total 218278
-system.ruby.L1Cache_Controller.MM.L1_to_L2 | 28016 12.51% 12.51% | 28156 12.57% 25.08% | 28260 12.62% 37.69% | 27634 12.34% 50.03% | 28206 12.59% 62.62% | 27940 12.47% 75.09% | 27939 12.47% 87.56% | 27858 12.44% 100.00%
-system.ruby.L1Cache_Controller.MM.L1_to_L2::total 224009
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 24 12.06% 12.06% | 21 10.55% 22.61% | 24 12.06% 34.67% | 19 9.55% 44.22% | 28 14.07% 58.29% | 24 12.06% 70.35% | 37 18.59% 88.94% | 22 11.06% 100.00%
-system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 199
-system.ruby.L1Cache_Controller.MM.Other_GETX | 248 11.64% 11.64% | 283 13.29% 24.93% | 265 12.44% 37.37% | 277 13.00% 50.38% | 266 12.49% 62.86% | 250 11.74% 74.60% | 302 14.18% 88.78% | 239 11.22% 100.00%
-system.ruby.L1Cache_Controller.MM.Other_GETX::total 2130
-system.ruby.L1Cache_Controller.MM.Other_GETS | 402 11.45% 11.45% | 475 13.53% 24.98% | 443 12.62% 37.60% | 447 12.73% 50.33% | 400 11.39% 61.72% | 455 12.96% 74.68% | 437 12.45% 87.13% | 452 12.87% 100.00%
-system.ruby.L1Cache_Controller.MM.Other_GETS::total 3511
-system.ruby.L1Cache_Controller.MM.Merged_GETS | 40 11.66% 11.66% | 38 11.08% 22.74% | 45 13.12% 35.86% | 45 13.12% 48.98% | 42 12.24% 61.22% | 44 12.83% 74.05% | 42 12.24% 86.30% | 47 13.70% 100.00%
-system.ruby.L1Cache_Controller.MM.Merged_GETS::total 343
-system.ruby.L1Cache_Controller.IR.Load | 1 11.11% 11.11% | 1 11.11% 22.22% | 1 11.11% 33.33% | 0 0.00% 33.33% | 2 22.22% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00%
-system.ruby.L1Cache_Controller.IR.Load::total 9
-system.ruby.L1Cache_Controller.IR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
-system.ruby.L1Cache_Controller.IR.Store::total 1
-system.ruby.L1Cache_Controller.IR.L1_to_L2 | 0 0.00% 0.00% | 10 71.43% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 1 7.14% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00%
-system.ruby.L1Cache_Controller.IR.L1_to_L2::total 14
-system.ruby.L1Cache_Controller.SR.Load | 2 10.00% 10.00% | 4 20.00% 30.00% | 2 10.00% 40.00% | 4 20.00% 60.00% | 3 15.00% 75.00% | 3 15.00% 90.00% | 0 0.00% 90.00% | 2 10.00% 100.00%
-system.ruby.L1Cache_Controller.SR.Load::total 20
-system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 3 37.50% 37.50% | 0 0.00% 37.50% | 2 25.00% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SR.Store::total 8
-system.ruby.L1Cache_Controller.SR.L1_to_L2 | 8 12.70% 12.70% | 13 20.63% 33.33% | 6 9.52% 42.86% | 18 28.57% 71.43% | 12 19.05% 90.48% | 6 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SR.L1_to_L2::total 63
-system.ruby.L1Cache_Controller.OR.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 28.57% 28.57% | 0 0.00% 28.57% | 2 28.57% 57.14% | 0 0.00% 57.14% | 2 28.57% 85.71% | 1 14.29% 100.00%
-system.ruby.L1Cache_Controller.OR.Load::total 7
-system.ruby.L1Cache_Controller.OR.Store | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OR.Store::total 2
-system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 7.14% 7.14% | 0 0.00% 7.14% | 7 50.00% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 6 42.86% 100.00%
-system.ruby.L1Cache_Controller.OR.L1_to_L2::total 14
-system.ruby.L1Cache_Controller.MR.Load | 27 12.62% 12.62% | 21 9.81% 22.43% | 24 11.21% 33.64% | 30 14.02% 47.66% | 23 10.75% 58.41% | 22 10.28% 68.69% | 29 13.55% 82.24% | 38 17.76% 100.00%
-system.ruby.L1Cache_Controller.MR.Load::total 214
-system.ruby.L1Cache_Controller.MR.Store | 12 11.65% 11.65% | 14 13.59% 25.24% | 10 9.71% 34.95% | 15 14.56% 49.51% | 13 12.62% 62.14% | 12 11.65% 73.79% | 14 13.59% 87.38% | 13 12.62% 100.00%
-system.ruby.L1Cache_Controller.MR.Store::total 103
-system.ruby.L1Cache_Controller.MR.L1_to_L2 | 54 9.57% 9.57% | 59 10.46% 20.04% | 75 13.30% 33.33% | 104 18.44% 51.77% | 53 9.40% 61.17% | 57 10.11% 71.28% | 95 16.84% 88.12% | 67 11.88% 100.00%
-system.ruby.L1Cache_Controller.MR.L1_to_L2::total 564
-system.ruby.L1Cache_Controller.MMR.Load | 18 14.75% 14.75% | 8 6.56% 21.31% | 19 15.57% 36.89% | 9 7.38% 44.26% | 14 11.48% 55.74% | 14 11.48% 67.21% | 25 20.49% 87.70% | 15 12.30% 100.00%
-system.ruby.L1Cache_Controller.MMR.Load::total 122
-system.ruby.L1Cache_Controller.MMR.Store | 6 7.79% 7.79% | 13 16.88% 24.68% | 5 6.49% 31.17% | 10 12.99% 44.16% | 14 18.18% 62.34% | 10 12.99% 75.32% | 12 15.58% 90.91% | 7 9.09% 100.00%
-system.ruby.L1Cache_Controller.MMR.Store::total 77
-system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 70 21.60% 21.60% | 45 13.89% 35.49% | 31 9.57% 45.06% | 21 6.48% 51.54% | 26 8.02% 59.57% | 33 10.19% 69.75% | 71 21.91% 91.67% | 27 8.33% 100.00%
-system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 324
-system.ruby.L1Cache_Controller.IM.L1_to_L2 | 278922 12.54% 12.54% | 278884 12.54% 25.09% | 280828 12.63% 37.71% | 276004 12.41% 50.13% | 281673 12.67% 62.79% | 275479 12.39% 75.18% | 275157 12.37% 87.56% | 276670 12.44% 100.00%
-system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2223617
-system.ruby.L1Cache_Controller.IM.Other_GETX | 62 11.50% 11.50% | 80 14.84% 26.35% | 63 11.69% 38.03% | 64 11.87% 49.91% | 49 9.09% 59.00% | 79 14.66% 73.65% | 68 12.62% 86.27% | 74 13.73% 100.00%
-system.ruby.L1Cache_Controller.IM.Other_GETX::total 539
-system.ruby.L1Cache_Controller.IM.Other_GETS | 122 13.19% 13.19% | 114 12.32% 25.51% | 111 12.00% 37.51% | 122 13.19% 50.70% | 132 14.27% 64.97% | 114 12.32% 77.30% | 111 12.00% 89.30% | 99 10.70% 100.00%
-system.ruby.L1Cache_Controller.IM.Other_GETS::total 925
-system.ruby.L1Cache_Controller.IM.Ack | 136672 12.48% 12.48% | 137498 12.56% 25.04% | 139357 12.73% 37.77% | 134236 12.26% 50.03% | 137674 12.57% 62.61% | 136413 12.46% 75.07% | 136515 12.47% 87.54% | 136466 12.46% 100.00%
-system.ruby.L1Cache_Controller.IM.Ack::total 1094831
-system.ruby.L1Cache_Controller.IM.Data | 1385 12.77% 12.77% | 1390 12.82% 25.59% | 1413 13.03% 38.62% | 1313 12.11% 50.72% | 1321 12.18% 62.90% | 1338 12.34% 75.24% | 1325 12.22% 87.46% | 1360 12.54% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 10845
-system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26634 12.49% 12.49% | 26785 12.56% 25.04% | 26868 12.60% 37.64% | 26334 12.35% 49.99% | 26894 12.61% 62.60% | 26626 12.48% 75.08% | 26639 12.49% 87.57% | 26515 12.43% 100.00%
-system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 213295
-system.ruby.L1Cache_Controller.SM.L1_to_L2 | 4 7.27% 7.27% | 12 21.82% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 39 70.91% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SM.L1_to_L2::total 55
-system.ruby.L1Cache_Controller.SM.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SM.Other_GETX::total 1
-system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 14 60.87% 60.87% | 0 0.00% 60.87% | 8 34.78% 95.65% | 0 0.00% 95.65% | 0 0.00% 95.65% | 1 4.35% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 23
-system.ruby.L1Cache_Controller.SM.Data | 1 11.11% 11.11% | 3 33.33% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 3 33.33% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SM.Data::total 9
-system.ruby.L1Cache_Controller.OM.L1_to_L2 | 32 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OM.L1_to_L2::total 32
-system.ruby.L1Cache_Controller.OM.Ack | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OM.Ack::total 14
-system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 2
-system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1654 14.08% 14.08% | 1334 11.36% 25.44% | 1564 13.32% 38.75% | 1401 11.93% 50.68% | 1584 13.49% 64.17% | 1430 12.17% 76.34% | 1334 11.36% 87.70% | 1445 12.30% 100.00%
-system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 11746
-system.ruby.L1Cache_Controller.ISM.Ack | 3080 13.09% 13.09% | 2971 12.63% 25.72% | 2974 12.64% 38.36% | 2882 12.25% 50.61% | 2947 12.52% 63.13% | 3048 12.95% 76.08% | 2844 12.09% 88.17% | 2783 11.83% 100.00%
-system.ruby.L1Cache_Controller.ISM.Ack::total 23529
-system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1386 12.77% 12.77% | 1393 12.83% 25.60% | 1413 13.02% 38.62% | 1315 12.12% 50.74% | 1321 12.17% 62.91% | 1338 12.33% 75.23% | 1328 12.24% 87.47% | 1360 12.53% 100.00%
-system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10854
-system.ruby.L1Cache_Controller.M_W.Load | 1 5.00% 5.00% | 2 10.00% 15.00% | 3 15.00% 30.00% | 3 15.00% 45.00% | 5 25.00% 70.00% | 4 20.00% 90.00% | 1 5.00% 95.00% | 1 5.00% 100.00%
-system.ruby.L1Cache_Controller.M_W.Load::total 20
-system.ruby.L1Cache_Controller.M_W.Store | 2 12.50% 12.50% | 1 6.25% 18.75% | 3 18.75% 37.50% | 4 25.00% 62.50% | 4 25.00% 87.50% | 1 6.25% 93.75% | 0 0.00% 93.75% | 1 6.25% 100.00%
-system.ruby.L1Cache_Controller.M_W.Store::total 16
-system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 74211 12.51% 12.51% | 73890 12.45% 24.96% | 73594 12.40% 37.36% | 74076 12.48% 49.84% | 74874 12.62% 62.46% | 75025 12.64% 75.10% | 73018 12.30% 87.40% | 74757 12.60% 100.00%
-system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 593445
-system.ruby.L1Cache_Controller.M_W.Ack | 97926 12.44% 12.44% | 97718 12.42% 24.86% | 98794 12.55% 37.42% | 98518 12.52% 49.94% | 99085 12.59% 62.53% | 98436 12.51% 75.04% | 97279 12.36% 87.40% | 99172 12.60% 100.00%
-system.ruby.L1Cache_Controller.M_W.Ack::total 786928
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47035 12.45% 12.45% | 47328 12.53% 24.98% | 47103 12.47% 37.45% | 47380 12.54% 49.99% | 47173 12.49% 62.48% | 47199 12.49% 74.98% | 47210 12.50% 87.47% | 47319 12.53% 100.00%
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 377747
-system.ruby.L1Cache_Controller.MM_W.Load | 1 5.26% 5.26% | 3 15.79% 21.05% | 1 5.26% 26.32% | 3 15.79% 42.11% | 4 21.05% 63.16% | 2 10.53% 73.68% | 3 15.79% 89.47% | 2 10.53% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Load::total 19
-system.ruby.L1Cache_Controller.MM_W.Store | 3 42.86% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213577
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 965.002013
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 693.262198
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 669.469949
+system.ruby.ST.Directory.miss_type_mach_latency_hist | 78892 36.94% 36.94% | 40040 18.75% 55.69% | 40325 18.88% 74.57% | 41749 19.55% 94.11% | 11679 5.47% 99.58% | 862 0.40% 99.99% | 29 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213577
+system.ruby.Directory_Controller.GETX 227677 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 408275 0.00% 0.00%
+system.ruby.Directory_Controller.PUT 604225 0.00% 0.00%
+system.ruby.Directory_Controller.Unblock 1518 0.00% 0.00%
+system.ruby.Directory_Controller.UnblockS 26146 0.00% 0.00%
+system.ruby.Directory_Controller.UnblockM 599871 0.00% 0.00%
+system.ruby.Directory_Controller.Writeback_Clean 7905 0.00% 0.00%
+system.ruby.Directory_Controller.Writeback_Dirty 1418 0.00% 0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean 360062 0.00% 0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 219677 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 605779 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 221094 0.00% 0.00%
+system.ruby.Directory_Controller.All_Unblocks 1058 0.00% 0.00%
+system.ruby.Directory_Controller.NX.GETX 87 0.00% 0.00%
+system.ruby.Directory_Controller.NX.GETS 94 0.00% 0.00%
+system.ruby.Directory_Controller.NX.PUT 10803 0.00% 0.00%
+system.ruby.Directory_Controller.NO.GETX 7224 0.00% 0.00%
+system.ruby.Directory_Controller.NO.GETS 11783 0.00% 0.00%
+system.ruby.Directory_Controller.NO.PUT 579803 0.00% 0.00%
+system.ruby.Directory_Controller.O.GETX 9234 0.00% 0.00%
+system.ruby.Directory_Controller.O.GETS 16635 0.00% 0.00%
+system.ruby.Directory_Controller.E.GETX 207154 0.00% 0.00%
+system.ruby.Directory_Controller.E.GETS 372772 0.00% 0.00%
+system.ruby.Directory_Controller.E.PUT 1 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B.GETX 582 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B.GETS 1058 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B.PUT 13362 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B.UnblockS 8383 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM 598303 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_X.PUT 16 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_X.UnblockS 26 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_X.UnblockM 556 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S.GETS 1 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S.PUT 37 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S.UnblockS 46 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S.UnblockM 1012 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S_W.GETX 4 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S_W.GETS 1 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S_W.PUT 138 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S_W.UnblockS 1059 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 1058 0.00% 0.00%
+system.ruby.Directory_Controller.O_B.GETX 9 0.00% 0.00%
+system.ruby.Directory_Controller.O_B.GETS 25 0.00% 0.00%
+system.ruby.Directory_Controller.O_B.UnblockS 16632 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_W.GETX 1927 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_W.GETS 3352 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data 589145 0.00% 0.00%
+system.ruby.Directory_Controller.O_B_W.GETX 51 0.00% 0.00%
+system.ruby.Directory_Controller.O_B_W.GETS 103 0.00% 0.00%
+system.ruby.Directory_Controller.O_B_W.Memory_Data 16634 0.00% 0.00%
+system.ruby.Directory_Controller.WB.GETX 1371 0.00% 0.00%
+system.ruby.Directory_Controller.WB.GETS 2380 0.00% 0.00%
+system.ruby.Directory_Controller.WB.PUT 65 0.00% 0.00%
+system.ruby.Directory_Controller.WB.Unblock 1518 0.00% 0.00%
+system.ruby.Directory_Controller.WB.Writeback_Clean 7905 0.00% 0.00%
+system.ruby.Directory_Controller.WB.Writeback_Dirty 1418 0.00% 0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 360062 0.00% 0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 219677 0.00% 0.00%
+system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1418 0.00% 0.00%
+system.ruby.Directory_Controller.WB_E_W.GETX 34 0.00% 0.00%
+system.ruby.Directory_Controller.WB_E_W.GETS 71 0.00% 0.00%
+system.ruby.Directory_Controller.WB_E_W.Memory_Ack 219676 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load | 50441 12.51% 12.51% | 50284 12.47% 24.99% | 50341 12.49% 37.48% | 50472 12.52% 50.00% | 50384 12.50% 62.50% | 50303 12.48% 74.98% | 50287 12.48% 87.45% | 50586 12.55% 100.00%
+system.ruby.L1Cache_Controller.Load::total 403098
+system.ruby.L1Cache_Controller.Store | 27978 12.49% 12.49% | 27946 12.47% 24.96% | 28262 12.61% 37.57% | 27557 12.30% 49.87% | 28153 12.56% 62.43% | 28184 12.58% 75.01% | 27910 12.46% 87.47% | 28086 12.53% 100.00%
+system.ruby.L1Cache_Controller.Store::total 224076
+system.ruby.L1Cache_Controller.L2_Replacement | 78258 12.50% 12.50% | 78079 12.47% 24.98% | 78452 12.53% 37.51% | 77881 12.44% 49.95% | 78395 12.52% 62.48% | 78336 12.51% 74.99% | 78026 12.47% 87.45% | 78526 12.55% 100.00%
+system.ruby.L1Cache_Controller.L2_Replacement::total 625953
+system.ruby.L1Cache_Controller.L1_to_L2 | 976938 12.50% 12.50% | 978501 12.52% 25.01% | 977534 12.50% 37.52% | 974694 12.47% 49.98% | 977852 12.51% 62.49% | 976494 12.49% 74.98% | 976920 12.50% 87.48% | 978975 12.52% 100.00%
+system.ruby.L1Cache_Controller.L1_to_L2::total 7817908
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 73 13.37% 13.37% | 64 11.72% 25.09% | 59 10.81% 35.90% | 74 13.55% 49.45% | 63 11.54% 60.99% | 64 11.72% 72.71% | 79 14.47% 87.18% | 70 12.82% 100.00%
+system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 546
+system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 73 13.37% 13.37% | 64 11.72% 25.09% | 59 10.81% 35.90% | 74 13.55% 49.45% | 63 11.54% 60.99% | 64 11.72% 72.71% | 79 14.47% 87.18% | 70 12.82% 100.00%
+system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 546
+system.ruby.L1Cache_Controller.Other_GETX | 195769 12.50% 12.50% | 195808 12.50% 25.01% | 195461 12.48% 37.49% | 196183 12.53% 50.02% | 195586 12.49% 62.51% | 195564 12.49% 75.00% | 195830 12.51% 87.50% | 195657 12.50% 100.00%
+system.ruby.L1Cache_Controller.Other_GETX::total 1565858
+system.ruby.L1Cache_Controller.Other_GETS | 351064 12.50% 12.50% | 351190 12.50% 25.00% | 351149 12.50% 37.50% | 351024 12.50% 50.00% | 351114 12.50% 62.50% | 351209 12.50% 75.00% | 351228 12.50% 87.51% | 350905 12.49% 100.00%
+system.ruby.L1Cache_Controller.Other_GETS::total 2808883
+system.ruby.L1Cache_Controller.Merged_GETS | 139 13.14% 13.14% | 131 12.38% 25.52% | 122 11.53% 37.05% | 152 14.37% 51.42% | 142 13.42% 64.84% | 100 9.45% 74.29% | 131 12.38% 86.67% | 141 13.33% 100.00%
+system.ruby.L1Cache_Controller.Merged_GETS::total 1058
+system.ruby.L1Cache_Controller.Ack | 544353 12.50% 12.50% | 543353 12.48% 24.98% | 545955 12.54% 37.51% | 541876 12.44% 49.95% | 545429 12.52% 62.48% | 544934 12.51% 74.99% | 542876 12.47% 87.46% | 546350 12.54% 100.00%
+system.ruby.L1Cache_Controller.Ack::total 4355126
+system.ruby.L1Cache_Controller.Shared_Ack | 59 14.01% 14.01% | 38 9.03% 23.04% | 47 11.16% 34.20% | 57 13.54% 47.74% | 44 10.45% 58.19% | 52 12.35% 70.55% | 63 14.96% 85.51% | 61 14.49% 100.00%
+system.ruby.L1Cache_Controller.Shared_Ack::total 421
+system.ruby.L1Cache_Controller.Data | 3443 12.55% 12.55% | 3428 12.50% 25.05% | 3401 12.40% 37.44% | 3393 12.37% 49.81% | 3427 12.49% 62.30% | 3495 12.74% 75.04% | 3416 12.45% 87.49% | 3431 12.51% 100.00%
+system.ruby.L1Cache_Controller.Data::total 27434
+system.ruby.L1Cache_Controller.Shared_Data | 1248 13.12% 13.12% | 1157 12.16% 25.28% | 1179 12.39% 37.67% | 1166 12.26% 49.93% | 1183 12.43% 62.36% | 1208 12.70% 75.06% | 1185 12.46% 87.51% | 1188 12.49% 100.00%
+system.ruby.L1Cache_Controller.Shared_Data::total 9514
+system.ruby.L1Cache_Controller.Exclusive_Data | 73575 12.49% 12.49% | 73502 12.48% 24.97% | 73882 12.54% 37.51% | 73331 12.45% 49.96% | 73794 12.53% 62.48% | 73640 12.50% 74.99% | 73433 12.47% 87.45% | 73919 12.55% 100.00%
+system.ruby.L1Cache_Controller.Exclusive_Data::total 589076
+system.ruby.L1Cache_Controller.Writeback_Ack | 73741 12.49% 12.49% | 73736 12.49% 24.97% | 74045 12.54% 37.51% | 73508 12.45% 49.96% | 74018 12.53% 62.49% | 73844 12.50% 74.99% | 73562 12.46% 87.45% | 74128 12.55% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total 590582
+system.ruby.L1Cache_Controller.Writeback_Nack | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Nack::total 1
+system.ruby.L1Cache_Controller.All_acks | 1299 13.13% 13.13% | 1192 12.05% 25.18% | 1222 12.35% 37.54% | 1212 12.25% 49.79% | 1221 12.34% 62.14% | 1259 12.73% 74.87% | 1245 12.59% 87.45% | 1241 12.55% 100.00%
+system.ruby.L1Cache_Controller.All_acks::total 9891
+system.ruby.L1Cache_Controller.All_acks_no_sharers | 76966 12.49% 12.49% | 76895 12.48% 24.97% | 77240 12.54% 37.51% | 76678 12.45% 49.95% | 77182 12.53% 62.48% | 77082 12.51% 74.99% | 76789 12.46% 87.45% | 77296 12.55% 100.00%
+system.ruby.L1Cache_Controller.All_acks_no_sharers::total 616128
+system.ruby.L1Cache_Controller.I.Load | 50343 12.51% 12.51% | 50202 12.48% 24.99% | 50229 12.48% 37.47% | 50381 12.52% 50.00% | 50297 12.50% 62.50% | 50214 12.48% 74.98% | 50172 12.47% 87.45% | 50503 12.55% 100.00%
+system.ruby.L1Cache_Controller.I.Load::total 402341
+system.ruby.L1Cache_Controller.I.Store | 27925 12.48% 12.48% | 27886 12.47% 24.95% | 28233 12.62% 37.57% | 27511 12.30% 49.87% | 28108 12.57% 62.44% | 28131 12.58% 75.01% | 27864 12.46% 87.47% | 28034 12.53% 100.00%
+system.ruby.L1Cache_Controller.I.Store::total 223692
+system.ruby.L1Cache_Controller.I.L2_Replacement | 1231 13.06% 13.06% | 1181 12.53% 25.59% | 1181 12.53% 38.11% | 1159 12.29% 50.41% | 1164 12.35% 62.76% | 1144 12.14% 74.89% | 1231 13.06% 87.95% | 1136 12.05% 100.00%
+system.ruby.L1Cache_Controller.I.L2_Replacement::total 9427
+system.ruby.L1Cache_Controller.I.L1_to_L2 | 85 12.25% 12.25% | 91 13.11% 25.36% | 73 10.52% 35.88% | 83 11.96% 47.84% | 90 12.97% 60.81% | 97 13.98% 74.78% | 89 12.82% 87.61% | 86 12.39% 100.00%
+system.ruby.L1Cache_Controller.I.L1_to_L2::total 694
+system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 0 0.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00%
+system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total 8
+system.ruby.L1Cache_Controller.I.Other_GETX | 194598 12.50% 12.50% | 194683 12.50% 25.00% | 194349 12.48% 37.49% | 195081 12.53% 50.02% | 194486 12.49% 62.51% | 194479 12.49% 75.00% | 194715 12.51% 87.51% | 194530 12.49% 100.00%
+system.ruby.L1Cache_Controller.I.Other_GETX::total 1556921
+system.ruby.L1Cache_Controller.I.Other_GETS | 349168 12.50% 12.50% | 349401 12.51% 25.00% | 349271 12.50% 37.50% | 349157 12.50% 50.00% | 349254 12.50% 62.50% | 349362 12.50% 75.00% | 349363 12.50% 87.51% | 349100 12.49% 100.00%
+system.ruby.L1Cache_Controller.I.Other_GETS::total 2794076
+system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.S.Load::total 2
+system.ruby.L1Cache_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.S.Store::total 1
+system.ruby.L1Cache_Controller.S.L2_Replacement | 3281 12.66% 12.66% | 3158 12.19% 24.84% | 3224 12.44% 37.28% | 3212 12.39% 49.68% | 3210 12.39% 62.06% | 3343 12.90% 74.96% | 3230 12.46% 87.43% | 3259 12.57% 100.00%
+system.ruby.L1Cache_Controller.S.L2_Replacement::total 25917
+system.ruby.L1Cache_Controller.S.L1_to_L2 | 3309 12.66% 12.66% | 3182 12.17% 24.83% | 3249 12.43% 37.26% | 3236 12.38% 49.64% | 3243 12.41% 62.05% | 3372 12.90% 74.95% | 3258 12.46% 87.41% | 3290 12.59% 100.00%
+system.ruby.L1Cache_Controller.S.L1_to_L2::total 26139
+system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 1 5.56% 5.56% | 2 11.11% 16.67% | 1 5.56% 22.22% | 5 27.78% 50.00% | 0 0.00% 50.00% | 1 5.56% 55.56% | 3 16.67% 72.22% | 5 27.78% 100.00%
+system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 18
+system.ruby.L1Cache_Controller.S.Other_GETX | 27 12.16% 12.16% | 23 10.36% 22.52% | 25 11.26% 33.78% | 23 10.36% 44.14% | 37 16.67% 60.81% | 31 13.96% 74.77% | 28 12.61% 87.39% | 28 12.61% 100.00%
+system.ruby.L1Cache_Controller.S.Other_GETX::total 222
+system.ruby.L1Cache_Controller.S.Other_GETS | 50 11.88% 11.88% | 58 13.78% 25.65% | 48 11.40% 37.05% | 57 13.54% 50.59% | 53 12.59% 63.18% | 48 11.40% 74.58% | 56 13.30% 87.89% | 51 12.11% 100.00%
+system.ruby.L1Cache_Controller.S.Other_GETS::total 421
+system.ruby.L1Cache_Controller.O.L2_Replacement | 853 12.74% 12.74% | 805 12.02% 24.76% | 861 12.86% 37.62% | 860 12.84% 50.46% | 837 12.50% 62.96% | 826 12.34% 75.30% | 802 11.98% 87.28% | 852 12.72% 100.00%
+system.ruby.L1Cache_Controller.O.L2_Replacement::total 6696
+system.ruby.L1Cache_Controller.O.L1_to_L2 | 72 12.50% 12.50% | 69 11.98% 24.48% | 72 12.50% 36.98% | 78 13.54% 50.52% | 78 13.54% 64.06% | 62 10.76% 74.83% | 75 13.02% 87.85% | 70 12.15% 100.00%
+system.ruby.L1Cache_Controller.O.L1_to_L2::total 576
+system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
+system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 5
+system.ruby.L1Cache_Controller.O.Other_GETX | 6 12.77% 12.77% | 5 10.64% 23.40% | 9 19.15% 42.55% | 8 17.02% 59.57% | 7 14.89% 74.47% | 3 6.38% 80.85% | 7 14.89% 95.74% | 2 4.26% 100.00%
+system.ruby.L1Cache_Controller.O.Other_GETX::total 47
+system.ruby.L1Cache_Controller.O.Other_GETS | 8 16.33% 16.33% | 5 10.20% 26.53% | 4 8.16% 34.69% | 7 14.29% 48.98% | 4 8.16% 57.14% | 9 18.37% 75.51% | 5 10.20% 85.71% | 7 14.29% 100.00%
+system.ruby.L1Cache_Controller.O.Other_GETS::total 49
+system.ruby.L1Cache_Controller.O.Merged_GETS | 3 13.04% 13.04% | 4 17.39% 30.43% | 4 17.39% 47.83% | 3 13.04% 60.87% | 4 17.39% 78.26% | 2 8.70% 86.96% | 1 4.35% 91.30% | 2 8.70% 100.00%
+system.ruby.L1Cache_Controller.O.Merged_GETS::total 23
+system.ruby.L1Cache_Controller.M.Load | 3 8.33% 8.33% | 5 13.89% 22.22% | 7 19.44% 41.67% | 3 8.33% 50.00% | 6 16.67% 66.67% | 6 16.67% 83.33% | 1 2.78% 86.11% | 5 13.89% 100.00%
+system.ruby.L1Cache_Controller.M.Load::total 36
+system.ruby.L1Cache_Controller.M.Store | 2 11.76% 11.76% | 4 23.53% 35.29% | 3 17.65% 52.94% | 0 0.00% 52.94% | 0 0.00% 52.94% | 5 29.41% 82.35% | 3 17.65% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.M.Store::total 17
+system.ruby.L1Cache_Controller.M.L2_Replacement | 45717 12.49% 12.49% | 45764 12.50% 25.00% | 45686 12.48% 37.48% | 45851 12.53% 50.01% | 45789 12.51% 62.52% | 45558 12.45% 74.97% | 45647 12.47% 87.44% | 45961 12.56% 100.00%
+system.ruby.L1Cache_Controller.M.L2_Replacement::total 365973
+system.ruby.L1Cache_Controller.M.L1_to_L2 | 46965 12.51% 12.51% | 46934 12.50% 25.00% | 46906 12.49% 37.49% | 47064 12.53% 50.02% | 46964 12.50% 62.53% | 46761 12.45% 74.98% | 46832 12.47% 87.45% | 47142 12.55% 100.00%
+system.ruby.L1Cache_Controller.M.L1_to_L2::total 375568
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 43 13.87% 13.87% | 35 11.29% 25.16% | 31 10.00% 35.16% | 44 14.19% 49.35% | 35 11.29% 60.65% | 43 13.87% 74.52% | 42 13.55% 88.06% | 37 11.94% 100.00%
+system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 310
+system.ruby.L1Cache_Controller.M.Other_GETX | 481 13.18% 13.18% | 466 12.77% 25.95% | 455 12.47% 38.42% | 444 12.17% 50.59% | 438 12.00% 62.59% | 461 12.63% 75.23% | 479 13.13% 88.35% | 425 11.65% 100.00%
+system.ruby.L1Cache_Controller.M.Other_GETX::total 3649
+system.ruby.L1Cache_Controller.M.Other_GETS | 748 12.76% 12.76% | 702 11.97% 24.73% | 764 13.03% 37.76% | 746 12.72% 50.48% | 725 12.36% 62.84% | 741 12.64% 75.48% | 698 11.90% 87.38% | 740 12.62% 100.00%
+system.ruby.L1Cache_Controller.M.Other_GETS::total 5864
+system.ruby.L1Cache_Controller.M.Merged_GETS | 64 12.14% 12.14% | 63 11.95% 24.10% | 62 11.76% 35.86% | 79 14.99% 50.85% | 78 14.80% 65.65% | 50 9.49% 75.14% | 63 11.95% 87.10% | 68 12.90% 100.00%
+system.ruby.L1Cache_Controller.M.Merged_GETS::total 527
+system.ruby.L1Cache_Controller.MM.Load | 3 12.00% 12.00% | 1 4.00% 16.00% | 2 8.00% 24.00% | 5 20.00% 44.00% | 4 16.00% 60.00% | 3 12.00% 72.00% | 4 16.00% 88.00% | 3 12.00% 100.00%
+system.ruby.L1Cache_Controller.MM.Load::total 25
+system.ruby.L1Cache_Controller.MM.Store | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 1 9.09% 45.45% | 1 9.09% 54.55% | 0 0.00% 54.55% | 1 9.09% 63.64% | 4 36.36% 100.00%
+system.ruby.L1Cache_Controller.MM.Store::total 11
+system.ruby.L1Cache_Controller.MM.L2_Replacement | 27176 12.47% 12.47% | 27171 12.47% 24.94% | 27500 12.62% 37.55% | 26799 12.30% 49.85% | 27395 12.57% 62.42% | 27465 12.60% 75.02% | 27116 12.44% 87.47% | 27318 12.53% 100.00%
+system.ruby.L1Cache_Controller.MM.L2_Replacement::total 217940
+system.ruby.L1Cache_Controller.MM.L1_to_L2 | 27906 12.48% 12.48% | 27872 12.47% 24.95% | 28217 12.62% 37.57% | 27501 12.30% 49.87% | 28089 12.56% 62.43% | 28113 12.57% 75.01% | 27857 12.46% 87.47% | 28015 12.53% 100.00%
+system.ruby.L1Cache_Controller.MM.L1_to_L2::total 223570
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 27 13.17% 13.17% | 25 12.20% 25.37% | 24 11.71% 37.07% | 25 12.20% 49.27% | 26 12.68% 61.95% | 19 9.27% 71.22% | 33 16.10% 87.32% | 26 12.68% 100.00%
+system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 205
+system.ruby.L1Cache_Controller.MM.Other_GETX | 267 12.74% 12.74% | 270 12.88% 25.62% | 259 12.36% 37.98% | 265 12.64% 50.62% | 246 11.74% 62.36% | 255 12.17% 74.52% | 260 12.40% 86.93% | 274 13.07% 100.00%
+system.ruby.L1Cache_Controller.MM.Other_GETX::total 2096
+system.ruby.L1Cache_Controller.MM.Other_GETS | 451 13.18% 13.18% | 418 12.22% 25.40% | 435 12.72% 38.12% | 419 12.25% 50.37% | 438 12.80% 63.17% | 394 11.52% 74.69% | 458 13.39% 88.07% | 408 11.93% 100.00%
+system.ruby.L1Cache_Controller.MM.Other_GETS::total 3421
+system.ruby.L1Cache_Controller.MM.Merged_GETS | 47 13.31% 13.31% | 45 12.75% 26.06% | 44 12.46% 38.53% | 43 12.18% 50.71% | 42 11.90% 62.61% | 38 10.76% 73.37% | 48 13.60% 86.97% | 46 13.03% 100.00%
+system.ruby.L1Cache_Controller.MM.Merged_GETS::total 353
+system.ruby.L1Cache_Controller.IR.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 2 33.33% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.IR.Load::total 6
+system.ruby.L1Cache_Controller.IR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.IR.Store::total 2
+system.ruby.L1Cache_Controller.IR.L1_to_L2 | 7 35.00% 35.00% | 0 0.00% 35.00% | 1 5.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 12 60.00% 100.00%
+system.ruby.L1Cache_Controller.IR.L1_to_L2::total 20
+system.ruby.L1Cache_Controller.SR.Load | 1 7.69% 7.69% | 1 7.69% 15.38% | 1 7.69% 23.08% | 4 30.77% 53.85% | 0 0.00% 53.85% | 1 7.69% 61.54% | 3 23.08% 84.62% | 2 15.38% 100.00%
+system.ruby.L1Cache_Controller.SR.Load::total 13
+system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 3 60.00% 100.00%
+system.ruby.L1Cache_Controller.SR.Store::total 5
+system.ruby.L1Cache_Controller.SR.L1_to_L2 | 11 21.57% 21.57% | 14 27.45% 49.02% | 0 0.00% 49.02% | 12 23.53% 72.55% | 0 0.00% 72.55% | 0 0.00% 72.55% | 9 17.65% 90.20% | 5 9.80% 100.00%
+system.ruby.L1Cache_Controller.SR.L1_to_L2::total 51
+system.ruby.L1Cache_Controller.OR.Load | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
+system.ruby.L1Cache_Controller.OR.Load::total 5
+system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 6 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.OR.L1_to_L2::total 12
+system.ruby.L1Cache_Controller.MR.Load | 27 13.64% 13.64% | 21 10.61% 24.24% | 27 13.64% 37.88% | 27 13.64% 51.52% | 20 10.10% 61.62% | 23 11.62% 73.23% | 28 14.14% 87.37% | 25 12.63% 100.00%
+system.ruby.L1Cache_Controller.MR.Load::total 198
+system.ruby.L1Cache_Controller.MR.Store | 16 14.29% 14.29% | 14 12.50% 26.79% | 4 3.57% 30.36% | 17 15.18% 45.54% | 15 13.39% 58.93% | 20 17.86% 76.79% | 14 12.50% 89.29% | 12 10.71% 100.00%
+system.ruby.L1Cache_Controller.MR.Store::total 112
+system.ruby.L1Cache_Controller.MR.L1_to_L2 | 88 17.78% 17.78% | 39 7.88% 25.66% | 51 10.30% 35.96% | 88 17.78% 53.74% | 74 14.95% 68.69% | 39 7.88% 76.57% | 69 13.94% 90.51% | 47 9.49% 100.00%
+system.ruby.L1Cache_Controller.MR.L1_to_L2::total 495
+system.ruby.L1Cache_Controller.MMR.Load | 19 13.77% 13.77% | 13 9.42% 23.19% | 18 13.04% 36.23% | 20 14.49% 50.72% | 17 12.32% 63.04% | 13 9.42% 72.46% | 23 16.67% 89.13% | 15 10.87% 100.00%
+system.ruby.L1Cache_Controller.MMR.Load::total 138
+system.ruby.L1Cache_Controller.MMR.Store | 8 11.94% 11.94% | 12 17.91% 29.85% | 6 8.96% 38.81% | 5 7.46% 46.27% | 9 13.43% 59.70% | 6 8.96% 68.66% | 10 14.93% 83.58% | 11 16.42% 100.00%
+system.ruby.L1Cache_Controller.MMR.Store::total 67
+system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 77 18.55% 18.55% | 56 13.49% 32.05% | 70 16.87% 48.92% | 35 8.43% 57.35% | 58 13.98% 71.33% | 20 4.82% 76.14% | 76 18.31% 94.46% | 23 5.54% 100.00%
+system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 415
+system.ruby.L1Cache_Controller.IM.L1_to_L2 | 278544 12.60% 12.60% | 277743 12.56% 25.16% | 280869 12.70% 37.86% | 272194 12.31% 50.17% | 276047 12.48% 62.65% | 276727 12.51% 75.16% | 274477 12.41% 87.57% | 274776 12.43% 100.00%
+system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2211377
+system.ruby.L1Cache_Controller.IM.Other_GETX | 85 16.16% 16.16% | 58 11.03% 27.19% | 69 13.12% 40.30% | 47 8.94% 49.24% | 75 14.26% 63.50% | 70 13.31% 76.81% | 62 11.79% 88.59% | 60 11.41% 100.00%
+system.ruby.L1Cache_Controller.IM.Other_GETX::total 526
+system.ruby.L1Cache_Controller.IM.Other_GETS | 106 11.79% 11.79% | 118 13.13% 24.92% | 113 12.57% 37.49% | 111 12.35% 49.83% | 103 11.46% 61.29% | 111 12.35% 73.64% | 119 13.24% 86.87% | 118 13.13% 100.00%
+system.ruby.L1Cache_Controller.IM.Other_GETS::total 899
+system.ruby.L1Cache_Controller.IM.Ack | 136713 12.57% 12.57% | 135265 12.43% 25.00% | 137767 12.66% 37.67% | 133467 12.27% 49.94% | 136048 12.51% 62.44% | 136618 12.56% 75.00% | 135810 12.49% 87.49% | 136093 12.51% 100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total 1087781
+system.ruby.L1Cache_Controller.IM.Data | 1382 12.80% 12.80% | 1402 12.99% 25.79% | 1328 12.30% 38.10% | 1322 12.25% 50.34% | 1363 12.63% 62.97% | 1329 12.31% 75.28% | 1343 12.44% 87.72% | 1325 12.28% 100.00%
+system.ruby.L1Cache_Controller.IM.Data::total 10794
+system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26543 12.47% 12.47% | 26483 12.44% 24.91% | 26903 12.64% 37.54% | 26188 12.30% 49.85% | 26745 12.56% 62.41% | 26801 12.59% 75.00% | 26521 12.46% 87.45% | 26709 12.55% 100.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 212893
+system.ruby.L1Cache_Controller.SM.L1_to_L2 | 0 0.00% 0.00% | 6 18.18% 18.18% | 4 12.12% 30.30% | 7 21.21% 51.52% | 0 0.00% 51.52% | 0 0.00% 51.52% | 0 0.00% 51.52% | 16 48.48% 100.00%
+system.ruby.L1Cache_Controller.SM.L1_to_L2::total 33
+system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 14 66.67% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total 21
+system.ruby.L1Cache_Controller.SM.Data | 0 0.00% 0.00% | 1 16.67% 16.67% | 1 16.67% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 3 50.00% 100.00%
+system.ruby.L1Cache_Controller.SM.Data::total 6
+system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1378 12.28% 12.28% | 1476 13.15% 25.43% | 1358 12.10% 37.52% | 1291 11.50% 49.02% | 1461 13.02% 62.04% | 1735 15.46% 77.50% | 1152 10.26% 87.76% | 1374 12.24% 100.00%
+system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 11225
+system.ruby.L1Cache_Controller.ISM.Ack | 2968 12.36% 12.36% | 3074 12.80% 25.15% | 2971 12.37% 37.52% | 3107 12.93% 50.46% | 3108 12.94% 63.39% | 3097 12.89% 76.29% | 2854 11.88% 88.17% | 2842 11.83% 100.00%
+system.ruby.L1Cache_Controller.ISM.Ack::total 24021
+system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1382 12.80% 12.80% | 1403 12.99% 25.79% | 1329 12.31% 38.09% | 1323 12.25% 50.34% | 1363 12.62% 62.96% | 1329 12.31% 75.27% | 1343 12.44% 87.70% | 1328 12.30% 100.00%
+system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10800
+system.ruby.L1Cache_Controller.M_W.Load | 2 9.52% 9.52% | 6 28.57% 38.10% | 4 19.05% 57.14% | 1 4.76% 61.90% | 2 9.52% 71.43% | 3 14.29% 85.71% | 3 14.29% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.M_W.Load::total 21
+system.ruby.L1Cache_Controller.M_W.Store | 2 14.29% 14.29% | 4 28.57% 42.86% | 1 7.14% 50.00% | 2 14.29% 64.29% | 1 7.14% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.M_W.Store::total 14
+system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 74738 12.51% 12.51% | 76785 12.85% 25.37% | 73525 12.31% 37.68% | 73939 12.38% 50.05% | 74584 12.49% 62.54% | 74401 12.46% 75.00% | 74616 12.49% 87.49% | 74732 12.51% 100.00%
+system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 597320
+system.ruby.L1Cache_Controller.M_W.Ack | 98263 12.50% 12.50% | 98562 12.53% 25.03% | 97942 12.46% 37.49% | 98017 12.46% 49.95% | 97892 12.45% 62.40% | 97827 12.44% 74.84% | 98974 12.59% 87.43% | 98873 12.57% 100.00%
+system.ruby.L1Cache_Controller.M_W.Ack::total 786350
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47030 12.50% 12.50% | 47015 12.50% 25.00% | 46978 12.49% 37.49% | 47141 12.53% 50.02% | 47047 12.51% 62.53% | 46836 12.45% 74.98% | 46909 12.47% 87.45% | 47210 12.55% 100.00%
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 376166
+system.ruby.L1Cache_Controller.MM_W.Load | 2 11.11% 11.11% | 4 22.22% 33.33% | 2 11.11% 44.44% | 1 5.56% 50.00% | 3 16.67% 66.67% | 4 22.22% 88.89% | 2 11.11% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total 18
+system.ruby.L1Cache_Controller.MM_W.Store | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 1 14.29% 28.57% | 0 0.00% 28.57% | 2 28.57% 57.14% | 2 28.57% 85.71% | 1 14.29% 100.00%
system.ruby.L1Cache_Controller.MM_W.Store::total 7
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 42529 12.65% 12.65% | 42714 12.70% 25.35% | 41979 12.48% 37.83% | 41933 12.47% 50.30% | 42121 12.53% 62.83% | 41515 12.35% 75.17% | 41809 12.43% 87.61% | 41681 12.39% 100.00%
-system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 336281
-system.ruby.L1Cache_Controller.MM_W.Ack | 55486 12.51% 12.51% | 55882 12.60% 25.11% | 54740 12.34% 37.45% | 55509 12.52% 49.97% | 56002 12.63% 62.60% | 55351 12.48% 75.08% | 55541 12.52% 87.60% | 54986 12.40% 100.00%
-system.ruby.L1Cache_Controller.MM_W.Ack::total 443497
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26636 12.49% 12.49% | 26786 12.56% 25.04% | 26871 12.60% 37.64% | 26338 12.35% 49.99% | 26898 12.61% 62.60% | 26627 12.48% 75.08% | 26639 12.49% 87.57% | 26516 12.43% 100.00%
-system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 213311
-system.ruby.L1Cache_Controller.IS.L1_to_L2 | 498344 12.45% 12.45% | 499845 12.49% 24.94% | 498249 12.45% 37.39% | 500193 12.50% 49.89% | 497512 12.43% 62.32% | 502981 12.57% 74.89% | 502709 12.56% 87.45% | 502230 12.55% 100.00%
-system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4002063
-system.ruby.L1Cache_Controller.IS.Other_GETX | 113 12.07% 12.07% | 119 12.71% 24.79% | 115 12.29% 37.07% | 109 11.65% 48.72% | 125 13.35% 62.07% | 123 13.14% 75.21% | 120 12.82% 88.03% | 112 11.97% 100.00%
-system.ruby.L1Cache_Controller.IS.Other_GETX::total 936
-system.ruby.L1Cache_Controller.IS.Other_GETS | 228 14.04% 14.04% | 201 12.38% 26.42% | 192 11.82% 38.24% | 206 12.68% 50.92% | 192 11.82% 62.75% | 195 12.01% 74.75% | 229 14.10% 88.85% | 181 11.15% 100.00%
-system.ruby.L1Cache_Controller.IS.Other_GETS::total 1624
-system.ruby.L1Cache_Controller.IS.Ack | 244442 12.45% 12.45% | 246481 12.56% 25.01% | 244196 12.44% 37.45% | 245842 12.52% 49.98% | 244425 12.45% 62.43% | 245791 12.52% 74.95% | 246310 12.55% 87.50% | 245330 12.50% 100.00%
-system.ruby.L1Cache_Controller.IS.Ack::total 1962817
-system.ruby.L1Cache_Controller.IS.Shared_Ack | 33 10.93% 10.93% | 41 13.58% 24.50% | 32 10.60% 35.10% | 36 11.92% 47.02% | 41 13.58% 60.60% | 49 16.23% 76.82% | 35 11.59% 88.41% | 35 11.59% 100.00%
-system.ruby.L1Cache_Controller.IS.Shared_Ack::total 302
-system.ruby.L1Cache_Controller.IS.Data | 2045 12.34% 12.34% | 2085 12.58% 24.93% | 2074 12.52% 37.45% | 2001 12.08% 49.52% | 2142 12.93% 62.45% | 2131 12.86% 75.31% | 2029 12.25% 87.56% | 2061 12.44% 100.00%
-system.ruby.L1Cache_Controller.IS.Data::total 16568
-system.ruby.L1Cache_Controller.IS.Shared_Data | 1205 12.51% 12.51% | 1184 12.29% 24.80% | 1195 12.41% 37.21% | 1186 12.31% 49.52% | 1199 12.45% 61.97% | 1238 12.85% 74.82% | 1198 12.44% 87.26% | 1227 12.74% 100.00%
-system.ruby.L1Cache_Controller.IS.Shared_Data::total 9632
-system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47037 12.45% 12.45% | 47329 12.53% 24.98% | 47106 12.47% 37.45% | 47384 12.54% 49.99% | 47177 12.49% 62.48% | 47200 12.49% 74.98% | 47210 12.50% 87.47% | 47320 12.53% 100.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 377763
-system.ruby.L1Cache_Controller.SS.Load | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.SS.Load::total 1
-system.ruby.L1Cache_Controller.SS.L1_to_L2 | 5041 12.61% 12.61% | 5297 13.25% 25.86% | 4845 12.12% 37.98% | 4861 12.16% 50.14% | 5186 12.97% 63.12% | 4925 12.32% 75.44% | 4836 12.10% 87.53% | 4983 12.47% 100.00%
-system.ruby.L1Cache_Controller.SS.L1_to_L2::total 39974
-system.ruby.L1Cache_Controller.SS.Ack | 7136 12.32% 12.32% | 7580 13.08% 25.40% | 7139 12.32% 37.72% | 7109 12.27% 49.99% | 7501 12.95% 62.94% | 7189 12.41% 75.35% | 7032 12.14% 87.49% | 7250 12.51% 100.00%
-system.ruby.L1Cache_Controller.SS.Ack::total 57936
-system.ruby.L1Cache_Controller.SS.Shared_Ack | 11 9.02% 9.02% | 23 18.85% 27.87% | 17 13.93% 41.80% | 19 15.57% 57.38% | 17 13.93% 71.31% | 13 10.66% 81.97% | 13 10.66% 92.62% | 9 7.38% 100.00%
-system.ruby.L1Cache_Controller.SS.Shared_Ack::total 122
-system.ruby.L1Cache_Controller.SS.All_acks | 1242 12.43% 12.43% | 1233 12.34% 24.77% | 1238 12.39% 37.16% | 1235 12.36% 49.52% | 1246 12.47% 61.99% | 1291 12.92% 74.91% | 1239 12.40% 87.31% | 1268 12.69% 100.00%
-system.ruby.L1Cache_Controller.SS.All_acks::total 9992
-system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2008 12.39% 12.39% | 2036 12.56% 24.95% | 2031 12.53% 37.48% | 1952 12.04% 49.52% | 2095 12.93% 62.45% | 2078 12.82% 75.27% | 1988 12.27% 87.54% | 2020 12.46% 100.00%
-system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16208
-system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.OI.Load::total 2
-system.ruby.L1Cache_Controller.OI.Other_GETX | 1 6.25% 6.25% | 1 6.25% 12.50% | 4 25.00% 37.50% | 2 12.50% 50.00% | 2 12.50% 62.50% | 2 12.50% 75.00% | 2 12.50% 87.50% | 2 12.50% 100.00%
-system.ruby.L1Cache_Controller.OI.Other_GETX::total 16
-system.ruby.L1Cache_Controller.OI.Other_GETS | 2 7.41% 7.41% | 3 11.11% 18.52% | 5 18.52% 37.04% | 4 14.81% 51.85% | 3 11.11% 62.96% | 3 11.11% 74.07% | 2 7.41% 81.48% | 5 18.52% 100.00%
-system.ruby.L1Cache_Controller.OI.Other_GETS::total 27
-system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 16.67% 16.67% | 4 16.67% 33.33% | 5 20.83% 54.17% | 3 12.50% 66.67% | 1 4.17% 70.83% | 1 4.17% 75.00% | 3 12.50% 87.50% | 3 12.50% 100.00%
-system.ruby.L1Cache_Controller.OI.Merged_GETS::total 24
-system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1199 12.70% 12.70% | 1194 12.64% 25.34% | 1128 11.94% 37.28% | 1165 12.34% 49.62% | 1171 12.40% 62.02% | 1158 12.26% 74.28% | 1204 12.75% 87.03% | 1225 12.97% 100.00%
-system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9444
-system.ruby.L1Cache_Controller.MI.Load | 15 12.82% 12.82% | 22 18.80% 31.62% | 10 8.55% 40.17% | 11 9.40% 49.57% | 19 16.24% 65.81% | 10 8.55% 74.36% | 12 10.26% 84.62% | 18 15.38% 100.00%
-system.ruby.L1Cache_Controller.MI.Load::total 117
-system.ruby.L1Cache_Controller.MI.Store | 13 16.46% 16.46% | 7 8.86% 25.32% | 9 11.39% 36.71% | 4 5.06% 41.77% | 8 10.13% 51.90% | 14 17.72% 69.62% | 18 22.78% 92.41% | 6 7.59% 100.00%
-system.ruby.L1Cache_Controller.MI.Store::total 79
-system.ruby.L1Cache_Controller.MI.Other_GETX | 197 13.47% 13.47% | 173 11.83% 25.31% | 170 11.63% 36.94% | 190 13.00% 49.93% | 203 13.89% 63.82% | 188 12.86% 76.68% | 151 10.33% 87.00% | 190 13.00% 100.00%
-system.ruby.L1Cache_Controller.MI.Other_GETX::total 1462
-system.ruby.L1Cache_Controller.MI.Other_GETS | 348 13.58% 13.58% | 322 12.56% 26.14% | 310 12.10% 38.24% | 294 11.47% 49.71% | 337 13.15% 62.86% | 282 11.00% 73.86% | 343 13.38% 87.24% | 327 12.76% 100.00%
-system.ruby.L1Cache_Controller.MI.Other_GETS::total 2563
-system.ruby.L1Cache_Controller.MI.Merged_GETS | 14 12.28% 12.28% | 17 14.91% 27.19% | 16 14.04% 41.23% | 14 12.28% 53.51% | 15 13.16% 66.67% | 16 14.04% 80.70% | 12 10.53% 91.23% | 10 8.77% 100.00%
-system.ruby.L1Cache_Controller.MI.Merged_GETS::total 114
-system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72569 12.48% 12.48% | 72904 12.54% 25.01% | 72891 12.53% 37.55% | 72442 12.46% 50.00% | 72864 12.53% 62.53% | 72649 12.49% 75.02% | 72638 12.49% 87.51% | 72642 12.49% 100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 581599
-system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 41839 12.37% 12.37% | 42308 12.51% 24.87% | 42669 12.61% 37.49% | 42131 12.45% 49.94% | 42574 12.59% 62.53% | 41857 12.37% 74.90% | 42636 12.60% 87.50% | 42269 12.50% 100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 338283
+system.ruby.L1Cache_Controller.MM_W.Ack | 54858 12.28% 12.28% | 55978 12.53% 24.81% | 55938 12.52% 37.33% | 55130 12.34% 49.66% | 56721 12.69% 62.36% | 56318 12.60% 74.96% | 55482 12.42% 87.38% | 56384 12.62% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Ack::total 446809
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26545 12.47% 12.47% | 26487 12.44% 24.91% | 26904 12.64% 37.55% | 26190 12.30% 49.85% | 26746 12.56% 62.41% | 26802 12.59% 75.00% | 26524 12.46% 87.46% | 26709 12.54% 100.00%
+system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 212907
+system.ruby.L1Cache_Controller.IS.L1_to_L2 | 496961 12.46% 12.46% | 496660 12.45% 24.91% | 494888 12.41% 37.32% | 501380 12.57% 49.89% | 498894 12.51% 62.39% | 497896 12.48% 74.88% | 500417 12.55% 87.42% | 501712 12.58% 100.00%
+system.ruby.L1Cache_Controller.IS.L1_to_L2::total 3988808
+system.ruby.L1Cache_Controller.IS.Other_GETX | 120 13.70% 13.70% | 102 11.64% 25.34% | 104 11.87% 37.21% | 122 13.93% 51.14% | 116 13.24% 64.38% | 92 10.50% 74.89% | 101 11.53% 86.42% | 119 13.58% 100.00%
+system.ruby.L1Cache_Controller.IS.Other_GETX::total 876
+system.ruby.L1Cache_Controller.IS.Other_GETS | 212 13.16% 13.16% | 192 11.92% 25.08% | 219 13.59% 38.67% | 199 12.35% 51.02% | 188 11.67% 62.69% | 205 12.73% 75.42% | 205 12.73% 88.14% | 191 11.86% 100.00%
+system.ruby.L1Cache_Controller.IS.Other_GETS::total 1611
+system.ruby.L1Cache_Controller.IS.Ack | 244322 12.52% 12.52% | 243435 12.47% 24.99% | 243945 12.50% 37.48% | 245096 12.56% 50.04% | 244536 12.53% 62.56% | 243639 12.48% 75.04% | 242664 12.43% 87.48% | 244497 12.52% 100.00%
+system.ruby.L1Cache_Controller.IS.Ack::total 1952134
+system.ruby.L1Cache_Controller.IS.Shared_Ack | 37 12.63% 12.63% | 28 9.56% 22.18% | 26 8.87% 31.06% | 37 12.63% 43.69% | 35 11.95% 55.63% | 36 12.29% 67.92% | 48 16.38% 84.30% | 46 15.70% 100.00%
+system.ruby.L1Cache_Controller.IS.Shared_Ack::total 293
+system.ruby.L1Cache_Controller.IS.Data | 2061 12.39% 12.39% | 2025 12.17% 24.56% | 2072 12.46% 37.02% | 2070 12.44% 49.46% | 2064 12.41% 61.87% | 2166 13.02% 74.89% | 2073 12.46% 87.36% | 2103 12.64% 100.00%
+system.ruby.L1Cache_Controller.IS.Data::total 16634
+system.ruby.L1Cache_Controller.IS.Shared_Data | 1248 13.12% 13.12% | 1157 12.16% 25.28% | 1179 12.39% 37.67% | 1166 12.26% 49.93% | 1183 12.43% 62.36% | 1208 12.70% 75.06% | 1185 12.46% 87.51% | 1188 12.49% 100.00%
+system.ruby.L1Cache_Controller.IS.Shared_Data::total 9514
+system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47032 12.50% 12.50% | 47019 12.50% 25.00% | 46979 12.49% 37.49% | 47143 12.53% 50.02% | 47049 12.51% 62.53% | 46839 12.45% 74.98% | 46912 12.47% 87.45% | 47210 12.55% 100.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 376183
+system.ruby.L1Cache_Controller.SS.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.SS.Load::total 3
+system.ruby.L1Cache_Controller.SS.L1_to_L2 | 4693 11.36% 11.36% | 5086 12.31% 23.68% | 5364 12.99% 36.66% | 5399 13.07% 49.74% | 5426 13.14% 62.87% | 5212 12.62% 75.49% | 4958 12.00% 87.50% | 5163 12.50% 100.00%
+system.ruby.L1Cache_Controller.SS.L1_to_L2::total 41301
+system.ruby.L1Cache_Controller.SS.Ack | 7229 12.46% 12.46% | 7039 12.13% 24.60% | 7385 12.73% 37.33% | 7059 12.17% 49.49% | 7124 12.28% 61.78% | 7435 12.82% 74.59% | 7092 12.23% 86.82% | 7647 13.18% 100.00%
+system.ruby.L1Cache_Controller.SS.Ack::total 58010
+system.ruby.L1Cache_Controller.SS.Shared_Ack | 22 17.19% 17.19% | 10 7.81% 25.00% | 21 16.41% 41.41% | 20 15.62% 57.03% | 9 7.03% 64.06% | 16 12.50% 76.56% | 15 11.72% 88.28% | 15 11.72% 100.00%
+system.ruby.L1Cache_Controller.SS.Shared_Ack::total 128
+system.ruby.L1Cache_Controller.SS.All_acks | 1299 13.13% 13.13% | 1192 12.05% 25.18% | 1222 12.35% 37.54% | 1212 12.25% 49.79% | 1221 12.34% 62.14% | 1259 12.73% 74.87% | 1245 12.59% 87.45% | 1241 12.55% 100.00%
+system.ruby.L1Cache_Controller.SS.All_acks::total 9891
+system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2009 12.36% 12.36% | 1990 12.24% 24.60% | 2029 12.48% 37.08% | 2024 12.45% 49.54% | 2026 12.46% 62.00% | 2115 13.01% 75.01% | 2013 12.38% 87.39% | 2049 12.61% 100.00%
+system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16255
+system.ruby.L1Cache_Controller.OI.Other_GETX | 8 33.33% 33.33% | 5 20.83% 54.17% | 2 8.33% 62.50% | 2 8.33% 70.83% | 0 0.00% 70.83% | 2 8.33% 79.17% | 2 8.33% 87.50% | 3 12.50% 100.00%
+system.ruby.L1Cache_Controller.OI.Other_GETX::total 24
+system.ruby.L1Cache_Controller.OI.Other_GETS | 2 9.52% 9.52% | 4 19.05% 28.57% | 2 9.52% 38.10% | 3 14.29% 52.38% | 2 9.52% 61.90% | 2 9.52% 71.43% | 1 4.76% 76.19% | 5 23.81% 100.00%
+system.ruby.L1Cache_Controller.OI.Other_GETS::total 21
+system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 17.39% 17.39% | 1 4.35% 21.74% | 2 8.70% 30.43% | 4 17.39% 47.83% | 8 34.78% 82.61% | 2 8.70% 91.30% | 0 0.00% 91.30% | 2 8.70% 100.00%
+system.ruby.L1Cache_Controller.OI.Merged_GETS::total 23
+system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1185 12.71% 12.71% | 1110 11.90% 24.61% | 1162 12.46% 37.08% | 1206 12.93% 50.01% | 1193 12.79% 62.81% | 1169 12.54% 75.34% | 1142 12.25% 87.59% | 1157 12.41% 100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9324
+system.ruby.L1Cache_Controller.MI.Load | 12 10.34% 10.34% | 9 7.76% 18.10% | 21 18.10% 36.21% | 10 8.62% 44.83% | 14 12.07% 56.90% | 18 15.52% 72.41% | 19 16.38% 88.79% | 13 11.21% 100.00%
+system.ruby.L1Cache_Controller.MI.Load::total 116
+system.ruby.L1Cache_Controller.MI.Store | 11 17.19% 17.19% | 11 17.19% 34.38% | 8 12.50% 46.88% | 8 12.50% 59.38% | 5 7.81% 67.19% | 9 14.06% 81.25% | 5 7.81% 89.06% | 7 10.94% 100.00%
+system.ruby.L1Cache_Controller.MI.Store::total 64
+system.ruby.L1Cache_Controller.MI.Other_GETX | 176 11.77% 11.77% | 195 13.04% 24.82% | 189 12.64% 37.46% | 191 12.78% 50.23% | 181 12.11% 62.34% | 171 11.44% 73.78% | 176 11.77% 85.55% | 216 14.45% 100.00%
+system.ruby.L1Cache_Controller.MI.Other_GETX::total 1495
+system.ruby.L1Cache_Controller.MI.Other_GETS | 319 12.65% 12.65% | 292 11.58% 24.24% | 293 11.62% 35.86% | 325 12.89% 48.75% | 347 13.76% 62.51% | 337 13.37% 75.88% | 323 12.81% 88.69% | 285 11.31% 100.00%
+system.ruby.L1Cache_Controller.MI.Other_GETS::total 2521
+system.ruby.L1Cache_Controller.MI.Merged_GETS | 21 15.91% 15.91% | 18 13.64% 29.55% | 10 7.58% 37.12% | 23 17.42% 54.55% | 10 7.58% 62.12% | 8 6.06% 68.18% | 19 14.39% 82.58% | 23 17.42% 100.00%
+system.ruby.L1Cache_Controller.MI.Merged_GETS::total 132
+system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72372 12.48% 12.48% | 72427 12.49% 24.98% | 72692 12.54% 37.52% | 72109 12.44% 49.95% | 72644 12.53% 62.48% | 72502 12.51% 74.99% | 72242 12.46% 87.45% | 72752 12.55% 100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 579740
+system.ruby.L1Cache_Controller.II.Load | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.II.Load::total 2
+system.ruby.L1Cache_Controller.II.Other_GETX | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.II.Other_GETX::total 2
-system.ruby.L1Cache_Controller.II.Writeback_Ack | 198 13.40% 13.40% | 174 11.77% 25.17% | 174 11.77% 36.94% | 192 12.99% 49.93% | 205 13.87% 63.80% | 190 12.86% 76.66% | 153 10.35% 87.01% | 192 12.99% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1478
-system.ruby.L1Cache_Controller.IT.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00%
-system.ruby.L1Cache_Controller.IT.Load::total 6
-system.ruby.L1Cache_Controller.IT.L1_to_L2 | 0 0.00% 0.00% | 10 18.87% 18.87% | 0 0.00% 18.87% | 0 0.00% 18.87% | 7 13.21% 32.08% | 0 0.00% 32.08% | 34 64.15% 96.23% | 2 3.77% 100.00%
-system.ruby.L1Cache_Controller.IT.L1_to_L2::total 53
-system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 1 10.00% 10.00% | 1 10.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 3 30.00% 100.00%
-system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total 10
-system.ruby.L1Cache_Controller.ST.Load | 1 14.29% 14.29% | 2 28.57% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.ST.Load::total 7
-system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.ST.Store::total 3
-system.ruby.L1Cache_Controller.ST.L1_to_L2 | 8 8.08% 8.08% | 21 21.21% 29.29% | 6 6.06% 35.35% | 20 20.20% 55.56% | 26 26.26% 81.82% | 7 7.07% 88.89% | 11 11.11% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache_Controller.ST.L1_to_L2::total 99
-system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 2 7.14% 7.14% | 7 25.00% 32.14% | 2 7.14% 39.29% | 6 21.43% 60.71% | 4 14.29% 75.00% | 3 10.71% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00%
-system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 28
-system.ruby.L1Cache_Controller.OT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack | 184 12.12% 12.12% | 199 13.11% 25.23% | 191 12.58% 37.81% | 193 12.71% 50.53% | 181 11.92% 62.45% | 173 11.40% 73.85% | 178 11.73% 85.57% | 219 14.43% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1518
+system.ruby.L1Cache_Controller.II.Writeback_Nack | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1
+system.ruby.L1Cache_Controller.IT.Load | 1 25.00% 25.00% | 0 0.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.IT.Load::total 4
+system.ruby.L1Cache_Controller.IT.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.IT.Store::total 2
+system.ruby.L1Cache_Controller.IT.L1_to_L2 | 7 35.00% 35.00% | 0 0.00% 35.00% | 1 5.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 12 60.00% 100.00%
+system.ruby.L1Cache_Controller.IT.L1_to_L2::total 20
+system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 1 12.50% 12.50% | 1 12.50% 25.00% | 2 25.00% 50.00% | 0 0.00% 50.00% | 2 25.00% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00%
+system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total 8
+system.ruby.L1Cache_Controller.ST.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 3 50.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.ST.Load::total 6
+system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 3 75.00% 100.00%
+system.ruby.L1Cache_Controller.ST.Store::total 4
+system.ruby.L1Cache_Controller.ST.L1_to_L2 | 11 10.89% 10.89% | 14 13.86% 24.75% | 8 7.92% 32.67% | 12 11.88% 44.55% | 0 0.00% 44.55% | 0 0.00% 44.55% | 9 8.91% 53.47% | 47 46.53% 100.00%
+system.ruby.L1Cache_Controller.ST.L1_to_L2::total 101
+system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 1 5.56% 5.56% | 2 11.11% 16.67% | 1 5.56% 22.22% | 5 27.78% 50.00% | 0 0.00% 50.00% | 1 5.56% 55.56% | 3 16.67% 72.22% | 5 27.78% 100.00%
+system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 18
+system.ruby.L1Cache_Controller.OT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00%
system.ruby.L1Cache_Controller.OT.Load::total 3
-system.ruby.L1Cache_Controller.OT.L1_to_L2 | 10 27.03% 27.03% | 0 0.00% 27.03% | 1 2.70% 29.73% | 0 0.00% 29.73% | 20 54.05% 83.78% | 0 0.00% 83.78% | 0 0.00% 83.78% | 6 16.22% 100.00%
-system.ruby.L1Cache_Controller.OT.L1_to_L2::total 37
-system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 1 11.11% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00%
-system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 9
-system.ruby.L1Cache_Controller.MT.Load | 8 7.48% 7.48% | 12 11.21% 18.69% | 12 11.21% 29.91% | 21 19.63% 49.53% | 13 12.15% 61.68% | 9 8.41% 70.09% | 14 13.08% 83.18% | 18 16.82% 100.00%
-system.ruby.L1Cache_Controller.MT.Load::total 107
-system.ruby.L1Cache_Controller.MT.Store | 6 13.04% 13.04% | 4 8.70% 21.74% | 5 10.87% 32.61% | 9 19.57% 52.17% | 8 17.39% 69.57% | 6 13.04% 82.61% | 7 15.22% 97.83% | 1 2.17% 100.00%
-system.ruby.L1Cache_Controller.MT.Store::total 46
-system.ruby.L1Cache_Controller.MT.L1_to_L2 | 162 14.36% 14.36% | 102 9.04% 23.40% | 101 8.95% 32.36% | 198 17.55% 49.91% | 105 9.31% 59.22% | 124 10.99% 70.21% | 181 16.05% 86.26% | 155 13.74% 100.00%
-system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1128
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 39 12.30% 12.30% | 35 11.04% 23.34% | 34 10.73% 34.07% | 45 14.20% 48.26% | 36 11.36% 59.62% | 34 10.73% 70.35% | 43 13.56% 83.91% | 51 16.09% 100.00%
-system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 317
-system.ruby.L1Cache_Controller.MMT.Load | 12 18.75% 18.75% | 5 7.81% 26.56% | 7 10.94% 37.50% | 5 7.81% 45.31% | 10 15.62% 60.94% | 7 10.94% 71.88% | 10 15.62% 87.50% | 8 12.50% 100.00%
-system.ruby.L1Cache_Controller.MMT.Load::total 64
-system.ruby.L1Cache_Controller.MMT.Store | 5 13.51% 13.51% | 8 21.62% 35.14% | 3 8.11% 43.24% | 2 5.41% 48.65% | 3 8.11% 56.76% | 8 21.62% 78.38% | 6 16.22% 94.59% | 2 5.41% 100.00%
-system.ruby.L1Cache_Controller.MMT.Store::total 37
-system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 86 13.21% 13.21% | 96 14.75% 27.96% | 55 8.45% 36.41% | 38 5.84% 42.24% | 69 10.60% 52.84% | 110 16.90% 69.74% | 148 22.73% 92.47% | 49 7.53% 100.00%
-system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 651
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 24 12.06% 12.06% | 21 10.55% 22.61% | 24 12.06% 34.67% | 19 9.55% 44.22% | 28 14.07% 58.29% | 24 12.06% 70.35% | 37 18.59% 88.94% | 22 11.06% 100.00%
-system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 199
+system.ruby.L1Cache_Controller.OT.L1_to_L2 | 3 20.00% 20.00% | 0 0.00% 20.00% | 6 40.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 6 40.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.OT.L1_to_L2::total 15
+system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00%
+system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 5
+system.ruby.L1Cache_Controller.MT.Load | 15 16.85% 16.85% | 10 11.24% 28.09% | 12 13.48% 41.57% | 11 12.36% 53.93% | 11 12.36% 66.29% | 9 10.11% 76.40% | 13 14.61% 91.01% | 8 8.99% 100.00%
+system.ruby.L1Cache_Controller.MT.Load::total 89
+system.ruby.L1Cache_Controller.MT.Store | 7 15.91% 15.91% | 5 11.36% 27.27% | 1 2.27% 29.55% | 8 18.18% 47.73% | 9 20.45% 68.18% | 4 9.09% 77.27% | 5 11.36% 88.64% | 5 11.36% 100.00%
+system.ruby.L1Cache_Controller.MT.Store::total 44
+system.ruby.L1Cache_Controller.MT.L1_to_L2 | 153 13.17% 13.17% | 95 8.18% 21.34% | 101 8.69% 30.03% | 171 14.72% 44.75% | 156 13.43% 58.18% | 158 13.60% 71.77% | 214 18.42% 90.19% | 114 9.81% 100.00%
+system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1162
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 43 13.87% 13.87% | 35 11.29% 25.16% | 31 10.00% 35.16% | 44 14.19% 49.35% | 35 11.29% 60.65% | 43 13.87% 74.52% | 42 13.55% 88.06% | 37 11.94% 100.00%
+system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 310
+system.ruby.L1Cache_Controller.MMT.Load | 10 13.89% 13.89% | 8 11.11% 25.00% | 10 13.89% 38.89% | 8 11.11% 50.00% | 9 12.50% 62.50% | 6 8.33% 70.83% | 13 18.06% 88.89% | 8 11.11% 100.00%
+system.ruby.L1Cache_Controller.MMT.Load::total 72
+system.ruby.L1Cache_Controller.MMT.Store | 5 14.71% 14.71% | 6 17.65% 32.35% | 4 11.76% 44.12% | 3 8.82% 52.94% | 3 8.82% 61.76% | 6 17.65% 79.41% | 3 8.82% 88.24% | 4 11.76% 100.00%
+system.ruby.L1Cache_Controller.MMT.Store::total 34
+system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 91 12.59% 12.59% | 71 9.82% 22.41% | 96 13.28% 35.68% | 73 10.10% 45.78% | 114 15.77% 61.55% | 32 4.43% 65.98% | 176 24.34% 90.32% | 70 9.68% 100.00%
+system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 723
+system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 27 13.17% 13.17% | 25 12.20% 25.37% | 24 11.71% 37.07% | 25 12.20% 49.27% | 26 12.68% 61.95% | 19 9.27% 71.22% | 33 16.10% 87.32% | 26 12.68% 100.00%
+system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 205
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.007583 # Number of seconds simulated
-sim_ticks 7582589 # Number of ticks simulated
-final_tick 7582589 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.007555 # Number of seconds simulated
+sim_ticks 7555268 # Number of ticks simulated
+final_tick 7555268 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 210657 # Simulator tick rate (ticks/s)
-host_mem_usage 700452 # Number of bytes of host memory used
-host_seconds 36.00 # Real time elapsed on the host
+host_tick_rate 300368 # Simulator tick rate (ticks/s)
+host_mem_usage 516584 # Number of bytes of host memory used
+host_seconds 25.15 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39656192 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 39656192 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39654720 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 39654720 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 619628 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 619628 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 619605 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 619605 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 5229901291 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 5229901291 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 5229707162 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 5229707162 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 10459608453 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 10459608453 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 619636 # Number of read requests accepted
-system.mem_ctrls.writeReqs 619605 # Number of write requests accepted
-system.mem_ctrls.readBursts 619636 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 619605 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 38799872 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 856832 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 39161920 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 39656704 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 39654720 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 13388 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 7653 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39518912 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 39518912 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39517888 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 39517888 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 617483 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 617483 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 617467 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 617467 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 5230643307 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 5230643307 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 5230507773 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 5230507773 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 10461151080 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 10461151080 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 617498 # Number of read requests accepted
+system.mem_ctrls.writeReqs 617467 # Number of write requests accepted
+system.mem_ctrls.readBursts 617498 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 617467 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 38662976 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 856576 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 39021568 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 39519872 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 39517888 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 13384 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 7703 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 76050 # Per bank write bursts
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-system.mem_ctrls.perBankRdBursts::2 75889 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 76027 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 75490 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 75499 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 75763 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 75663 # Per bank write bursts
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+system.mem_ctrls.perBankRdBursts::6 76010 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 75636 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts
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-system.mem_ctrls.perBankWrBursts::1 76551 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 76672 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 76745 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 76164 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 76242 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 76436 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 76362 # Per bank write bursts
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system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
-system.mem_ctrls.numWrRetry 1316 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 7582575 # Total gap between requests
+system.mem_ctrls.numWrRetry 1313 # Number of times write queue was full causing retry
+system.mem_ctrls.totGap 7555254 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 619636 # Read request sizes (log2)
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system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
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-system.mem_ctrls.bytesPerActivate::samples 245657 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 317.354620 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 242.734089 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 224.484514 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 33363 13.58% 13.58% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 75184 30.61% 44.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 48043 19.56% 63.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 35710 14.54% 78.28% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 24482 9.97% 88.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 14306 5.82% 94.07% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 7560 3.08% 97.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 3712 1.51% 98.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 3297 1.34% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 245657 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 38245 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 15.851693 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 8.811529 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 11.405114 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-3 12517 32.73% 32.73% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::4-7 1776 4.64% 37.37% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::8-11 493 1.29% 38.66% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-15 184 0.48% 39.14% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-19 3224 8.43% 47.57% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-23 7216 18.87% 66.44% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::24-27 6295 16.46% 82.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::28-31 5266 13.77% 96.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::32-35 1235 3.23% 99.90% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-39 38 0.10% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::68-71 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.mem_ctrls.wrPerTurnAround::samples 38244 # Writes before turning the bus around for reads
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+system.mem_ctrls.rdPerTurnAround::80-83 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 38244 100.00% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 38244 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 111772725 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 123291437 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 3031240 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 184.37 # Average queueing delay per DRAM burst
+system.mem_ctrls.wrPerTurnAround::16 38107 100.00% 100.00% # Writes before turning the bus around for reads
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+system.mem_ctrls.totQLat 111252820 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 122730891 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 3020545 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 184.16 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 203.37 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 5116.97 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 5164.72 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 5229.97 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 5229.71 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 203.16 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 5117.35 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 5164.82 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 5230.77 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 5230.51 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 80.33 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 39.98 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 40.35 # Data bus utilization in percentage for writes
-system.mem_ctrls.avgRdQLen 18.20 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 53.15 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 370717 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 601771 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 61.15 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 98.34 # Row buffer hit rate for writes
+system.mem_ctrls.avgRdQLen 18.19 # Average read queue length when enqueuing
+system.mem_ctrls.avgWrQLen 53.14 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 369680 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 599969 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 61.19 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 98.39 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 6.12 # Average gap between requests
-system.mem_ctrls.pageHitRate 79.83 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 1855594440 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 1030885800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 7559160960 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 6338580480 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 494828880 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 5163405192 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 16345200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 22458800952 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 2964.435559 # Core power per rank (mW)
+system.mem_ctrls.pageHitRate 79.88 # Row buffer hit rate, read and write combined
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+system.mem_ctrls_0.averagePower 2963.601171 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 12 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 252980 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 252200 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 494828880 # Energy for refresh commands per rank (pJ)
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-system.mem_ctrls_1.totalEnergy 5060549352 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 667.969023 # Core power per rank (mW)
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system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 1 # Clock period in ticks
-system.cpu0.num_reads 99415 # number of read accesses completed
-system.cpu0.num_writes 55396 # number of write accesses completed
-system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 99989 # number of read accesses completed
-system.cpu1.num_writes 55766 # number of write accesses completed
-system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 100000 # number of read accesses completed
-system.cpu2.num_writes 55829 # number of write accesses completed
-system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 99767 # number of read accesses completed
-system.cpu3.num_writes 55101 # number of write accesses completed
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 99087 # number of read accesses completed
-system.cpu4.num_writes 55181 # number of write accesses completed
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 99334 # number of read accesses completed
-system.cpu5.num_writes 55288 # number of write accesses completed
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 98895 # number of read accesses completed
-system.cpu6.num_writes 55228 # number of write accesses completed
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 99279 # number of read accesses completed
-system.cpu7.num_writes 55473 # number of write accesses completed
-system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 98710 # number of read accesses completed
+system.cpu0.num_writes 55193 # number of write accesses completed
+system.cpu1.num_reads 99197 # number of read accesses completed
+system.cpu1.num_writes 54876 # number of write accesses completed
+system.cpu2.num_reads 99807 # number of read accesses completed
+system.cpu2.num_writes 55097 # number of write accesses completed
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+system.cpu3.num_writes 55678 # number of write accesses completed
+system.cpu4.num_reads 99475 # number of read accesses completed
+system.cpu4.num_writes 55578 # number of write accesses completed
+system.cpu5.num_reads 100000 # number of read accesses completed
+system.cpu5.num_writes 55526 # number of write accesses completed
+system.cpu6.num_reads 99558 # number of read accesses completed
+system.cpu6.num_writes 55241 # number of write accesses completed
+system.cpu7.num_reads 99313 # number of read accesses completed
+system.cpu7.num_writes 55346 # number of write accesses completed
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 32 # delay histogram for all message
system.ruby.delayHist::max_bucket 319 # delay histogram for all message
-system.ruby.delayHist::samples 1259803 # delay histogram for all message
-system.ruby.delayHist::mean 2.138829 # delay histogram for all message
-system.ruby.delayHist::stdev 7.497358 # delay histogram for all message
-system.ruby.delayHist | 1243420 98.70% 98.70% | 10426 0.83% 99.53% | 5324 0.42% 99.95% | 510 0.04% 99.99% | 106 0.01% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 1259803 # delay histogram for all message
+system.ruby.delayHist::samples 1255488 # delay histogram for all message
+system.ruby.delayHist::mean 2.169527 # delay histogram for all message
+system.ruby.delayHist::stdev 7.600459 # delay histogram for all message
+system.ruby.delayHist | 1238674 98.66% 98.66% | 10648 0.85% 99.51% | 5547 0.44% 99.95% | 516 0.04% 99.99% | 82 0.01% 100.00% | 21 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 1255488 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 2
system.ruby.outstanding_req_hist::max_bucket 19
-system.ruby.outstanding_req_hist::samples 628107
-system.ruby.outstanding_req_hist::mean 15.998448
-system.ruby.outstanding_req_hist::gmean 15.997186
-system.ruby.outstanding_req_hist::stdev 0.125758
-system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 627972 99.98% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist::total 628107
+system.ruby.outstanding_req_hist::samples 625936
+system.ruby.outstanding_req_hist::mean 15.998449
+system.ruby.outstanding_req_hist::gmean 15.997183
+system.ruby.outstanding_req_hist::stdev 0.125950
+system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 27 0.00% 0.02% | 625805 99.98% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist::total 625936
system.ruby.latency_hist::bucket_size 512
system.ruby.latency_hist::max_bucket 5119
-system.ruby.latency_hist::samples 627979
-system.ruby.latency_hist::mean 1545.382761
-system.ruby.latency_hist::gmean 1522.867536
-system.ruby.latency_hist::stdev 263.957857
-system.ruby.latency_hist | 68 0.01% 0.01% | 7984 1.27% 1.28% | 316387 50.38% 51.66% | 279515 44.51% 96.17% | 23839 3.80% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist::total 627979
+system.ruby.latency_hist::samples 625808
+system.ruby.latency_hist::mean 1545.142387
+system.ruby.latency_hist::gmean 1522.552701
+system.ruby.latency_hist::stdev 264.347793
+system.ruby.latency_hist | 80 0.01% 0.01% | 8131 1.30% 1.31% | 315699 50.45% 51.76% | 277984 44.42% 96.18% | 23716 3.79% 99.97% | 198 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist::total 625808
system.ruby.miss_latency_hist::bucket_size 512
system.ruby.miss_latency_hist::max_bucket 5119
-system.ruby.miss_latency_hist::samples 627979
-system.ruby.miss_latency_hist::mean 1545.382761
-system.ruby.miss_latency_hist::gmean 1522.867536
-system.ruby.miss_latency_hist::stdev 263.957857
-system.ruby.miss_latency_hist | 68 0.01% 0.01% | 7984 1.27% 1.28% | 316387 50.38% 51.66% | 279515 44.51% 96.17% | 23839 3.80% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist::total 627979
-system.ruby.L1Cache.incomplete_times 8356
-system.ruby.Directory.incomplete_times 619619
+system.ruby.miss_latency_hist::samples 625808
+system.ruby.miss_latency_hist::mean 1545.142387
+system.ruby.miss_latency_hist::gmean 1522.552701
+system.ruby.miss_latency_hist::stdev 264.347793
+system.ruby.miss_latency_hist | 80 0.01% 0.01% | 8131 1.30% 1.31% | 315699 50.45% 51.76% | 277984 44.42% 96.18% | 23716 3.79% 99.97% | 198 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.L1Cache.incomplete_times 8330
+system.ruby.Directory.incomplete_times 617475
system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 78629 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78629 # Number of cache demand accesses
+system.ruby.l1_cntrl0.cacheMemory.demand_misses 78125 # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78125 # Number of cache demand accesses
system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.cacheMemory.demand_misses 78616 # Number of cache demand misses
-system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78616 # Number of cache demand accesses
+system.ruby.l1_cntrl1.cacheMemory.demand_misses 78092 # Number of cache demand misses
+system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78092 # Number of cache demand accesses
system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl2.cacheMemory.demand_misses 78776 # Number of cache demand misses
-system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78776 # Number of cache demand accesses
+system.ruby.l1_cntrl2.cacheMemory.demand_misses 78168 # Number of cache demand misses
+system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78168 # Number of cache demand accesses
system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.cacheMemory.demand_misses 78236 # Number of cache demand misses
-system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78236 # Number of cache demand accesses
+system.ruby.l1_cntrl3.cacheMemory.demand_misses 78501 # Number of cache demand misses
+system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78501 # Number of cache demand accesses
system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl4.cacheMemory.demand_misses 78211 # Number of cache demand misses
-system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78211 # Number of cache demand accesses
+system.ruby.l1_cntrl4.cacheMemory.demand_misses 78224 # Number of cache demand misses
+system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78224 # Number of cache demand accesses
system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl5.cacheMemory.demand_misses 78653 # Number of cache demand misses
-system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78653 # Number of cache demand accesses
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+system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78367 # Number of cache demand accesses
system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.cacheMemory.demand_misses 78454 # Number of cache demand misses
-system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78454 # Number of cache demand accesses
+system.ruby.l1_cntrl6.cacheMemory.demand_misses 78095 # Number of cache demand misses
+system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78095 # Number of cache demand accesses
system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl7.cacheMemory.demand_misses 78418 # Number of cache demand misses
-system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78418 # Number of cache demand accesses
+system.ruby.l1_cntrl7.cacheMemory.demand_misses 78258 # Number of cache demand misses
+system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78258 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
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+system.ruby.network.routers7.percent_links_utilized 5.195587
+system.ruby.network.routers7.msg_count.Control::2 78258
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+system.ruby.network.routers9.percent_links_utilized 9.176790
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+system.ruby.network.msg_count.Control 1877487
+system.ruby.network.msg_count.Data 1864059
+system.ruby.network.msg_count.Response_Data 1877425
+system.ruby.network.msg_count.Writeback_Control 1889042
+system.ruby.network.msg_byte.Control 15019896
+system.ruby.network.msg_byte.Data 134212248
+system.ruby.network.msg_byte.Response_Data 135174600
+system.ruby.network.msg_byte.Writeback_Control 15112336
+system.ruby.network.routers0.throttle0.link_utilization 5.173099
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78122
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78585
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5624784
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 628680
+system.ruby.network.routers0.throttle1.link_utilization 5.197632
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+system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1015
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+system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5585040
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 73080
+system.ruby.network.routers1.throttle0.link_utilization 5.171087
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78091
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+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5622552
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+system.ruby.network.routers1.throttle1.link_utilization 5.195924
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+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1043
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+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 75096
+system.ruby.network.routers2.throttle0.link_utilization 5.175965
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+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5627808
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 629120
+system.ruby.network.routers2.throttle1.link_utilization 5.201192
+system.ruby.network.routers2.throttle1.msg_count.Control::2 78168
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+system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78497
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+system.ruby.network.routers4.throttle1.link_utilization 5.205077
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+system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1050
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+system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 75600
+system.ruby.network.routers5.throttle0.link_utilization 5.189472
+system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78365
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+system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5642280
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+system.ruby.network.routers5.throttle1.link_utilization 5.216499
+system.ruby.network.routers5.throttle1.msg_count.Control::2 78366
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+system.ruby.network.routers6.throttle0.link_utilization 5.171200
+system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78092
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+system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 74736
+system.ruby.network.routers8.throttle0.link_utilization 41.150135
+system.ruby.network.routers8.throttle0.msg_count.Control::2 625829
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+system.ruby.network.routers8.throttle1.link_utilization 40.944855
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+system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 629681
+system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44458488
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+system.ruby.network.routers9.throttle0.link_utilization 5.173099
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+system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5624784
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+system.ruby.network.routers9.throttle1.link_utilization 5.171087
+system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78091
+system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 78560
+system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5622552
+system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 628480
+system.ruby.network.routers9.throttle2.link_utilization 5.175965
+system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78164
+system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 78640
+system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5627808
+system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 629120
+system.ruby.network.routers9.throttle3.link_utilization 5.198148
+system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78497
+system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 78995
+system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5651784
+system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 631960
+system.ruby.network.routers9.throttle4.link_utilization 5.179743
+system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78221
+system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 78698
+system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5631912
+system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 629584
+system.ruby.network.routers9.throttle5.link_utilization 5.189492
+system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78365
+system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 78875
+system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5642280
+system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 631000
+system.ruby.network.routers9.throttle6.link_utilization 5.171200
+system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78092
+system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78568
+system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5622624
+system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 628544
+system.ruby.network.routers9.throttle7.link_utilization 5.182238
+system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78256
+system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 78760
+system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5634432
+system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 630080
+system.ruby.network.routers9.throttle8.link_utilization 41.150135
+system.ruby.network.routers9.throttle8.msg_count.Control::2 625829
+system.ruby.network.routers9.throttle8.msg_count.Data::2 621353
+system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5006632
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system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 627979 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.257658 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 1.293410 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 603579 96.11% 96.11% | 17844 2.84% 98.96% | 5625 0.90% 99.85% | 739 0.12% 99.97% | 162 0.03% 100.00% | 24 0.00% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 627979 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 625808 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean 0.264720 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 1.304410 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 600768 96.00% 96.00% | 18387 2.94% 98.94% | 5734 0.92% 99.85% | 745 0.12% 99.97% | 149 0.02% 100.00% | 19 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 625808 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 32 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 319 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 631824 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 4.008551 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 10.168722 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 615441 97.41% 97.41% | 10426 1.65% 99.06% | 5324 0.84% 99.90% | 510 0.08% 99.98% | 106 0.02% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 631824 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 629680 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean 4.062621 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev 10.310093 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 612866 97.33% 97.33% | 10648 1.69% 99.02% | 5547 0.88% 99.90% | 516 0.08% 99.98% | 82 0.01% 100.00% | 21 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 629680 # delay histogram for vnet_2
system.ruby.LD.latency_hist::bucket_size 512
system.ruby.LD.latency_hist::max_bucket 5119
-system.ruby.LD.latency_hist::samples 404144
-system.ruby.LD.latency_hist::mean 1545.571497
-system.ruby.LD.latency_hist::gmean 1523.054184
-system.ruby.LD.latency_hist::stdev 263.999078
-system.ruby.LD.latency_hist | 46 0.01% 0.01% | 5096 1.26% 1.27% | 203787 50.42% 51.70% | 179678 44.46% 96.16% | 15429 3.82% 99.97% | 108 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist::total 404144
+system.ruby.LD.latency_hist::samples 403166
+system.ruby.LD.latency_hist::mean 1544.913271
+system.ruby.LD.latency_hist::gmean 1522.275613
+system.ruby.LD.latency_hist::stdev 264.561950
+system.ruby.LD.latency_hist | 54 0.01% 0.01% | 5301 1.31% 1.33% | 203466 50.47% 51.80% | 178892 44.37% 96.17% | 15319 3.80% 99.97% | 134 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.miss_latency_hist::bucket_size 512
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system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512
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-system.ruby.L1Cache_Controller.I.Store | 27949 12.49% 12.49% | 28009 12.51% 25.00% | 28276 12.63% 37.63% | 27727 12.39% 50.02% | 27985 12.50% 62.52% | 27887 12.46% 74.98% | 27966 12.49% 87.47% | 28043 12.53% 100.00%
-system.ruby.L1Cache_Controller.I.Store::total 223842
-system.ruby.L1Cache_Controller.I.Replacement | 576 12.83% 12.83% | 532 11.85% 24.67% | 604 13.45% 38.12% | 608 13.54% 51.66% | 578 12.87% 64.53% | 529 11.78% 76.31% | 540 12.02% 88.33% | 524 11.67% 100.00%
-system.ruby.L1Cache_Controller.I.Replacement::total 4491
-system.ruby.L1Cache_Controller.II.Writeback_Nack | 487 12.60% 12.60% | 482 12.47% 25.07% | 475 12.29% 37.36% | 483 12.50% 49.86% | 454 11.75% 61.60% | 472 12.21% 73.82% | 483 12.50% 86.31% | 529 13.69% 100.00%
-system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3865
-system.ruby.L1Cache_Controller.M.Fwd_GETX | 576 12.83% 12.83% | 532 11.85% 24.67% | 604 13.45% 38.12% | 608 13.54% 51.66% | 578 12.87% 64.53% | 529 11.78% 76.31% | 540 12.02% 88.33% | 524 11.67% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4491
-system.ruby.L1Cache_Controller.M.Replacement | 78049 12.52% 12.52% | 78080 12.52% 25.04% | 78168 12.54% 37.58% | 77624 12.45% 50.03% | 77629 12.45% 62.48% | 78120 12.53% 75.01% | 77910 12.50% 87.51% | 77890 12.49% 100.00%
-system.ruby.L1Cache_Controller.M.Replacement::total 623470
-system.ruby.L1Cache_Controller.MI.Fwd_GETX | 487 12.60% 12.60% | 482 12.47% 25.07% | 475 12.29% 37.36% | 483 12.50% 49.86% | 454 11.75% 61.60% | 472 12.21% 73.82% | 483 12.50% 86.31% | 529 13.69% 100.00%
-system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3865
-system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77562 12.52% 12.52% | 77596 12.52% 25.04% | 77693 12.54% 37.58% | 77141 12.45% 50.03% | 77175 12.46% 62.49% | 77648 12.53% 75.02% | 77427 12.50% 87.51% | 77361 12.49% 100.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 619603
-system.ruby.L1Cache_Controller.IS.Data | 50680 12.54% 12.54% | 50605 12.52% 25.06% | 50498 12.50% 37.56% | 50509 12.50% 50.05% | 50225 12.43% 62.48% | 50765 12.56% 75.04% | 50488 12.49% 87.54% | 50374 12.46% 100.00%
-system.ruby.L1Cache_Controller.IS.Data::total 404144
-system.ruby.L1Cache_Controller.IM.Data | 27948 12.49% 12.49% | 28008 12.51% 25.00% | 28276 12.63% 37.63% | 27725 12.39% 50.02% | 27984 12.50% 62.52% | 27887 12.46% 74.98% | 27965 12.49% 87.47% | 28042 12.53% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 223835
+system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 219637
+system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1547.153103
+system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1524.733978
+system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 263.641675
+system.ruby.ST.Directory.miss_type_mach_latency_hist | 26 0.01% 0.01% | 2692 1.23% 1.24% | 110368 50.25% 51.49% | 98134 44.68% 96.17% | 8353 3.80% 99.97% | 64 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist::total 219637
+system.ruby.Directory_Controller.GETX 689360 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 617467 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX_NotOwner 3886 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 617479 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 617466 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 617498 0.00% 0.00%
+system.ruby.Directory_Controller.M.GETX 8330 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 617467 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX_NotOwner 3886 0.00% 0.00%
+system.ruby.Directory_Controller.IM.GETX 63241 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 617479 0.00% 0.00%
+system.ruby.Directory_Controller.MI.GETX 291 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 617466 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load | 50298 12.48% 12.48% | 50313 12.48% 24.95% | 50604 12.55% 37.51% | 50559 12.54% 50.05% | 50335 12.48% 62.53% | 50365 12.49% 75.02% | 50340 12.49% 87.51% | 50369 12.49% 100.00%
+system.ruby.L1Cache_Controller.Load::total 403183
+system.ruby.L1Cache_Controller.Store | 27827 12.50% 12.50% | 27779 12.48% 24.97% | 27564 12.38% 37.36% | 27942 12.55% 49.91% | 27889 12.53% 62.43% | 28002 12.58% 75.01% | 27755 12.47% 87.47% | 27889 12.53% 100.00%
+system.ruby.L1Cache_Controller.Store::total 222647
+system.ruby.L1Cache_Controller.Data | 78122 12.48% 12.48% | 78091 12.48% 24.96% | 78164 12.49% 37.45% | 78497 12.54% 50.00% | 78221 12.50% 62.49% | 78365 12.52% 75.02% | 78092 12.48% 87.50% | 78256 12.50% 100.00%
+system.ruby.L1Cache_Controller.Data::total 625808
+system.ruby.L1Cache_Controller.Fwd_GETX | 1015 12.18% 12.18% | 1043 12.52% 24.71% | 1020 12.24% 36.95% | 1077 12.93% 49.88% | 1050 12.61% 62.48% | 1062 12.75% 75.23% | 1025 12.30% 87.54% | 1038 12.46% 100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total 8330
+system.ruby.L1Cache_Controller.Replacement | 78121 12.48% 12.48% | 78088 12.48% 24.96% | 78164 12.49% 37.45% | 78497 12.54% 50.00% | 78220 12.50% 62.49% | 78363 12.52% 75.02% | 78091 12.48% 87.50% | 78254 12.50% 100.00%
+system.ruby.L1Cache_Controller.Replacement::total 625798
+system.ruby.L1Cache_Controller.Writeback_Ack | 77106 12.49% 12.49% | 77045 12.48% 24.97% | 77144 12.49% 37.46% | 77418 12.54% 50.00% | 77169 12.50% 62.49% | 77300 12.52% 75.01% | 77066 12.48% 87.49% | 77216 12.51% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total 617464
+system.ruby.L1Cache_Controller.Writeback_Nack | 464 11.94% 11.94% | 472 12.15% 24.09% | 476 12.25% 36.34% | 499 12.84% 49.18% | 479 12.33% 61.50% | 513 13.20% 74.70% | 477 12.27% 86.98% | 506 13.02% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Nack::total 3886
+system.ruby.L1Cache_Controller.I.Load | 50298 12.48% 12.48% | 50313 12.48% 24.95% | 50604 12.55% 37.51% | 50559 12.54% 50.05% | 50335 12.48% 62.53% | 50365 12.49% 75.02% | 50340 12.49% 87.51% | 50369 12.49% 100.00%
+system.ruby.L1Cache_Controller.I.Load::total 403183
+system.ruby.L1Cache_Controller.I.Store | 27827 12.50% 12.50% | 27779 12.48% 24.97% | 27564 12.38% 37.36% | 27942 12.55% 49.91% | 27889 12.53% 62.43% | 28002 12.58% 75.01% | 27755 12.47% 87.47% | 27889 12.53% 100.00%
+system.ruby.L1Cache_Controller.I.Store::total 222647
+system.ruby.L1Cache_Controller.I.Replacement | 551 12.40% 12.40% | 571 12.85% 25.25% | 544 12.24% 37.49% | 578 13.01% 50.50% | 571 12.85% 63.34% | 549 12.35% 75.70% | 548 12.33% 88.03% | 532 11.97% 100.00%
+system.ruby.L1Cache_Controller.I.Replacement::total 4444
+system.ruby.L1Cache_Controller.II.Writeback_Nack | 464 11.94% 11.94% | 472 12.15% 24.09% | 476 12.25% 36.34% | 499 12.84% 49.18% | 479 12.33% 61.50% | 513 13.20% 74.70% | 477 12.27% 86.98% | 506 13.02% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3886
+system.ruby.L1Cache_Controller.M.Fwd_GETX | 551 12.40% 12.40% | 571 12.85% 25.25% | 544 12.24% 37.49% | 578 13.01% 50.50% | 571 12.85% 63.34% | 549 12.35% 75.70% | 548 12.33% 88.03% | 532 11.97% 100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4444
+system.ruby.L1Cache_Controller.M.Replacement | 77570 12.48% 12.48% | 77517 12.48% 24.96% | 77620 12.49% 37.45% | 77919 12.54% 49.99% | 77649 12.50% 62.49% | 77814 12.52% 75.01% | 77543 12.48% 87.49% | 77722 12.51% 100.00%
+system.ruby.L1Cache_Controller.M.Replacement::total 621354
+system.ruby.L1Cache_Controller.MI.Fwd_GETX | 464 11.94% 11.94% | 472 12.15% 24.09% | 476 12.25% 36.34% | 499 12.84% 49.18% | 479 12.33% 61.50% | 513 13.20% 74.70% | 477 12.27% 86.98% | 506 13.02% 100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3886
+system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77106 12.49% 12.49% | 77045 12.48% 24.97% | 77144 12.49% 37.46% | 77418 12.54% 50.00% | 77169 12.50% 62.49% | 77300 12.52% 75.01% | 77066 12.48% 87.49% | 77216 12.51% 100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 617464
+system.ruby.L1Cache_Controller.IS.Data | 50296 12.48% 12.48% | 50312 12.48% 24.95% | 50601 12.55% 37.51% | 50556 12.54% 50.05% | 50332 12.48% 62.53% | 50363 12.49% 75.02% | 50339 12.49% 87.51% | 50367 12.49% 100.00%
+system.ruby.L1Cache_Controller.IS.Data::total 403166
+system.ruby.L1Cache_Controller.IM.Data | 27826 12.50% 12.50% | 27779 12.48% 24.98% | 27563 12.38% 37.36% | 27941 12.55% 49.90% | 27889 12.53% 62.43% | 28002 12.58% 75.01% | 27753 12.47% 87.47% | 27889 12.53% 100.00%
+system.ruby.L1Cache_Controller.IM.Data::total 222642
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.001487 # Number of seconds simulated
-sim_ticks 1486654500 # Number of ticks simulated
-final_tick 1486654500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.001493 # Number of seconds simulated
+sim_ticks 1493307500 # Number of ticks simulated
+final_tick 1493307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 296727534 # Simulator tick rate (ticks/s)
-host_mem_usage 404724 # Number of bytes of host memory used
-host_seconds 5.01 # Real time elapsed on the host
+host_tick_rate 295462472 # Simulator tick rate (ticks/s)
+host_mem_usage 222068 # Number of bytes of host memory used
+host_seconds 5.05 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 76776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 78761 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 77348 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 78011 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 77583 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 76150 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 79121 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 75007 # Number of bytes read from this memory
-system.physmem.bytes_read::total 618757 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 383744 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5329 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5414 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5336 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5424 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5535 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5438 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5327 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5496 # Number of bytes written to this memory
-system.physmem.bytes_written::total 427043 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11067 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10847 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10757 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10790 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11118 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10756 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10829 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10873 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87037 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 5996 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5329 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5414 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5336 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5424 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5535 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5438 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5327 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5496 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49295 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 51643472 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 52978685 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 52028228 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 52474196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 52186302 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 51222392 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 53220839 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 50453552 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 416207666 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 258125879 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 3584558 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 3641734 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 3589267 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 3648460 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 3723125 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 3657877 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 3583213 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 3696891 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 287251006 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 258125879 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 55228030 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 56620419 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 55617496 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 56122657 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 55909426 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 54880270 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 56804052 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 54150443 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 703458672 # Total bandwidth to/from this memory (bytes/s)
-system.membus.snoop_filter.tot_requests 122188 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 120140 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 84101 # Transaction distribution
-system.membus.trans_dist::ReadResp 84098 # Transaction distribution
-system.membus.trans_dist::WriteReq 43299 # Transaction distribution
-system.membus.trans_dist::WriteResp 43298 # Transaction distribution
-system.membus.trans_dist::Writeback 5996 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58155 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 47311 # Transaction distribution
-system.membus.trans_dist::ReadExReq 50200 # Transaction distribution
-system.membus.trans_dist::ReadExResp 2936 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 419394 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 419394 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1045797 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1045797 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 58108 # Total snoops (count)
-system.membus.snoop_fanout::samples 122188 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 122188 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 122188 # Request fanout histogram
-system.membus.reqLayer0.occupancy 471309000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 31.7 # Layer utilization (%)
-system.membus.respLayer0.occupancy 318465500 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 21.4 # Layer utilization (%)
+system.physmem.bytes_read::cpu0 74794 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 78736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 78807 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 78188 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 77250 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 74477 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 79412 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 78325 # Number of bytes read from this memory
+system.physmem.bytes_read::total 619989 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 384000 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5518 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5402 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5400 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5514 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5530 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5340 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5402 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory
+system.physmem.bytes_written::total 427483 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 10849 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10948 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10767 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10841 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10974 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10721 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10994 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10915 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87009 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6000 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5518 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5402 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5400 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5514 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5530 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5340 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5402 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49483 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 50086134 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 52725912 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 52773458 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 52358941 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 51730806 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 49873854 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 53178599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 52450684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 415178388 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 257147306 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 3695153 # Write bandwidth from this memory (bytes/s)
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-system.l2c.tags.occ_blocks::cpu3 6.146479 # Average occupied blocks per requestor
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-system.l2c.UpgradeReq_hits::cpu7 353 # number of UpgradeReq hits
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-system.l2c.UpgradeReq_miss_rate::cpu3 0.851339 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.864326 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu6 0.848459 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu4 27821.965898 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 28229.274611 # average UpgradeReq miss latency
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.864326 # mshr miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.844464 # mshr miss rate for UpgradeReq accesses
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-system.l2c.demand_mshr_miss_rate::cpu4 0.287199 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5 0.284857 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6 0.291075 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7 0.285731 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.286225 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0 0.285250 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1 0.288967 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2 0.284374 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3 0.282382 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4 0.287199 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5 0.284857 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6 0.291075 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7 0.285731 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.286225 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46821.581871 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 46907.453408 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46061.030166 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46977.872059 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46974.905424 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46299.340267 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46847.021337 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46908.825301 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 46730.457039 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40763.307494 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40701.385189 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40664.456910 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40748.820136 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40689.317954 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40679.792746 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40662.966700 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40774.973985 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40710.246324 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41140.304700 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41280.249090 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41318.512880 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41193.634757 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41207.717467 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41281.085847 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41208.584867 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41098.819188 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41216.112269 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 41917.037378 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 42071.248094 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 41950.912108 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 41974.667593 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 42032.092843 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 41958.847281 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 41985.195533 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 41870.388000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 41970.441418 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 41917.037378 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 42071.248094 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 41950.912108 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 41974.667593 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 42032.092843 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 41958.847281 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 41985.195533 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 41870.388000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 41970.441418 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.toL2Bus.snoop_filter.tot_requests 556652 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 259205 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 295399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 369106 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 369100 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43299 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43298 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 74943 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29164 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29164 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 161428 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 161427 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120001 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 119693 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 119622 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120026 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120574 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119580 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 119572 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119681 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 958749 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1736824 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1745103 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1743099 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1764010 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1727854 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1727156 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741472 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1730998 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 13916516 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 322180 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 556652 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.686233 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.173674 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 52178 9.37% 9.37% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 250105 44.93% 54.30% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 140101 25.17% 79.47% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 69083 12.41% 91.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 29746 5.34% 97.23% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 11224 2.02% 99.24% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 3520 0.63% 99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 695 0.12% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 556652 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1484170768 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 158821901 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 158474081 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 158663989 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 158858134 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 159553082 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 158926155 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 158642094 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 158326604 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%)
-system.cpu0.num_reads 99884 # number of read accesses completed
-system.cpu0.num_writes 54722 # number of write accesses completed
-system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.l1c.tags.replacements 22159 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 396.508288 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13572 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22560 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.601596 # Average number of references to valid blocks.
+system.cpu0.num_reads 99767 # number of read accesses completed
+system.cpu0.num_writes 55259 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22696 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 395.365301 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13357 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 23083 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.578651 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 396.508288 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.774430 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.774430 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 336605 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 336605 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8851 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8851 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1088 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1088 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9939 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9939 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9939 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9939 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36351 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36351 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23761 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23761 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60112 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60112 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60112 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60112 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 2463515507 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 2463515507 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 1861288603 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 1861288603 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 4324804110 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 4324804110 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 4324804110 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 4324804110 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45202 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45202 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 24849 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 24849 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70051 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70051 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70051 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70051 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804190 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.804190 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956216 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.956216 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.858118 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.858118 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.858118 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.858118 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67770.226596 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 67770.226596 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78333.765540 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 78333.765540 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 71945.769730 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 71945.769730 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 71945.769730 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 71945.769730 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 2211784 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 395.365301 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.772198 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.772198 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 272 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 339665 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 339665 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8708 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8708 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1150 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1150 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9858 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 9858 # number of demand (read+write) hits
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+system.cpu0.l1c.overall_accesses::total 70615 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809411 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.809411 # miss rate for ReadReq accesses
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+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67649.809015 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 67649.809015 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 77943.817708 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 77943.817708 # average WriteReq miss latency
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+system.cpu0.l1c.demand_avg_miss_latency::total 71677.987771 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 71677.987771 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 71677.987771 # average overall miss latency
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system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 60234 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 60506 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.719859 # average number of cycles each access was blocked
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9764 # number of writebacks
-system.cpu0.l1c.writebacks::total 9764 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36351 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36351 # number of ReadReq MSHR misses
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-system.cpu0.l1c.WriteReq_mshr_misses::total 23761 # number of WriteReq MSHR misses
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-system.cpu0.l1c.overall_mshr_misses::total 60112 # number of overall MSHR misses
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-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2386706389 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1811452635 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1811452635 # number of WriteReq MSHR miss cycles
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-system.cpu0.l1c.demand_mshr_miss_latency::total 4198159024 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.l1c.overall_mshr_miss_latency::total 4198159024 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1102233368 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1102233368 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 3973496829 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 3973496829 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5075730197 # number of overall MSHR uncacheable cycles
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-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956216 # mshr miss rate for WriteReq accesses
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-system.cpu0.l1c.demand_mshr_miss_rate::total 0.858118 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858118 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.858118 # mshr miss rate for overall accesses
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-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65657.241589 # average ReadReq mshr miss latency
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-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 76236.380413 # average WriteReq mshr miss latency
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-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69838.951025 # average overall mshr miss latency
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-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69838.951025 # average overall mshr miss latency
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+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65538.022092 # average ReadReq mshr miss latency
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+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99113 # number of read accesses completed
-system.cpu1.num_writes 54702 # number of write accesses completed
-system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.l1c.tags.replacements 22065 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 395.289903 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13538 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22464 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.602653 # Average number of references to valid blocks.
+system.cpu1.num_reads 100000 # number of read accesses completed
+system.cpu1.num_writes 54988 # number of write accesses completed
+system.cpu1.l1c.tags.replacements 22397 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 395.796271 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13630 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22804 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.597702 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 395.289903 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.772051 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.772051 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 336364 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 336364 # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1 8820 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8820 # number of ReadReq hits
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-system.cpu1.l1c.overall_hits::total 9957 # number of overall hits
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-system.cpu1.l1c.overall_misses::total 60036 # number of overall misses
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-system.cpu1.l1c.overall_miss_latency::total 4336084564 # number of overall miss cycles
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-system.cpu1.l1c.WriteReq_accesses::total 25014 # number of WriteReq accesses(hits+misses)
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-system.cpu1.l1c.overall_accesses::total 69993 # number of overall (read+write) accesses
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-system.cpu1.l1c.ReadReq_miss_rate::total 0.803908 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954545 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.954545 # miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_miss_rate::total 0.857743 # miss rate for demand accesses
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-system.cpu1.l1c.overall_miss_rate::total 0.857743 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 68147.206615 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 68147.206615 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78399.703480 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 78399.703480 # average WriteReq miss latency
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-system.cpu1.l1c.demand_avg_miss_latency::total 72224.741222 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 72224.741222 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 72224.741222 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 2199257 # number of cycles access was blocked
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+system.cpu1.l1c.tags.occ_percent::cpu1 0.773040 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total 0.773040 # Average percentage of cache occupancy
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+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 269 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 338465 # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses 338465 # Number of data accesses
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+system.cpu1.l1c.ReadReq_hits::total 8882 # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1 1141 # number of WriteReq hits
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+system.cpu1.l1c.ReadReq_misses::total 36639 # number of ReadReq misses
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+system.cpu1.l1c.WriteReq_misses::total 23767 # number of WriteReq misses
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+system.cpu1.l1c.demand_misses::total 60406 # number of demand (read+write) misses
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+system.cpu1.l1c.overall_misses::total 60406 # number of overall misses
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+system.cpu1.l1c.ReadReq_miss_latency::total 2485954076 # number of ReadReq miss cycles
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+system.cpu1.l1c.WriteReq_miss_latency::total 1862028208 # number of WriteReq miss cycles
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+system.cpu1.l1c.demand_miss_latency::total 4347982284 # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1 4347982284 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total 4347982284 # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1 45521 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total 45521 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 24908 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1 70429 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total 70429 # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1 70429 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total 70429 # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804881 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total 0.804881 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954191 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total 0.954191 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.857686 # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total 0.857686 # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1 0.857686 # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total 0.857686 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67849.943394 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 67849.943394 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78345.109101 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 78345.109101 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 71979.311393 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 71979.311393 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 71979.311393 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 71979.311393 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 2202198 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 59892 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 60277 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.720380 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.534632 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9710 # number of writebacks
-system.cpu1.l1c.writebacks::total 9710 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36159 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36159 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23877 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23877 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60036 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60036 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60036 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60036 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2387770588 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2387770588 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1821987516 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1821987516 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4209758104 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 4209758104 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4209758104 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 4209758104 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1078285196 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1078285196 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4031598145 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 4031598145 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5109883341 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5109883341 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803908 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803908 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954545 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954545 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857743 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.857743 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857743 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.857743 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 66035.304848 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 66035.304848 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76307.221008 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76307.221008 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 70120.562729 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 70120.562729 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 70120.562729 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 70120.562729 # average overall mshr miss latency
+system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks
+system.cpu1.l1c.writebacks::total 9809 # number of writebacks
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+system.cpu1.l1c.ReadReq_mshr_misses::total 36639 # number of ReadReq MSHR misses
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+system.cpu1.l1c.demand_mshr_misses::total 60406 # number of demand (read+write) MSHR misses
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+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1084723149 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4036922188 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5121645337 # number of overall MSHR uncacheable cycles
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+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954191 # mshr miss rate for WriteReq accesses
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+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.857686 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65739.153361 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65739.153361 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76248.417975 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76248.417975 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 98176 # number of read accesses completed
-system.cpu2.num_writes 54646 # number of write accesses completed
-system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.l1c.tags.replacements 22558 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 395.943086 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13415 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22958 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.584328 # Average number of references to valid blocks.
+system.cpu2.num_reads 99645 # number of read accesses completed
+system.cpu2.num_writes 55347 # number of write accesses completed
+system.cpu2.l1c.tags.replacements 22638 # number of replacements
+system.cpu2.l1c.tags.tagsinuse 395.541236 # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs 13666 # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.593323 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 395.943086 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.773326 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.773326 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 336254 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 336254 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8574 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8574 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1152 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1152 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9726 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9726 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9726 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9726 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36359 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36359 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 23860 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 23860 # number of WriteReq misses
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-system.cpu2.l1c.demand_misses::total 60219 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 60219 # number of overall misses
-system.cpu2.l1c.overall_misses::total 60219 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 2471651596 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 2471651596 # number of ReadReq miss cycles
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-system.cpu2.l1c.demand_miss_latency::total 4345940706 # number of demand (read+write) miss cycles
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-system.cpu2.l1c.overall_miss_latency::total 4345940706 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 44933 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 44933 # number of ReadReq accesses(hits+misses)
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-system.cpu2.l1c.WriteReq_accesses::total 25012 # number of WriteReq accesses(hits+misses)
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-system.cpu2.l1c.demand_accesses::total 69945 # number of demand (read+write) accesses
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-system.cpu2.l1c.overall_accesses::total 69945 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.809183 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.809183 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953942 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.953942 # miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_miss_rate::total 0.860948 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.860948 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.860948 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67979.086223 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 67979.086223 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78553.608969 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 78553.608969 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 72168.928511 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 72168.928511 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 72168.928511 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 72168.928511 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 2198300 # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2 395.541236 # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2 0.772541 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total 0.772541 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0 271 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses 339287 # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses 339287 # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2 8844 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total 8844 # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2 1130 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total 1130 # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2 9974 # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total 9974 # number of demand (read+write) hits
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+system.cpu2.l1c.overall_hits::total 9974 # number of overall hits
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+system.cpu2.l1c.ReadReq_misses::total 36761 # number of ReadReq misses
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+system.cpu2.l1c.WriteReq_misses::total 23865 # number of WriteReq misses
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+system.cpu2.l1c.demand_misses::total 60626 # number of demand (read+write) misses
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+system.cpu2.l1c.overall_misses::total 60626 # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2 2497854261 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total 2497854261 # number of ReadReq miss cycles
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+system.cpu2.l1c.WriteReq_miss_latency::total 1869962350 # number of WriteReq miss cycles
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+system.cpu2.l1c.demand_miss_latency::total 4367816611 # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2 4367816611 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total 4367816611 # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2 45605 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total 45605 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2 24995 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total 24995 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2 70600 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total 70600 # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2 70600 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total 70600 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806074 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.806074 # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954791 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total 0.954791 # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2 0.858725 # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total 0.858725 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.858725 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.858725 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67948.485106 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 67948.485106 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78355.849571 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 78355.849571 # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 72045.271187 # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 72045.271187 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 72045.271187 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 72045.271187 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 2198319 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 59965 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 60200 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.659718 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.516927 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9891 # number of writebacks
-system.cpu2.l1c.writebacks::total 9891 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36359 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36359 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23860 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 23860 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60219 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60219 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60219 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60219 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2394908316 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2394908316 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1824229170 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1824229170 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4219137486 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 4219137486 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4219137486 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 4219137486 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1069659636 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1069659636 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3964277301 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3964277301 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 5033936937 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5033936937 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.809183 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.809183 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953942 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953942 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860948 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.860948 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860948 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.860948 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65868.376908 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65868.376908 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76455.539396 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76455.539396 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 70063.227320 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 70063.227320 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 70063.227320 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 70063.227320 # average overall mshr miss latency
+system.cpu2.l1c.writebacks::writebacks 9871 # number of writebacks
+system.cpu2.l1c.writebacks::total 9871 # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36761 # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total 36761 # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23865 # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total 23865 # number of WriteReq MSHR misses
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+system.cpu2.l1c.demand_mshr_misses::total 60626 # number of demand (read+write) MSHR misses
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+system.cpu2.l1c.overall_mshr_misses::total 60626 # number of overall MSHR misses
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+system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2420242117 # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1819999216 # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1819999216 # number of WriteReq MSHR miss cycles
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+system.cpu2.l1c.demand_mshr_miss_latency::total 4240241333 # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4240241333 # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total 4240241333 # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1065167222 # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1065167222 # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3984850744 # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3984850744 # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 5050017966 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5050017966 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806074 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806074 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954791 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954791 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total 0.858725 # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total 0.858725 # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65837.221974 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65837.221974 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76262.275969 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76262.275969 # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 98913 # number of read accesses completed
-system.cpu3.num_writes 55212 # number of write accesses completed
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.l1c.tags.replacements 22225 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 393.873430 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13306 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22621 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.588214 # Average number of references to valid blocks.
+system.cpu3.num_reads 98252 # number of read accesses completed
+system.cpu3.num_writes 55235 # number of write accesses completed
+system.cpu3.l1c.tags.replacements 22381 # number of replacements
+system.cpu3.l1c.tags.tagsinuse 396.107709 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13213 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22778 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.580077 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 393.873430 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.769284 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.769284 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 336364 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 336364 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8580 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8580 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1197 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1197 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9777 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9777 # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3 9777 # number of overall hits
-system.cpu3.l1c.overall_hits::total 9777 # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3 36212 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total 36212 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 23956 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 23956 # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3 60168 # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total 60168 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60168 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60168 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 2456007015 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 2456007015 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 1878963119 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 1878963119 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 4334970134 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 4334970134 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 4334970134 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 4334970134 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 44792 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 44792 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3 25153 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total 25153 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3 69945 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total 69945 # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3 69945 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total 69945 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808448 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.808448 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952411 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.952411 # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3 0.860219 # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total 0.860219 # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3 0.860219 # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total 0.860219 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67823.014885 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 67823.014885 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78433.925488 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 78433.925488 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 72047.768482 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 72047.768482 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 72047.768482 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 72047.768482 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 2191987 # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3 396.107709 # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3 0.773648 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total 0.773648 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses 335638 # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses 335638 # Number of data accesses
+system.cpu3.l1c.ReadReq_hits::cpu3 8470 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total 8470 # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3 1156 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total 1156 # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3 9626 # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total 9626 # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3 9626 # number of overall hits
+system.cpu3.l1c.overall_hits::total 9626 # number of overall hits
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+system.cpu3.l1c.ReadReq_misses::total 36183 # number of ReadReq misses
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+system.cpu3.l1c.WriteReq_misses::total 23969 # number of WriteReq misses
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+system.cpu3.l1c.demand_misses::total 60152 # number of demand (read+write) misses
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+system.cpu3.l1c.overall_misses::total 60152 # number of overall misses
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+system.cpu3.l1c.ReadReq_miss_latency::total 2454128819 # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3 1887224651 # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total 1887224651 # number of WriteReq miss cycles
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+system.cpu3.l1c.demand_miss_latency::total 4341353470 # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3 4341353470 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total 4341353470 # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3 44653 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total 44653 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3 25125 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total 25125 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3 69778 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total 69778 # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3 69778 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total 69778 # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810315 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total 0.810315 # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953990 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total 0.953990 # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3 0.862048 # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total 0.862048 # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3 0.862048 # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total 0.862048 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67825.465522 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 67825.465522 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78736.061204 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 78736.061204 # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 72173.052766 # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 72173.052766 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 72173.052766 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 72173.052766 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 2184377 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 59750 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 59819 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.685975 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.516441 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9841 # number of writebacks
-system.cpu3.l1c.writebacks::total 9841 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36212 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36212 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23956 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23956 # number of WriteReq MSHR misses
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-system.cpu3.l1c.demand_mshr_misses::total 60168 # number of demand (read+write) MSHR misses
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-system.cpu3.l1c.overall_mshr_misses::total 60168 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2379648497 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2379648497 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1828763107 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1828763107 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4208411604 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 4208411604 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4208411604 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 4208411604 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1072329681 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1072329681 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 3992913639 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 3992913639 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 5065243320 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 5065243320 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808448 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808448 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952411 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952411 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860219 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.860219 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860219 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.860219 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.362559 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.362559 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76338.416555 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76338.416555 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 69944.349222 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 69944.349222 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 69944.349222 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 69944.349222 # average overall mshr miss latency
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+system.cpu3.l1c.writebacks::total 9931 # number of writebacks
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+system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1837004571 # number of WriteReq MSHR miss cycles
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+system.cpu3.l1c.overall_mshr_miss_rate::total 0.862048 # mshr miss rate for overall accesses
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+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.050825 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76640.851558 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76640.851558 # average WriteReq mshr miss latency
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+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 100000 # number of read accesses completed
-system.cpu4.num_writes 54692 # number of write accesses completed
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.l1c.tags.replacements 22289 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 395.541537 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13462 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22679 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.593589 # Average number of references to valid blocks.
+system.cpu4.num_reads 99562 # number of read accesses completed
+system.cpu4.num_writes 54813 # number of write accesses completed
+system.cpu4.l1c.tags.replacements 22626 # number of replacements
+system.cpu4.l1c.tags.tagsinuse 395.713168 # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs 13359 # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs 23019 # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs 0.580347 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 395.541537 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.772542 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.772542 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 337633 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 337633 # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1176 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1176 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 9915 # number of demand (read+write) hits
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-system.cpu4.l1c.overall_hits::cpu4 9915 # number of overall hits
-system.cpu4.l1c.overall_hits::total 9915 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 36692 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 36692 # number of ReadReq misses
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-system.cpu4.l1c.WriteReq_misses::total 23629 # number of WriteReq misses
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-system.cpu4.l1c.demand_misses::total 60321 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 60321 # number of overall misses
-system.cpu4.l1c.overall_misses::total 60321 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 2465146363 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 2465146363 # number of ReadReq miss cycles
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-system.cpu4.l1c.WriteReq_miss_latency::total 1837411479 # number of WriteReq miss cycles
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-system.cpu4.l1c.demand_miss_latency::total 4302557842 # number of demand (read+write) miss cycles
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-system.cpu4.l1c.overall_miss_latency::total 4302557842 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 45431 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 45431 # number of ReadReq accesses(hits+misses)
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-system.cpu4.l1c.WriteReq_accesses::total 24805 # number of WriteReq accesses(hits+misses)
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-system.cpu4.l1c.overall_accesses::total 70236 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807642 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.807642 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952590 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.952590 # miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_miss_rate::total 0.858833 # miss rate for demand accesses
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-system.cpu4.l1c.overall_miss_rate::total 0.858833 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67184.845825 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 67184.845825 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 77760.864996 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 77760.864996 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 71327.694203 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 71327.694203 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 71327.694203 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 71327.694203 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 2196199 # number of cycles access was blocked
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+system.cpu4.l1c.tags.occ_percent::total 0.772877 # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses 337886 # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses 337886 # Number of data accesses
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+system.cpu4.l1c.ReadReq_hits::total 8660 # number of ReadReq hits
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+system.cpu4.l1c.overall_hits::total 9790 # number of overall hits
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+system.cpu4.l1c.overall_misses::total 60473 # number of overall misses
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+system.cpu4.l1c.ReadReq_miss_latency::total 2479360793 # number of ReadReq miss cycles
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+system.cpu4.l1c.overall_miss_latency::total 4330486769 # number of overall miss cycles
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+system.cpu4.l1c.WriteReq_accesses::total 24855 # number of WriteReq accesses(hits+misses)
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+system.cpu4.l1c.overall_accesses::total 70263 # number of overall (read+write) accesses
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+system.cpu4.l1c.ReadReq_miss_rate::total 0.809285 # miss rate for ReadReq accesses
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+system.cpu4.l1c.overall_miss_rate::total 0.860666 # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67469.271607 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 67469.271607 # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78024.277176 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 78024.277176 # average WriteReq miss latency
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+system.cpu4.l1c.demand_avg_miss_latency::total 71610.251997 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 71610.251997 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 71610.251997 # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs 2193235 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 60342 # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs 60223 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.395860 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.418561 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9615 # number of writebacks
-system.cpu4.l1c.writebacks::total 9615 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36692 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 36692 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23629 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 23629 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 60321 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 60321 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 60321 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2387693175 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2387693175 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1788001185 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1788001185 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4175694360 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 4175694360 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4175694360 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 4175694360 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1103066428 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1103066428 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 4057809634 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 4057809634 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5160876062 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5160876062 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807642 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807642 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952590 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952590 # mshr miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.858833 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858833 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.858833 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65073.944593 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65073.944593 # average ReadReq mshr miss latency
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-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75669.778027 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69224.554633 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69224.554633 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69224.554633 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69224.554633 # average overall mshr miss latency
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+system.cpu4.l1c.writebacks::total 9708 # number of writebacks
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+system.cpu4.l1c.ReadReq_mshr_misses::total 36748 # number of ReadReq MSHR misses
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+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 4121360584 # number of WriteReq MSHR uncacheable cycles
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+system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5213160091 # number of overall MSHR uncacheable cycles
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+system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total 0.860666 # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65355.525607 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65355.525607 # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 75932.759031 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75932.759031 # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency
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+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 98940 # number of read accesses completed
-system.cpu5.num_writes 55179 # number of write accesses completed
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.l1c.tags.replacements 22195 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 395.048373 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13447 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22597 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.595079 # Average number of references to valid blocks.
+system.cpu5.num_reads 98672 # number of read accesses completed
+system.cpu5.num_writes 54809 # number of write accesses completed
+system.cpu5.l1c.tags.replacements 22472 # number of replacements
+system.cpu5.l1c.tags.tagsinuse 396.252013 # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs 13351 # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs 22867 # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs 0.583854 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 395.048373 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.771579 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.771579 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 337000 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 337000 # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5 8717 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8717 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1138 # number of WriteReq hits
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-system.cpu5.l1c.demand_hits::cpu5 9855 # number of demand (read+write) hits
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-system.cpu5.l1c.overall_hits::total 9855 # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5 36402 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total 36402 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 23842 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 23842 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 60244 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 60244 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60244 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60244 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 2469941136 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 2469941136 # number of ReadReq miss cycles
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-system.cpu5.l1c.WriteReq_miss_latency::total 1867542812 # number of WriteReq miss cycles
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-system.cpu5.l1c.overall_miss_latency::total 4337483948 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 45119 # number of ReadReq accesses(hits+misses)
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-system.cpu5.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses)
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-system.cpu5.l1c.overall_accesses::total 70099 # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806800 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total 0.806800 # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954444 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total 0.954444 # miss rate for WriteReq accesses
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-system.cpu5.l1c.demand_miss_rate::total 0.859413 # miss rate for demand accesses
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-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 67851.797594 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 67851.797594 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78329.956044 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 78329.956044 # average WriteReq miss latency
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-system.cpu5.l1c.demand_avg_miss_latency::total 71998.604807 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 71998.604807 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 71998.604807 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 2193553 # number of cycles access was blocked
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+system.cpu5.l1c.tags.occ_percent::total 0.773930 # Average percentage of cache occupancy
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+system.cpu5.l1c.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses 336301 # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses 336301 # Number of data accesses
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+system.cpu5.l1c.ReadReq_hits::total 8563 # number of ReadReq hits
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+system.cpu5.l1c.overall_hits::total 9647 # number of overall hits
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+system.cpu5.l1c.ReadReq_misses::total 36411 # number of ReadReq misses
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+system.cpu5.l1c.overall_misses::total 60293 # number of overall misses
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+system.cpu5.l1c.overall_miss_latency::total 4367406139 # number of overall miss cycles
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+system.cpu5.l1c.WriteReq_accesses::cpu5 24966 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total 24966 # number of WriteReq accesses(hits+misses)
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+system.cpu5.l1c.demand_accesses::total 69940 # number of demand (read+write) accesses
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+system.cpu5.l1c.overall_accesses::total 69940 # number of overall (read+write) accesses
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+system.cpu5.l1c.ReadReq_miss_rate::total 0.809601 # miss rate for ReadReq accesses
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+system.cpu5.l1c.WriteReq_miss_rate::total 0.956581 # miss rate for WriteReq accesses
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+system.cpu5.l1c.demand_miss_rate::total 0.862067 # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5 0.862067 # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total 0.862067 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 68282.840048 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 68282.840048 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78768.932669 # average WriteReq miss latency
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+system.cpu5.l1c.demand_avg_miss_latency::total 72436.371370 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 72436.371370 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 72436.371370 # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs 2200429 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 59918 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 60083 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.609249 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.623155 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9638 # number of writebacks
-system.cpu5.l1c.writebacks::total 9638 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36402 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36402 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23842 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23842 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60244 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60244 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60244 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60244 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2393170720 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2393170720 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1817634658 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1817634658 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4210805378 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 4210805378 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4210805378 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 4210805378 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1069731206 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1069731206 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 4068656749 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 4068656749 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 5138387955 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 5138387955 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806800 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806800 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954444 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954444 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859413 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.859413 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859413 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.859413 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 65742.836108 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 65742.836108 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76236.668820 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76236.668820 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 69895.846524 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 69895.846524 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 69895.846524 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 69895.846524 # average overall mshr miss latency
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+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 66168.699651 # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76678.600703 # average WriteReq mshr miss latency
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+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 98989 # number of read accesses completed
-system.cpu6.num_writes 55088 # number of write accesses completed
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.l1c.tags.replacements 22403 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 396.761014 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13429 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.588914 # Average number of references to valid blocks.
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+system.cpu6.num_writes 54995 # number of write accesses completed
+system.cpu6.l1c.tags.replacements 22115 # number of replacements
+system.cpu6.l1c.tags.tagsinuse 396.164371 # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs 13666 # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs 22491 # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs 0.607621 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 396.761014 # Average occupied blocks per requestor
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-system.cpu6.l1c.tags.occ_percent::total 0.774924 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses 336438 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 336438 # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6 8710 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8710 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1155 # number of WriteReq hits
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-system.cpu6.l1c.overall_hits::total 9865 # number of overall hits
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-system.cpu6.l1c.WriteReq_misses::total 23840 # number of WriteReq misses
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-system.cpu6.l1c.overall_accesses::total 69986 # number of overall (read+write) accesses
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-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 68113.409278 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 68113.409278 # average ReadReq miss latency
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-system.cpu6.l1c.demand_avg_miss_latency::total 72337.933601 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 72337.933601 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 72337.933601 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 2205749 # number of cycles access was blocked
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+system.cpu6.l1c.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses 338129 # Number of tag accesses
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+system.cpu6.l1c.overall_miss_rate::total 0.857841 # miss rate for overall accesses
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+system.cpu6.l1c.ReadReq_avg_miss_latency::total 67668.920397 # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78504.150970 # average WriteReq miss latency
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+system.cpu6.l1c.demand_avg_miss_latency::total 71960.797442 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 71960.797442 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 71960.797442 # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs 2202006 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 59981 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 60316 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.507825 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9866 # number of writebacks
-system.cpu6.l1c.writebacks::total 9866 # number of writebacks
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-system.cpu6.l1c.ReadReq_mshr_misses::total 36281 # number of ReadReq MSHR misses
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-system.cpu6.l1c.WriteReq_mshr_misses::total 23840 # number of WriteReq MSHR misses
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-system.cpu6.l1c.demand_mshr_misses::total 60121 # number of demand (read+write) MSHR misses
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-system.cpu6.l1c.overall_mshr_misses::total 60121 # number of overall MSHR misses
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-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2394594434 # number of ReadReq MSHR miss cycles
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-system.cpu6.l1c.demand_mshr_miss_latency::total 4222550438 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4222550438 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 4222550438 # number of overall MSHR miss cycles
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-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1072935197 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 3927350232 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 3927350232 # number of WriteReq MSHR uncacheable cycles
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-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 5000285429 # number of overall MSHR uncacheable cycles
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-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806406 # mshr miss rate for ReadReq accesses
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-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953791 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859043 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.859043 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859043 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.859043 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 66001.334969 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 66001.334969 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76676.006879 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76676.006879 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 70234.201660 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 70234.201660 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 70234.201660 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 70234.201660 # average overall mshr miss latency
+system.cpu6.l1c.writebacks::writebacks 9723 # number of writebacks
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 54842 # number of write accesses completed
-system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.l1c.tags.replacements 22131 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 396.248772 # Cycle average of tags in use
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-system.cpu7.l1c.tags.sampled_refs 22531 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.589943 # Average number of references to valid blocks.
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system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855196 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.854756 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853544 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.848521 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690310 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.698723 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.692649 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.705160 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.697204 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.703256 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.699494 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696926 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.697958 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.287190 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.287190 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46609.388976 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47294.175540 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46968.504190 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46619.681182 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46599.636225 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46979.961598 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46411.842407 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46998.478070 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 46814.400260 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40729.266988 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40637.839276 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40733.916624 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40707.684320 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40668.047644 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40676.045817 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40692.731830 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40745.622311 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40699.067460 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41205.156422 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41269.020356 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41204.249543 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41391.448237 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41230.624830 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41179.802430 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41288.807910 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41341.093430 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41264.266834 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.snoop_filter.tot_requests 122833 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 120785 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.trans_dist::ReadReq 83923 # Transaction distribution
+system.membus.trans_dist::ReadResp 83923 # Transaction distribution
+system.membus.trans_dist::WriteReq 43483 # Transaction distribution
+system.membus.trans_dist::WriteResp 43481 # Transaction distribution
+system.membus.trans_dist::Writeback 6000 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 58661 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 47607 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50527 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3086 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420691 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 420691 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1047472 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1047472 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 58495 # Total snoops (count)
+system.membus.snoop_fanout::samples 122833 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 122833 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 122833 # Request fanout histogram
+system.membus.reqLayer0.occupancy 472878500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 31.7 # Layer utilization (%)
+system.membus.respLayer0.occupancy 318922500 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 21.4 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 559080 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 259825 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 297207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 370692 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 370683 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43483 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43481 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 75478 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29380 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29380 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161449 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 161449 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120700 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120118 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120296 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120254 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120627 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119815 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120341 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119764 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 961915 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1743799 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1739946 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1755311 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1759542 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742748 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1748105 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1744654 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1747573 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 13981678 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 323561 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 559080 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.688315 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.176863 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 52722 9.43% 9.43% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 250233 44.76% 54.19% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 141253 25.27% 79.45% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 69107 12.36% 91.81% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 29981 5.36% 97.18% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 11505 2.06% 99.23% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 3559 0.64% 99.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 720 0.13% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 559080 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1490758741 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 160617515 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 10.8 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 159518006 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 159700003 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 158882050 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 10.6 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 159826982 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 158824012 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 10.6 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 159298538 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 158114013 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000667 # Number of seconds simulated
-sim_ticks 666669000 # Number of ticks simulated
-final_tick 666669000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 667077000 # Number of ticks simulated
+final_tick 667077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 141005098 # Simulator tick rate (ticks/s)
-host_mem_usage 405228 # Number of bytes of host memory used
-host_seconds 4.73 # Real time elapsed on the host
+host_tick_rate 152389795 # Simulator tick rate (ticks/s)
+host_mem_usage 222064 # Number of bytes of host memory used
+host_seconds 4.38 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 77587 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 78424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 78448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 79552 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 79510 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 77345 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 78315 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 77919 # Number of bytes read from this memory
-system.physmem.bytes_read::total 627100 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 389952 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5508 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5505 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5430 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5540 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5487 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5602 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory
-system.physmem.bytes_written::total 433881 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10807 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10825 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10786 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10966 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10880 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10905 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10824 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 86938 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6093 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5508 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5505 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5430 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5540 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5487 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5602 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50022 # Number of write requests responded to by this memory
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-system.physmem.bw_read::cpu1 117635588 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 117671588 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 119327582 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 119264583 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 116017094 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 117472089 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 116878091 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 940646708 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::cpu0 8261971 # Write bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::cpu3 8309971 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 8053472 # Write bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::cpu6 8402971 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 8231971 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 650819222 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 584925953 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 124642064 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu3 127637553 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 127318054 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 124247565 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 125875059 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 125110062 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1591465930 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 83865 # Transaction distribution
-system.membus.trans_dist::ReadResp 83861 # Transaction distribution
-system.membus.trans_dist::WriteReq 43929 # Transaction distribution
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-system.membus.trans_dist::Writeback 6093 # Transaction distribution
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-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1060914 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1060914 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 57934 # Total snoops (count)
-system.membus.snoop_fanout::samples 123225 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 123225 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 123225 # Request fanout histogram
-system.membus.reqLayer0.occupancy 288472152 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 43.3 # Layer utilization (%)
-system.membus.respLayer0.occupancy 310892000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 46.6 # Layer utilization (%)
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+system.physmem.bytes_read::cpu3 77551 # Number of bytes read from this memory
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+system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5426 # Number of write requests responded to by this memory
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+system.physmem.bw_read::cpu0 124260018 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu3 116254945 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 124147587 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 116299917 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 117287809 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 117527662 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 959487435 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 597616167 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 8184962 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::cpu3 8122001 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 8238929 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_write::total 663572571 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::cpu0 132444980 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 130080935 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu4 132386516 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 124448902 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu7 125661655 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1623060007 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 13077 # number of replacements
-system.l2c.tags.tagsinuse 783.417350 # Cycle average of tags in use
-system.l2c.tags.total_refs 150095 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 13853 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 10.834837 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 730.528683 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 6.960741 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 6.211335 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 6.682597 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.340197 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.666463 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 5.896963 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 7.159072 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 6.971301 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.713407 # Average percentage of cache occupancy
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-system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 1967301 # Number of tag accesses
-system.l2c.tags.data_accesses 1967301 # Number of data accesses
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-system.l2c.ReadReq_hits::cpu1 10684 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2 10837 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3 10726 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4 10661 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5 10672 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6 10767 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 10772 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 85828 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 76131 # number of Writeback hits
-system.l2c.Writeback_hits::total 76131 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 391 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 342 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 349 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 346 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 350 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 327 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 361 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2756 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu1 1955 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2 1901 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 1956 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1993 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1935 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1923 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1905 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 15515 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu2 12738 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 12682 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 12654 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 12607 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 12690 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12677 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu2 12738 # number of overall hits
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-system.l2c.overall_hits::cpu4 12654 # number of overall hits
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-system.l2c.ReadReq_misses::cpu2 686 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3 704 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4 731 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5 661 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6 687 # number of ReadReq misses
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-system.l2c.ReadReq_accesses::cpu4 11392 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu5 11333 # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu7 11467 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 91380 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 76131 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 76131 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0 2291 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu3 2278 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4 2304 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5 2330 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6 2263 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7 2270 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu3 0.846795 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.849826 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5 0.849785 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6 0.855502 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7 0.840969 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1 30063.506507 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2 29142.670279 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3 28476.412131 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu4 28295.962717 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu5 28907.321717 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 29543.387397 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 28235.201152 # average UpgradeReq miss latency
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-system.l2c.overall_avg_miss_latency::cpu7 54987.261914 # average overall miss latency
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-system.l2c.blocked::no_mshrs 1706 # number of cycles access was blocked
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-system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits
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-system.l2c.ReadExReq_mshr_miss_latency::cpu2 182934447 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3 182700448 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu4 184033448 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu5 189305939 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu6 184033940 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu7 180980939 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 1468468550 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0 217697861 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1 216339861 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2 217364370 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3 217393372 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu4 219282384 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu5 221532365 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu6 217974360 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu7 215693352 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 1743277925 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0 217697861 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1 216339861 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2 217364370 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3 217393372 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu4 219282384 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu5 221532365 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu6 217974360 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu7 215693352 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 1743277925 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 401967952 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 402344948 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 400970454 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 406380953 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407457452 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405842942 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 405383447 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 402958951 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 3233307099 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 231807968 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 231164475 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 229115474 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 232479973 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225183971 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232284466 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 236479465 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230210970 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 1848726762 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0 633775920 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1 633509423 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2 630085928 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3 638860926 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu4 632641423 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu5 638127408 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu6 641862912 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu7 633169921 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 5082033861 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0 0.062172 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1 0.059238 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2 0.059360 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3 0.060980 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063641 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu5 0.057443 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059892 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu7 0.059998 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.060341 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.829332 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.848873 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.869390 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.846356 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.849392 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.849785 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.855502 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.840969 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.848631 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690782 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689960 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.697730 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.690341 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687803 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.700665 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.695068 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.694364 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.693348 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0 0.285730 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1 0.284802 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2 0.284985 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3 0.285433 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4 0.288227 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5 0.291227 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6 0.285883 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7 0.283690 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.286250 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0 0.285730 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1 0.284802 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2 0.284985 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3 0.285433 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4 0.288227 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5 0.291227 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6 0.285883 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7 0.283690 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.286250 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50354.101408 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50233.166419 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50336.144737 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49774.639885 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.222069 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49502.958525 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49475.830904 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50454.088663 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 49838.479325 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41049.998421 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40981.517439 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41048.265359 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41030.340768 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41011.750128 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41039.138889 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41074.378616 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41002.617601 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41029.801073 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41788.343822 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41826.979835 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41623.309898 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41769.649749 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41787.794732 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41752.522938 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41854.432568 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41729.522481 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41766.505020 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 42989.309044 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 42950.141155 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 42796.686356 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 42869.921514 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 42753.438097 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 42725.624879 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 42883.013968 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 42924.050149 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 42860.814914 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 42989.309044 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 42950.141155 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 42796.686356 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 42869.921514 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 42753.438097 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 42725.624879 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 42883.013968 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 42924.050149 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 42860.814914 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.toL2Bus.trans_dist::ReadReq 370706 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370692 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43929 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43926 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 76131 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 28975 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 28973 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 161585 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 161579 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120187 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120466 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120142 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120511 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120525 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120784 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120880 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120421 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 963916 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756245 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1754904 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1765350 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754211 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1769359 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771216 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757581 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1758989 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14087855 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 322583 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 561153 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 561153 100.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 561153 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 655042579 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 160407425 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 161285735 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 160748299 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 160702936 # Layer occupancy (ticks)
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system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
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system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
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-system.cpu2.l1c.demand_avg_miss_latency::total 30813.966045 # average overall miss latency
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-system.cpu2.l1c.overall_avg_miss_latency::total 30813.966045 # average overall miss latency
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system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu2.l1c.writebacks::total 9856 # number of writebacks
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-system.cpu2.l1c.demand_mshr_misses::total 60286 # number of demand (read+write) MSHR misses
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-system.cpu2.l1c.overall_mshr_misses::total 60286 # number of overall MSHR misses
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-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 889398318 # number of ReadReq MSHR miss cycles
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-system.cpu2.l1c.demand_mshr_miss_latency::total 1729207391 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1729207391 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1729207391 # number of overall MSHR miss cycles
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-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 693154089 # number of ReadReq MSHR uncacheable cycles
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-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2382490120 # number of overall MSHR uncacheable cycles
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-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858323 # mshr miss rate for demand accesses
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-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24356.400427 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24356.400427 # average ReadReq mshr miss latency
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-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35330.629912 # average WriteReq mshr miss latency
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-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28683.398982 # average overall mshr miss latency
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+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency
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system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 54970 # number of write accesses completed
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.l1c.tags.replacements 22272 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 393.391803 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13521 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22662 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.596638 # Average number of references to valid blocks.
+system.cpu3.num_reads 99256 # number of read accesses completed
+system.cpu3.num_writes 54955 # number of write accesses completed
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+system.cpu3.l1c.tags.tagsinuse 394.489449 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13390 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 23054 # Sample count of references to valid blocks.
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system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 393.391803 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.768343 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.768343 # Average percentage of cache occupancy
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-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 337590 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 337590 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8806 # number of ReadReq hits
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-system.cpu3.l1c.overall_hits::total 9965 # number of overall hits
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-system.cpu3.l1c.ReadReq_avg_miss_latency::total 26367.786823 # average ReadReq miss latency
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-system.cpu3.l1c.WriteReq_avg_miss_latency::total 37195.641008 # average WriteReq miss latency
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-system.cpu3.l1c.overall_avg_miss_latency::total 30657.251813 # average overall miss latency
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9730 # number of writebacks
-system.cpu3.l1c.writebacks::total 9730 # number of writebacks
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-system.cpu3.l1c.WriteReq_mshr_misses::total 23878 # number of WriteReq MSHR misses
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-system.cpu3.l1c.demand_mshr_misses::total 60275 # number of demand (read+write) MSHR misses
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-system.cpu3.l1c.overall_mshr_misses::total 60275 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 882022203 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882022203 # number of ReadReq MSHR miss cycles
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-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 837608778 # number of WriteReq MSHR miss cycles
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-system.cpu3.l1c.demand_mshr_miss_latency::total 1719630981 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719630981 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1719630981 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 701721013 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 701721013 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1702236593 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1702236593 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2403957606 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2403957606 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805190 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805190 # mshr miss rate for ReadReq accesses
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-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953709 # mshr miss rate for WriteReq accesses
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-system.cpu3.l1c.demand_mshr_miss_rate::total 0.858129 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858129 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.858129 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24233.376460 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24233.376460 # average ReadReq mshr miss latency
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-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35078.682385 # average WriteReq mshr miss latency
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-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28529.754973 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28529.754973 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28529.754973 # average overall mshr miss latency
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+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99302 # number of read accesses completed
-system.cpu4.num_writes 55134 # number of write accesses completed
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.l1c.tags.replacements 22459 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 393.483256 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13509 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22848 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.591255 # Average number of references to valid blocks.
+system.cpu4.num_reads 99292 # number of read accesses completed
+system.cpu4.num_writes 54781 # number of write accesses completed
+system.cpu4.l1c.tags.replacements 22192 # number of replacements
+system.cpu4.l1c.tags.tagsinuse 393.392100 # Cycle average of tags in use
+system.cpu4.l1c.tags.total_refs 13471 # Total number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs 22589 # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs 0.596352 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 393.483256 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.768522 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.768522 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 356 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 337715 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 337715 # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1196 # number of WriteReq hits
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-system.cpu4.l1c.overall_hits::total 9935 # number of overall hits
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-system.cpu4.l1c.ReadReq_misses::total 36407 # number of ReadReq misses
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-system.cpu4.l1c.demand_misses::total 60321 # number of demand (read+write) misses
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-system.cpu4.l1c.overall_misses::total 60321 # number of overall misses
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-system.cpu4.l1c.ReadReq_miss_latency::total 962640133 # number of ReadReq miss cycles
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-system.cpu4.l1c.overall_miss_latency::total 1852096434 # number of overall miss cycles
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-system.cpu4.l1c.overall_accesses::total 70256 # number of overall (read+write) accesses
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-system.cpu4.l1c.WriteReq_miss_rate::total 0.952370 # miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_miss_rate::total 0.858589 # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4 0.858589 # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total 0.858589 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26441.072678 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 26441.072678 # average ReadReq miss latency
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-system.cpu4.l1c.overall_avg_miss_latency::total 30704.007460 # average overall miss latency
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu4.l1c.writebacks::total 9933 # number of writebacks
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-system.cpu4.l1c.overall_mshr_misses::total 60321 # number of overall MSHR misses
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-system.cpu4.l1c.demand_mshr_miss_latency::total 1723760656 # number of demand (read+write) MSHR miss cycles
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-system.cpu4.l1c.overall_mshr_miss_latency::total 1723760656 # number of overall MSHR miss cycles
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-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 703520432 # number of ReadReq MSHR uncacheable cycles
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-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2361666982 # number of overall MSHR uncacheable cycles
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-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35079.551602 # average WriteReq mshr miss latency
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system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu5.num_writes 55294 # number of write accesses completed
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.l1c.tags.replacements 22607 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 394.741985 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13577 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 23024 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.589689 # Average number of references to valid blocks.
+system.cpu5.num_reads 99672 # number of read accesses completed
+system.cpu5.num_writes 54824 # number of write accesses completed
+system.cpu5.l1c.tags.replacements 22459 # number of replacements
+system.cpu5.l1c.tags.tagsinuse 393.671106 # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs 13533 # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs 22853 # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs 0.592176 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 394.741985 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.770980 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.770980 # Average percentage of cache occupancy
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-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 338075 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 338075 # Number of data accesses
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-system.cpu5.l1c.overall_hits::total 9949 # number of overall hits
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-system.cpu5.l1c.overall_miss_rate::total 0.858566 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26198.990477 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 26198.990477 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37500.677145 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 37500.677145 # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 30681.677854 # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 30681.677854 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 30681.677854 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 30681.677854 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 1031399 # number of cycles access was blocked
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+system.cpu5.l1c.tags.occ_percent::total 0.768889 # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses 337969 # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses 337969 # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5 8696 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total 8696 # number of ReadReq hits
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+system.cpu5.l1c.overall_hits::cpu5 9866 # number of overall hits
+system.cpu5.l1c.overall_hits::total 9866 # number of overall hits
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+system.cpu5.l1c.WriteReq_misses::total 23786 # number of WriteReq misses
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+system.cpu5.l1c.overall_misses::total 60444 # number of overall misses
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+system.cpu5.l1c.ReadReq_miss_latency::total 958216057 # number of ReadReq miss cycles
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+system.cpu5.l1c.WriteReq_miss_latency::total 885896912 # number of WriteReq miss cycles
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+system.cpu5.l1c.demand_miss_latency::total 1844112969 # number of demand (read+write) miss cycles
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+system.cpu5.l1c.overall_miss_latency::total 1844112969 # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5 45354 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total 45354 # number of ReadReq accesses(hits+misses)
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+system.cpu5.l1c.WriteReq_accesses::total 24956 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5 70310 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses
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+system.cpu5.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808264 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total 0.808264 # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953117 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total 0.953117 # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5 0.859679 # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total 0.859679 # miss rate for demand accesses
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+system.cpu5.l1c.overall_miss_rate::total 0.859679 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26139.343581 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 26139.343581 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37244.467838 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 37244.467838 # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 30509.446248 # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 30509.446248 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 30509.446248 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 30509.446248 # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs 1026604 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 62997 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 63359 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.372192 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.202970 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9959 # number of writebacks
-system.cpu5.l1c.writebacks::total 9959 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36440 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36440 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23955 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23955 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60395 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60395 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60395 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60395 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 876841351 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 876841351 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 847650833 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 847650833 # number of WriteReq MSHR miss cycles
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-system.cpu5.l1c.demand_mshr_miss_latency::total 1724492184 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1724492184 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1724492184 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 699333550 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 699333550 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1696976001 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1696976001 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2396309551 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2396309551 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805019 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805019 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955220 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955220 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858566 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.858566 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858566 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.858566 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24062.605681 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24062.605681 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35385.131831 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35385.131831 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28553.558805 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28553.558805 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28553.558805 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28553.558805 # average overall mshr miss latency
+system.cpu5.l1c.writebacks::writebacks 9812 # number of writebacks
+system.cpu5.l1c.writebacks::total 9812 # number of writebacks
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+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 707107291 # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1680181552 # number of WriteReq MSHR uncacheable cycles
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+system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2387288843 # number of overall MSHR uncacheable cycles
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+system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808264 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953117 # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953117 # mshr miss rate for WriteReq accesses
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+system.cpu5.l1c.demand_mshr_miss_rate::total 0.859679 # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total 0.859679 # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24002.189454 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24002.189454 # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35129.324224 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35129.324224 # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 100001 # number of read accesses completed
-system.cpu6.num_writes 55113 # number of write accesses completed
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.l1c.tags.replacements 22596 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 393.612008 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13438 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 23004 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.584159 # Average number of references to valid blocks.
+system.cpu6.num_reads 99511 # number of read accesses completed
+system.cpu6.num_writes 54977 # number of write accesses completed
+system.cpu6.l1c.tags.replacements 22541 # number of replacements
+system.cpu6.l1c.tags.tagsinuse 393.448229 # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs 13464 # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs 0.586948 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 393.612008 # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6 0.768773 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total 0.768773 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses 338625 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 338625 # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6 8756 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8756 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1144 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1144 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9900 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9900 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9900 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9900 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36780 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36780 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 23744 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 23744 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 60524 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 60524 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 60524 # number of overall misses
-system.cpu6.l1c.overall_misses::total 60524 # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6 967768080 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total 967768080 # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6 885331630 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total 885331630 # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6 1853099710 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total 1853099710 # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6 1853099710 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total 1853099710 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 45536 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total 45536 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6 24888 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total 24888 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6 70424 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total 70424 # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6 70424 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total 70424 # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807713 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954034 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total 0.954034 # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6 0.859423 # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total 0.859423 # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6 0.859423 # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total 0.859423 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26312.345840 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 26312.345840 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37286.541021 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 37286.541021 # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 30617.601447 # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 30617.601447 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 30617.601447 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 30617.601447 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 1031115 # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6 393.448229 # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6 0.768454 # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total 0.768454 # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses 337704 # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses 337704 # Number of data accesses
+system.cpu6.l1c.ReadReq_hits::cpu6 8641 # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total 8641 # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6 1220 # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total 1220 # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits
+system.cpu6.l1c.overall_hits::total 9861 # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6 36671 # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total 36671 # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6 23713 # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total 23713 # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6 60384 # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total 60384 # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6 60384 # number of overall misses
+system.cpu6.l1c.overall_misses::total 60384 # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6 960694665 # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total 960694665 # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6 879536054 # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total 879536054 # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6 1840230719 # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total 1840230719 # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6 1840230719 # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total 1840230719 # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6 45312 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total 45312 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6 24933 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total 24933 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6 70245 # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total 70245 # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6 70245 # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total 70245 # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.809300 # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total 0.809300 # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951069 # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total 0.951069 # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6 0.859620 # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6 0.859620 # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26197.667503 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 26197.667503 # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37090.880698 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 37090.880698 # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 30475.468982 # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 30475.468982 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 30475.468982 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 30475.468982 # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs 1019991 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 63035 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 62969 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.357817 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.198304 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9778 # number of writebacks
-system.cpu6.l1c.writebacks::total 9778 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36780 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36780 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23744 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 23744 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 60524 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 60524 # number of demand (read+write) MSHR misses
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-system.cpu6.l1c.overall_mshr_misses::total 60524 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 889223312 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 889223312 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 835020954 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 835020954 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1724244266 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total 1724244266 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1724244266 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 1724244266 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 698387416 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 698387416 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1741021536 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1741021536 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2439408952 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2439408952 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807713 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954034 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954034 # mshr miss rate for WriteReq accesses
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-system.cpu6.l1c.demand_mshr_miss_rate::total 0.859423 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859423 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.859423 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24176.816531 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24176.816531 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 35167.661472 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 35167.661472 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28488.603959 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28488.603959 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28488.603959 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28488.603959 # average overall mshr miss latency
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+system.cpu6.l1c.writebacks::total 9771 # number of writebacks
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+system.cpu6.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24063.313708 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24063.313708 # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34974.539957 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34974.539957 # average WriteReq mshr miss latency
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+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 99455 # number of read accesses completed
-system.cpu7.num_writes 55321 # number of write accesses completed
-system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.l1c.tags.replacements 22276 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 392.282274 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13267 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22648 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.585791 # Average number of references to valid blocks.
+system.cpu7.num_reads 98836 # number of read accesses completed
+system.cpu7.num_writes 54806 # number of write accesses completed
+system.cpu7.l1c.tags.replacements 22352 # number of replacements
+system.cpu7.l1c.tags.tagsinuse 393.572142 # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs 13400 # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs 22745 # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs 0.589140 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 392.282274 # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7 0.766176 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total 0.766176 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024 372 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0 356 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.726562 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 337172 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 337172 # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7 8517 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8517 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1168 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total 1168 # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7 9685 # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total 9685 # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7 9685 # number of overall hits
-system.cpu7.l1c.overall_hits::total 9685 # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7 36632 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total 36632 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7 23782 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total 23782 # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7 60414 # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total 60414 # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7 60414 # number of overall misses
-system.cpu7.l1c.overall_misses::total 60414 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7 969238606 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total 969238606 # number of ReadReq miss cycles
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-system.cpu7.l1c.WriteReq_miss_latency::total 880763834 # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7 1850002440 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total 1850002440 # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7 1850002440 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total 1850002440 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 45149 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total 45149 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7 24950 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses)
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-system.cpu7.l1c.demand_accesses::total 70099 # number of demand (read+write) accesses
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-system.cpu7.l1c.overall_accesses::total 70099 # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.811358 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total 0.811358 # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953186 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total 0.953186 # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7 0.861838 # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total 0.861838 # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7 0.861838 # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total 0.861838 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26458.795752 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 26458.795752 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37034.893365 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 37034.893365 # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 30622.081637 # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 30622.081637 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 30622.081637 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 30622.081637 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 1029627 # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7 393.572142 # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7 0.768696 # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total 0.768696 # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0 363 # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses 336509 # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses 336509 # Number of data accesses
+system.cpu7.l1c.ReadReq_hits::cpu7 8699 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total 8699 # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7 1106 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total 1106 # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7 9805 # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total 9805 # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7 9805 # number of overall hits
+system.cpu7.l1c.overall_hits::total 9805 # number of overall hits
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+system.cpu7.l1c.ReadReq_misses::total 36228 # number of ReadReq misses
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+system.cpu7.l1c.WriteReq_misses::total 23958 # number of WriteReq misses
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+system.cpu7.l1c.demand_misses::total 60186 # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7 60186 # number of overall misses
+system.cpu7.l1c.overall_misses::total 60186 # number of overall misses
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+system.cpu7.l1c.ReadReq_miss_latency::total 952764751 # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7 890612165 # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total 890612165 # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7 1843376916 # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total 1843376916 # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7 1843376916 # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total 1843376916 # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7 44927 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total 44927 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7 25064 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total 25064 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7 69991 # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total 69991 # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7 69991 # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total 69991 # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806375 # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total 0.806375 # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955873 # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total 0.955873 # miss rate for WriteReq accesses
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+system.cpu7.l1c.demand_miss_rate::total 0.859911 # miss rate for demand accesses
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu7.l1c.cache_copies 0 # number of cache copies performed
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system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 84242 # Transaction distribution
+system.membus.trans_dist::ReadResp 84239 # Transaction distribution
+system.membus.trans_dist::WriteReq 43998 # Transaction distribution
+system.membus.trans_dist::WriteResp 43998 # Transaction distribution
+system.membus.trans_dist::Writeback 6229 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 58563 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 47765 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50044 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3111 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 422189 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 422189 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1082703 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1082703 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 57731 # Total snoops (count)
+system.membus.snoop_fanout::samples 123701 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 123701 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 123701 # Request fanout histogram
+system.membus.reqLayer0.occupancy 290076020 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 43.5 # Layer utilization (%)
+system.membus.respLayer0.occupancy 312416500 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 46.8 # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq 371224 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 371216 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43998 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43997 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 76237 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29460 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29459 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161009 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 161004 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120675 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121112 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120676 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120671 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120387 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120891 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120940 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120505 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 965857 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1759071 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1770038 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776630 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1763929 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1758071 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1768584 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1767034 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1770802 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14134159 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 321748 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 561380 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 561380 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 561380 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 655414034 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 160915376 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 161401861 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 160885313 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 160977419 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 160313901 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 24.0 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 161018393 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 160998320 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 24.1 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 160391036 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 24.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff