arch-riscv: fix MIE csr register setting bugs
authorCui Jin <cuijin7@huawei.com>
Tue, 22 Dec 2020 08:46:46 +0000 (16:46 +0800)
committerCui Jin <cuijin7@huawei.com>
Thu, 31 Dec 2020 03:17:09 +0000 (03:17 +0000)
Any changes on xIE bits changes should trigger the updating
of CSR register. The old condition is wrongly reversed.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-855

Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38578
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/isa/formats/standard.isa

index 72f7dc1d29c0bf0381a3946dda22fda54d8d177c..b95af762335010ea27ac034a6c9127c015a53985 100644 (file)
@@ -383,9 +383,9 @@ def template CSRExecute {{
                             xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
                             break;
                           case CSR_MIP: case CSR_MIE:
-                            if (oldinterrupt.mei == newinterrupt.mei &&
-                                oldinterrupt.mti == newinterrupt.mti &&
-                                oldinterrupt.msi == newinterrupt.msi) {
+                            if (oldinterrupt.mei != newinterrupt.mei ||
+                                oldinterrupt.mti != newinterrupt.mti ||
+                                oldinterrupt.msi != newinterrupt.msi) {
                                 xc->setMiscReg(CSRData.at(csr).physIndex,data);
                             } else {
                                 std::string error = "Interrupt m bits are "