add fabs unit test

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index c0e384df003a842590252786704ee7ef7f232ccf..d677be4f3a2e2ec680a636e71847084cabf11cb3 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -96,6 +96,30 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 
+    def test_fp_abs(self):
+        """>>> lst = ["fabs 3, 1",
+                      "fabs 4, 2",
+                     ]
+        """
+        lst = ["fabs 3, 1",
+               "fabs 4, 2",
+                     ]
+
+        fprs = [0] * 32
+        fprs[1] = 0xC040266660000000
+        fprs[2] = 0x4040266660000000
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            print("FPR 1", sim.fpr(1))
+            print("FPR 2", sim.fpr(2))
+            print("FPR 3", sim.fpr(3))
+            print("FPR 4", sim.fpr(4))
+            self.assertEqual(sim.fpr(1), SelectableInt(0xC040266660000000, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
+            self.assertEqual(sim.fpr(3), SelectableInt(0x4040266660000000, 64))
+            self.assertEqual(sim.fpr(4), SelectableInt(0x4040266660000000, 64))
+
     def run_tst_program(self, prog, initial_regs=None,
                               initial_mem=None,
                               initial_fprs=None):