v850.md (divmodhi4): Make sure to sign extend the dividend to 32 bits.

	* config/v850/v850.md (divmodhi4): Make sure to sign extend the
	dividend to 32 bits.  Adjust length.
	(udivmodhi4): Cleanup output template.  Fix length.

From-SVN: r262022

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 754b5f1006313396b1e45f386a2864acff114345..ceec833bb708204bb476de2586438933f0051dbf 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-06-25  Jeff Law  <law@redhat.com>
+
+       * config/v850/v850.md (divmodhi4): Make sure to sign extend the
+       dividend to 32 bits.  Adjust length.
+       (udivmodhi4): Cleanup output template.  Fix length.
+
 2018-06-25  Carl Love  <cel@us.ibm.com>
 
        * config/rs6000/vsx.md: Change word selector to prefered location.

diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index 2656e90c90bf75a0ed55ea3cc8e1bea0c2127c70..e01a3102c31406cba77c8934203f1bc01dd7d336 100644 (file)
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -738,13 +738,13 @@
                (match_dup 2)))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_V850E_UP"
-  "divh %2,%0,%3"
-  [(set_attr "length" "4")
+  "sxh %0\n\tdivh %2,%0,%3"
+  [(set_attr "length" "6")
    (set_attr "cc" "clobber")
    (set_attr "type" "div")])
 
-;; Half-words are sign-extended by default, so we must zero extend to a word
-;; here before doing the divide.
+;; The half word needs to be zero/sign extended to 32 bits before doing
+;; the division/modulo operation.
 
 (define_insn "udivmodhi4"
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -755,8 +755,8 @@
                 (match_dup 2)))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_V850E_UP"
-  "zxh %0 ; divhu %2,%0,%3"
-  [(set_attr "length" "4")
+  "zxh %0\n\tdivhu %2,%0,%3"
+  [(set_attr "length" "6")
    (set_attr "cc" "clobber")
    (set_attr "type" "div")])
 \f