targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 5fe17147b29b85de25ee2ba58c38a6254a5f5b5b..ce7a13d98b8ebe3b83afce4a5bec2fe77e89ea54 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -72,7 +72,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------