* config/bfin-parse.y: Remove trailing whitespace.
(ccstat): Indent.
* config/tc-bfin.c (struct bfin_reg_entry): Remove.
(bfin_reg_info[]): Remove.
opcodes/
* bfin-dis.c (_print_insn_bfin): Don't declare.
(print_insn_bfin): Don't declare.
(dregs_pair): Remove.
(ignore_bits): Remove.
(ccstat): Remove.
+2009-09-03 Jie Zhang <jie.zhang@analog.com>
+
+ * config/bfin-parse.y: Remove trailing whitespace.
+ (ccstat): Indent.
+ * config/tc-bfin.c (struct bfin_reg_entry): Remove.
+ (bfin_reg_info[]): Remove.
+
2009-09-03 Jie Zhang <jie.zhang@analog.com>
* config/bfin-defs.h (F_REG_ALL): Remove macro.
%type <reg> a_minusassign
%type <macfunc> multiply_halfregs
%type <macfunc> assign_macfunc
-%type <macfunc> a_macfunc
+%type <macfunc> a_macfunc
%type <expr> expr_1
%type <instr> asm_1
%type <r0> vmod
ccstat:
CCREG cc_op STATUS_REG
{
- $$.r0 = $3.regno;
- $$.x0 = $2.r0;
- $$.s0 = 0;
+ $$.r0 = $3.regno;
+ $$.x0 = $2.r0;
+ $$.s0 = 0;
}
| CCREG cc_op V
{
- $$.r0 = 0x18;
- $$.x0 = $2.r0;
- $$.s0 = 0;
+ $$.r0 = 0x18;
+ $$.x0 = $2.r0;
+ $$.s0 = 0;
}
| STATUS_REG cc_op CCREG
{
- $$.r0 = $1.regno;
- $$.x0 = $2.r0;
- $$.s0 = 1;
+ $$.r0 = $1.regno;
+ $$.x0 = $2.r0;
+ $$.s0 = 1;
}
| V cc_op CCREG
{
- $$.r0 = 0x18;
- $$.x0 = $2.r0;
- $$.s0 = 1;
+ $$.r0 = 0x18;
+ $$.x0 = $2.r0;
+ $$.s0 = 1;
}
;
static flagword bfin_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
static const char *bfin_pic_flag = DEFAULT_FDPIC ? "-mfdpic" : (const char *)0;
-/* Registers list. */
-struct bfin_reg_entry
-{
- const char *name;
- int number;
-};
-
-static const struct bfin_reg_entry bfin_reg_info[] = {
- {"R0.L", REG_RL0},
- {"R1.L", REG_RL1},
- {"R2.L", REG_RL2},
- {"R3.L", REG_RL3},
- {"R4.L", REG_RL4},
- {"R5.L", REG_RL5},
- {"R6.L", REG_RL6},
- {"R7.L", REG_RL7},
- {"R0.H", REG_RH0},
- {"R1.H", REG_RH1},
- {"R2.H", REG_RH2},
- {"R3.H", REG_RH3},
- {"R4.H", REG_RH4},
- {"R5.H", REG_RH5},
- {"R6.H", REG_RH6},
- {"R7.H", REG_RH7},
- {"R0", REG_R0},
- {"R1", REG_R1},
- {"R2", REG_R2},
- {"R3", REG_R3},
- {"R4", REG_R4},
- {"R5", REG_R5},
- {"R6", REG_R6},
- {"R7", REG_R7},
- {"P0", REG_P0},
- {"P0.H", REG_P0},
- {"P0.L", REG_P0},
- {"P1", REG_P1},
- {"P1.H", REG_P1},
- {"P1.L", REG_P1},
- {"P2", REG_P2},
- {"P2.H", REG_P2},
- {"P2.L", REG_P2},
- {"P3", REG_P3},
- {"P3.H", REG_P3},
- {"P3.L", REG_P3},
- {"P4", REG_P4},
- {"P4.H", REG_P4},
- {"P4.L", REG_P4},
- {"P5", REG_P5},
- {"P5.H", REG_P5},
- {"P5.L", REG_P5},
- {"SP", REG_SP},
- {"SP.L", REG_SP},
- {"SP.H", REG_SP},
- {"FP", REG_FP},
- {"FP.L", REG_FP},
- {"FP.H", REG_FP},
- {"A0x", REG_A0x},
- {"A1x", REG_A1x},
- {"A0w", REG_A0w},
- {"A1w", REG_A1w},
- {"A0.x", REG_A0x},
- {"A1.x", REG_A1x},
- {"A0.w", REG_A0w},
- {"A1.w", REG_A1w},
- {"A0", REG_A0},
- {"A0.L", REG_A0},
- {"A0.H", REG_A0},
- {"A1", REG_A1},
- {"A1.L", REG_A1},
- {"A1.H", REG_A1},
- {"I0", REG_I0},
- {"I0.L", REG_I0},
- {"I0.H", REG_I0},
- {"I1", REG_I1},
- {"I1.L", REG_I1},
- {"I1.H", REG_I1},
- {"I2", REG_I2},
- {"I2.L", REG_I2},
- {"I2.H", REG_I2},
- {"I3", REG_I3},
- {"I3.L", REG_I3},
- {"I3.H", REG_I3},
- {"M0", REG_M0},
- {"M0.H", REG_M0},
- {"M0.L", REG_M0},
- {"M1", REG_M1},
- {"M1.H", REG_M1},
- {"M1.L", REG_M1},
- {"M2", REG_M2},
- {"M2.H", REG_M2},
- {"M2.L", REG_M2},
- {"M3", REG_M3},
- {"M3.H", REG_M3},
- {"M3.L", REG_M3},
- {"B0", REG_B0},
- {"B0.H", REG_B0},
- {"B0.L", REG_B0},
- {"B1", REG_B1},
- {"B1.H", REG_B1},
- {"B1.L", REG_B1},
- {"B2", REG_B2},
- {"B2.H", REG_B2},
- {"B2.L", REG_B2},
- {"B3", REG_B3},
- {"B3.H", REG_B3},
- {"B3.L", REG_B3},
- {"L0", REG_L0},
- {"L0.H", REG_L0},
- {"L0.L", REG_L0},
- {"L1", REG_L1},
- {"L1.H", REG_L1},
- {"L1.L", REG_L1},
- {"L2", REG_L2},
- {"L2.H", REG_L2},
- {"L2.L", REG_L2},
- {"L3", REG_L3},
- {"L3.H", REG_L3},
- {"L3.L", REG_L3},
- {"AZ", S_AZ},
- {"AN", S_AN},
- {"AC0", S_AC0},
- {"AC1", S_AC1},
- {"AV0", S_AV0},
- {"AV0S", S_AV0S},
- {"AV1", S_AV1},
- {"AV1S", S_AV1S},
- {"AQ", S_AQ},
- {"V", S_V},
- {"VS", S_VS},
- {"sftreset", REG_sftreset},
- {"omode", REG_omode},
- {"excause", REG_excause},
- {"emucause", REG_emucause},
- {"idle_req", REG_idle_req},
- {"hwerrcause", REG_hwerrcause},
- {"CC", REG_CC},
- {"LC0", REG_LC0},
- {"LC1", REG_LC1},
- {"ASTAT", REG_ASTAT},
- {"RETS", REG_RETS},
- {"LT0", REG_LT0},
- {"LB0", REG_LB0},
- {"LT1", REG_LT1},
- {"LB1", REG_LB1},
- {"CYCLES", REG_CYCLES},
- {"CYCLES2", REG_CYCLES2},
- {"USP", REG_USP},
- {"SEQSTAT", REG_SEQSTAT},
- {"SYSCFG", REG_SYSCFG},
- {"RETI", REG_RETI},
- {"RETX", REG_RETX},
- {"RETN", REG_RETN},
- {"RETE", REG_RETE},
- {"EMUDAT", REG_EMUDAT},
- {0, 0}
-};
-
/* Blackfin specific function to handle FD-PIC pointer initializations. */
static void
+2009-09-03 Jie Zhang <jie.zhang@analog.com>
+
+ * bfin-dis.c (_print_insn_bfin): Don't declare.
+ (print_insn_bfin): Don't declare.
+ (dregs_pair): Remove.
+ (ignore_bits): Remove.
+ (ccstat): Remove.
+
2009-09-03 Jie Zhang <jie.zhang@analog.com>
* bfin-dis.c (IS_DREG): Define.
{ "huimm32e", 32, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1},
};
-int _print_insn_bfin (bfd_vma pc, disassemble_info * outf);
-int print_insn_bfin (bfd_vma pc, disassemble_info * outf);
-
static char comment = 0;
static char parallel = 0;
};
#define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
-#define dregs_pair(x) REGNAME (decode_dregs_pair[(x) & 7])
/* P(0..5) SP FP. */
static enum machine_registers decode_pregs[] =
REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
};
-#define statbits(x) REGNAME (decode_statbits[(x) & 31])
-#define ignore_bits(x) REGNAME (decode_ignore_bits[(x) & 7])
-#define ccstat(x) REGNAME (decode_ccstat[(x) & 0])
+#define statbits(x) REGNAME (decode_statbits[(x) & 31])
/* LC0 LC1. */
static enum machine_registers decode_counters[] =
return 4;
}
-int
+static int
_print_insn_bfin (bfd_vma pc, disassemble_info *outf)
{
bfd_byte buf[4];
projects / binutils-gdb.git / commitdiff