radv: remove radv_get_image_fmask_info()

It's unnecessary to duplicate fields in another struct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index b1da5815f48f80669031a202d8409ee1d54edd75..cb83cde08cfca85eba97679841d853ed730d94a1 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4414,9 +4414,9 @@ radv_initialise_color_surface(struct radv_device *device,
 
                if (radv_image_has_fmask(iview->image)) {
                        if (device->physical_device->rad_info.chip_class >= GFX7)
-                               cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
-                       cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
-                       cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
+                               cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
+                       cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
+                       cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
                } else {
                        /* This must be set for fast clear to work without FMASK. */
                        if (device->physical_device->rad_info.chip_class >= GFX7)
@@ -4457,9 +4457,9 @@ radv_initialise_color_surface(struct radv_device *device,
        }
 
        if (radv_image_has_fmask(iview->image)) {
-               va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
+               va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
                cb->cb_color_fmask = va >> 8;
-               cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
+               cb->cb_color_fmask |= surf->fmask_tile_swizzle;
        } else {
                cb->cb_color_fmask = cb->cb_color_base;
        }
@@ -4509,7 +4509,7 @@ radv_initialise_color_surface(struct radv_device *device,
        if (radv_image_has_fmask(iview->image)) {
                cb->cb_color_info |= S_028C70_COMPRESSION(1);
                if (device->physical_device->rad_info.chip_class == GFX6) {
-                       unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
+                       unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
                        cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
                }
 

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index aaaf15ec8dc6fc02e45ac7065ee9ce87fcc2153f..efbb9de96b73fcb1a7cca03692a3685424a1d7b4 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -715,7 +715,7 @@ gfx10_make_texture_descriptor(struct radv_device *device,
 
                assert(image->plane_count == 1);
 
-               va = gpu_address + image->offset + image->fmask.offset;
+               va = gpu_address + image->offset + image->fmask_offset;
 
                switch (image->info.samples) {
                case 2:
@@ -879,7 +879,7 @@ si_make_texture_descriptor(struct radv_device *device,
 
                assert(image->plane_count == 1);
 
-               va = gpu_address + image->offset + image->fmask.offset;
+               va = gpu_address + image->offset + image->fmask_offset;
 
                if (device->physical_device->rad_info.chip_class == GFX9) {
                        fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
@@ -915,7 +915,7 @@ si_make_texture_descriptor(struct radv_device *device,
                }
 
                fmask_state[0] = va >> 8;
-               fmask_state[0] |= image->fmask.tile_swizzle;
+               fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
                fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
                        S_008F14_DATA_FORMAT(fmask_format) |
                        S_008F14_NUM_FORMAT(num_format);
@@ -946,9 +946,9 @@ si_make_texture_descriptor(struct radv_device *device,
                                fmask_state[7] |= va >> 8;
                        }
                } else {
-                       fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
+                       fmask_state[3] |= S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
                        fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
-                               S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
+                               S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
                        fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
 
                        if (radv_image_is_tc_compat_cmask(image)) {
@@ -1101,41 +1101,15 @@ radv_image_override_offset_stride(struct radv_device *device,
        }
 }
 
-/* The number of samples can be specified independently of the texture. */
-static void
-radv_image_get_fmask_info(struct radv_device *device,
-                         struct radv_image *image,
-                         unsigned nr_samples,
-                         struct radv_fmask_info *out)
-{
-       if (device->physical_device->rad_info.chip_class >= GFX9) {
-               out->alignment = image->planes[0].surface.fmask_alignment;
-               out->size = image->planes[0].surface.fmask_size;
-               out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
-               return;
-       }
-
-       out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
-       out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
-       out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
-       out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
-       out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
-       out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
-       out->alignment = image->planes[0].surface.fmask_alignment;
-       out->size = image->planes[0].surface.fmask_size;
-
-       assert(!out->tile_swizzle || !image->shareable);
-}
-
 static void
 radv_image_alloc_fmask(struct radv_device *device,
                       struct radv_image *image)
 {
-       radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
+       unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
 
-       image->fmask.offset = align64(image->size, image->fmask.alignment);
-       image->size = image->fmask.offset + image->fmask.size;
-       image->alignment = MAX2(image->alignment, image->fmask.alignment);
+       image->fmask_offset = align64(image->size, fmask_alignment);
+       image->size = image->fmask_offset + image->planes[0].surface.fmask_size;
+       image->alignment = MAX2(image->alignment, fmask_alignment);
 }
 
 static void

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index e6e96a103f164d408a451286f8eeae5cccc8e9cd..d9615a280b05cac62a1f361852533a746c3033d8 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1353,7 +1353,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
                 struct radv_image *image,
                 const VkImageSubresourceRange *range, uint32_t value)
 {
-       uint64_t offset = image->offset + image->fmask.offset;
+       uint64_t offset = image->offset + image->fmask_offset;
        uint64_t size;
 
        /* MSAA images do not support mipmap levels. */
@@ -1362,10 +1362,14 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
 
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
                /* TODO: clear layers. */
-               size = image->fmask.size;
+               size = image->planes[0].surface.fmask_size;
        } else {
-               offset += image->fmask.slice_size * range->baseArrayLayer;
-               size = image->fmask.slice_size * radv_get_layerCount(image, range);
+               unsigned fmask_slice_size =
+                       image->planes[0].surface.u.legacy.fmask.slice_size;
+
+
+               offset += fmask_slice_size * range->baseArrayLayer;
+               size = fmask_slice_size * radv_get_layerCount(image, range);
        }
 
        return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 33c2d4b8620b296a49cdfeb10bd7094c1b36be5c..49d3c78db98d09fe62a0db8ae43d245b49f1f408 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1549,18 +1549,6 @@ bool radv_dcc_formats_compatible(VkFormat format1,
                                  VkFormat format2);
 bool radv_device_supports_etc(struct radv_physical_device *physical_device);
 
-struct radv_fmask_info {
-       uint64_t offset;
-       uint64_t size;
-       unsigned alignment;
-       unsigned pitch_in_pixels;
-       unsigned bank_height;
-       unsigned slice_tile_max;
-       unsigned tile_mode_index;
-       unsigned tile_swizzle;
-       uint64_t slice_size;
-};
-
 struct radv_image_plane {
        VkFormat format;
        struct radeon_surf surface;
@@ -1594,8 +1582,8 @@ struct radv_image {
        bool tc_compatible_htile;
        bool tc_compatible_cmask;
 
-       struct radv_fmask_info fmask;
        uint64_t cmask_offset;
+       uint64_t fmask_offset;
        uint64_t clear_value_offset;
        uint64_t fce_pred_offset;
        uint64_t dcc_pred_offset;
@@ -1654,7 +1642,7 @@ radv_image_has_cmask(const struct radv_image *image)
 static inline bool
 radv_image_has_fmask(const struct radv_image *image)
 {
-       return image->fmask.size;
+       return image->planes[0].surface.fmask_size;
 }
 
 /**