Do not rename non LUT cells in abc9

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index e9f35be91ddd22e2f753366bba2154780df35b94..1783b4b1be10f1628d3f5dec78b5e8930ed4fe70 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -522,8 +522,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                std::map<std::string, int> cell_stats;
                for (auto c : mapped_mod->cells())
                {
+                       RTLIL::Cell *cell = nullptr;
                        if (c->type == "$_NOT_") {
-                               RTLIL::Cell *cell = nullptr;
                                RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
                                RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
                                if (!a_bit.wire) {
@@ -582,6 +582,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        }
                        cell_stats[RTLIL::unescape_id(c->type)]++;
 
+                        RTLIL::Cell *existing_cell = nullptr;
                        if (c->type == "$lut") {
                                if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
                                        SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
@@ -590,19 +591,23 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                         if (markgroups) c->attributes["\\abcgroup"] = map_autoidx;
                                        continue;
                                }
+                               cell = module->addCell(remap_name(c->name), c->type);
+                       }
+                       else {
+                               existing_cell = module->cell(c->name);
+                               cell = module->addCell(remap_name(c->name), c->type);
+                               module->swap_names(cell, existing_cell);
                        }
 
-                       RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
                        if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
-                        RTLIL::Cell *existing_cell = module->cell(c->name);
-                        if (existing_cell) {
-                                cell->parameters = existing_cell->parameters;
-                                cell->attributes = existing_cell->attributes;
-                        }
-                        else {
-                                cell->parameters = c->parameters;
-                                cell->attributes = c->attributes;
-                        }
+                       if (existing_cell) {
+                               cell->parameters = existing_cell->parameters;
+                               cell->attributes = existing_cell->attributes;
+                       }
+                       else {
+                               cell->parameters = c->parameters;
+                               cell->attributes = c->attributes;
+                       }
                        for (auto &conn : c->connections()) {
                                RTLIL::SigSpec newsig;
                                for (auto c : conn.second.chunks()) {