LLVMValueRef *locals;
};
-struct nir_to_llvm_context {
+struct radv_shader_context {
struct ac_llvm_context ac;
const struct ac_nir_compiler_options *options;
struct ac_shader_variant_info *shader_info;
uint64_t tcs_outputs_read;
};
-static inline struct nir_to_llvm_context *
-nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
+static inline struct radv_shader_context *
+radv_shader_context_from_abi(struct ac_shader_abi *abi)
{
- struct nir_to_llvm_context *ctx = NULL;
+ struct radv_shader_context *ctx = NULL;
return container_of(abi, ctx, abi);
}
return value;
}
-static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
+static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
{
switch (ctx->stage) {
case MESA_SHADER_TESS_CTRL:
* All three shaders VS(LS), TCS, TES share the same LDS space.
*/
static LLVMValueRef
-get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
+get_tcs_in_patch_stride(struct radv_shader_context *ctx)
{
if (ctx->stage == MESA_SHADER_VERTEX)
return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
}
static LLVMValueRef
-get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
+get_tcs_out_patch_stride(struct radv_shader_context *ctx)
{
return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
}
static LLVMValueRef
-get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
+get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
{
return LLVMBuildMul(ctx->ac.builder,
unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
}
static LLVMValueRef
-get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
+get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
{
return LLVMBuildMul(ctx->ac.builder,
unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
}
static LLVMValueRef
-get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
+get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
{
LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
}
static LLVMValueRef
-get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
+get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
{
LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
}
static LLVMValueRef
-get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
+get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
{
LLVMValueRef patch0_patch_data_offset =
get_tcs_out_patch0_patch_data_offset(ctx);
}
static void
-set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
+set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
uint8_t num_sgprs)
{
struct ac_userdata_info *ud_info =
}
static void
-set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
+set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
uint32_t indirect_offset)
{
struct ac_userdata_info *ud_info =
bool indirect_all_descriptor_sets;
};
-static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
+static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
gl_shader_stage stage)
{
switch (stage) {
}
static uint8_t
-count_vs_user_sgprs(struct nir_to_llvm_context *ctx)
+count_vs_user_sgprs(struct radv_shader_context *ctx)
{
uint8_t count = 0;
return count;
}
-static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
+static void allocate_user_sgprs(struct radv_shader_context *ctx,
gl_shader_stage stage,
bool has_previous_stage,
gl_shader_stage previous_stage,
}
static void
-declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
+declare_global_input_sgprs(struct radv_shader_context *ctx,
gl_shader_stage stage,
bool has_previous_stage,
gl_shader_stage previous_stage,
}
static void
-declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
+declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
gl_shader_stage stage,
bool has_previous_stage,
gl_shader_stage previous_stage,
}
static void
-declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
+declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
{
add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
if (!ctx->is_gs_copy_shader) {
}
static void
-declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
+declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
{
add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
}
static void
-set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
+set_global_input_locs(struct radv_shader_context *ctx, gl_shader_stage stage,
bool has_previous_stage, gl_shader_stage previous_stage,
const struct user_sgpr_info *user_sgpr_info,
LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
}
static void
-set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
+set_vs_specific_input_locs(struct radv_shader_context *ctx,
gl_shader_stage stage, bool has_previous_stage,
gl_shader_stage previous_stage,
uint8_t *user_sgpr_idx)
}
}
-static void create_function(struct nir_to_llvm_context *ctx,
+static void create_function(struct radv_shader_context *ctx,
gl_shader_stage stage,
bool has_previous_stage,
gl_shader_stage previous_stage)
radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
unsigned desc_set, unsigned binding)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
*
* Note that every attribute has 4 components.
*/
-static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
+static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
LLVMValueRef vertex_index,
LLVMValueRef param_index)
{
return base_addr;
}
-static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
+static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
unsigned param,
unsigned const_index,
bool is_compact,
}
static void
-mark_tess_output(struct nir_to_llvm_context *ctx,
+mark_tess_output(struct radv_shader_context *ctx,
bool is_patch, uint32_t param)
{
}
static LLVMValueRef
-get_dw_address(struct nir_to_llvm_context *ctx,
+get_dw_address(struct radv_shader_context *ctx,
LLVMValueRef dw_addr,
unsigned param,
unsigned const_index,
bool is_compact,
bool load_input)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef dw_addr, stride;
LLVMValueRef value[4], result;
unsigned param = shader_io_get_unique_index(location);
bool is_compact,
unsigned writemask)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef dw_addr;
LLVMValueRef stride = NULL;
LLVMValueRef buf_addr = NULL;
bool is_compact,
bool load_input)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef buf_addr;
LLVMValueRef result;
unsigned param = shader_io_get_unique_index(location);
unsigned const_index,
LLVMTypeRef type)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef vtx_offset;
unsigned param, vtx_offset_param;
LLVMValueRef value[4], result;
static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
enum glsl_interp_mode interp, unsigned location)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
switch (interp) {
case INTERP_MODE_FLAT:
static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
LLVMValueRef sample_id)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef result;
LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
ctx->options->key.fs.log2_num_samples :
ctx->options->key.fs.log2_ps_iter_samples;
LLVMValueRef gs_next_vertex;
LLVMValueRef can_emit;
int idx;
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
assert(stream == 0);
static void
visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
}
static LLVMValueRef
load_tess_coord(struct ac_shader_abi *abi)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef coord[4] = {
ctx->tes_u,
static LLVMValueRef
load_patch_vertices_in(struct ac_shader_abi *abi)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
}
static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
LLVMValueRef buffer_ptr, bool write)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef result;
LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef result;
LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
enum ac_descriptor_type desc_type,
bool image, bool write)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
}
static void
-handle_vs_input_decl(struct nir_to_llvm_context *ctx,
+handle_vs_input_decl(struct radv_shader_context *ctx,
struct nir_variable *variable)
{
LLVMValueRef t_list_ptr = ctx->vertex_buffers;
}
}
-static void interp_fs_input(struct nir_to_llvm_context *ctx,
+static void interp_fs_input(struct radv_shader_context *ctx,
unsigned attr,
LLVMValueRef interp_param,
LLVMValueRef prim_mask,
}
static void
-handle_fs_input_decl(struct nir_to_llvm_context *ctx,
+handle_fs_input_decl(struct radv_shader_context *ctx,
struct nir_variable *variable)
{
int idx = variable->data.location;
}
static void
-handle_vs_inputs(struct nir_to_llvm_context *ctx,
+handle_vs_inputs(struct radv_shader_context *ctx,
struct nir_shader *nir) {
nir_foreach_variable(variable, &nir->inputs)
handle_vs_input_decl(ctx, variable);
}
static void
-prepare_interp_optimize(struct nir_to_llvm_context *ctx,
+prepare_interp_optimize(struct radv_shader_context *ctx,
struct nir_shader *nir)
{
if (!ctx->options->key.fs.multisample)
}
static void
-handle_fs_inputs(struct nir_to_llvm_context *ctx,
+handle_fs_inputs(struct radv_shader_context *ctx,
struct nir_shader *nir)
{
prepare_interp_optimize(ctx, nir);
}
static void
-scan_shader_output_decl(struct nir_to_llvm_context *ctx,
+scan_shader_output_decl(struct radv_shader_context *ctx,
struct nir_variable *variable,
struct nir_shader *shader,
gl_shader_stage stage)
/* Initialize arguments for the shader export intrinsic */
static void
-si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
+si_llvm_init_export_args(struct radv_shader_context *ctx,
LLVMValueRef *values,
unsigned target,
struct ac_export_args *args)
}
static void
-radv_export_param(struct nir_to_llvm_context *ctx, unsigned index,
+radv_export_param(struct radv_shader_context *ctx, unsigned index,
LLVMValueRef *values)
{
struct ac_export_args args;
}
static LLVMValueRef
-radv_load_output(struct nir_to_llvm_context *ctx, unsigned index, unsigned chan)
+radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
{
LLVMValueRef output =
ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
}
static void
-handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
+handle_vs_outputs_post(struct radv_shader_context *ctx,
bool export_prim_id,
struct ac_vs_output_info *outinfo)
{
}
static void
-handle_es_outputs_post(struct nir_to_llvm_context *ctx,
+handle_es_outputs_post(struct radv_shader_context *ctx,
struct ac_es_output_info *outinfo)
{
int j;
}
static void
-handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
+handle_ls_outputs_post(struct radv_shader_context *ctx)
{
LLVMValueRef vertex_id = ctx->rel_auto_id;
LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
struct ac_build_if_state
{
- struct nir_to_llvm_context *ctx;
+ struct radv_shader_context *ctx;
LLVMValueRef condition;
LLVMBasicBlockRef entry_block;
LLVMBasicBlockRef true_block;
};
static LLVMBasicBlockRef
-ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
+ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
{
LLVMBasicBlockRef current_block;
LLVMBasicBlockRef next_block;
static void
ac_nir_build_if(struct ac_build_if_state *ifthen,
- struct nir_to_llvm_context *ctx,
+ struct radv_shader_context *ctx,
LLVMValueRef condition)
{
LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
}
static void
-write_tess_factors(struct nir_to_llvm_context *ctx)
+write_tess_factors(struct radv_shader_context *ctx)
{
unsigned stride, outer_comps, inner_comps;
struct ac_build_if_state if_ctx, inner_if_ctx;
}
static void
-handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
+handle_tcs_outputs_post(struct radv_shader_context *ctx)
{
write_tess_factors(ctx);
}
static bool
-si_export_mrt_color(struct nir_to_llvm_context *ctx,
+si_export_mrt_color(struct radv_shader_context *ctx,
LLVMValueRef *color, unsigned index, bool is_last,
struct ac_export_args *args)
{
}
static void
-radv_export_mrt_z(struct nir_to_llvm_context *ctx,
+radv_export_mrt_z(struct radv_shader_context *ctx,
LLVMValueRef depth, LLVMValueRef stencil,
LLVMValueRef samplemask)
{
}
static void
-handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
+handle_fs_outputs_post(struct radv_shader_context *ctx)
{
unsigned index = 0;
LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
}
static void
-emit_gs_epilogue(struct nir_to_llvm_context *ctx)
+emit_gs_epilogue(struct radv_shader_context *ctx)
{
ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
}
handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
LLVMValueRef *addrs)
{
- struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+ struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
switch (ctx->stage) {
case MESA_SHADER_VERTEX:
}
}
-static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
+static void ac_llvm_finalize_module(struct radv_shader_context *ctx)
{
LLVMPassManagerRef passmgr;
/* Create the pass manager */
}
static void
-ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
+ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
{
struct ac_vs_output_info *outinfo;
}
static void
-ac_setup_rings(struct nir_to_llvm_context *ctx)
+ac_setup_rings(struct radv_shader_context *ctx)
{
if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
(ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
}
/* Fixup the HW not emitting the TCS regs if there are no HS threads. */
-static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
+static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
{
LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
LLVMConstInt(ctx->ac.i32, 8, false),
ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
}
-static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
+static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
{
for(int i = 5; i >= 0; --i) {
ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
struct ac_shader_variant_info *shader_info,
const struct ac_nir_compiler_options *options)
{
- struct nir_to_llvm_context ctx = {0};
+ struct radv_shader_context ctx = {0};
unsigned i;
ctx.options = options;
ctx.shader_info = shader_info;
}
static void
-ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
+ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
{
LLVMValueRef vtx_offset =
LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
const struct ac_nir_compiler_options *options,
bool dump_shader)
{
- struct nir_to_llvm_context ctx = {0};
+ struct radv_shader_context ctx = {0};
ctx.context = LLVMContextCreate();
ctx.options = options;
ctx.shader_info = shader_info;
projects / mesa.git / commitdiff