whitespace, add MPW pricing

diff --git a/resources.mdwn b/resources.mdwn
index f78561c57c3918740786a9820fced6e9f4cd32c2..a94af724643e3462774e61b14f5524e4a0a150d7 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -192,11 +192,13 @@ test. It's still in development as far as I can tell.
 IEEE 754 has no official tests for floating-point but there are
 well-known third party tools to check such as John Hauser's TestFloat.
 
-There is also his SoftFloat library, which is a software emulation library for IEEE 754.
+There is also his SoftFloat library, which is a software emulation
+library for IEEE 754.
 
 * <http://www.jhauser.us/arithmetic/>
 
-Jacob is also working on an IEEE 754 software emulation library written in Rust which also has Python bindings:
+Jacob is also working on an IEEE 754 software emulation library written
+in Rust which also has Python bindings:
 
 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
 * Crate: <https://crates.io/crates/simple-soft-float>
@@ -231,16 +233,13 @@ thousands or millions of silicon.
 
 Some learning resources I found in the community:
 
-* ZipCPU: <http://zipcpu.com/>
-
-ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: <http://zipcpu.com/tutorial/>
-
-
-* Western Digital's SweRV CPU blog (I recommend looking at all their posts): <https://tomverbeure.github.io/>
-
-<https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
-
-<https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
+* ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
+  tutorial for beginners and many exercises/quizzes/slides:
+  <http://zipcpu.com/tutorial/>
+* Western Digital's SweRV CPU blog (I recommend looking at all their
+  posts): <https://tomverbeure.github.io/>
+* <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
+* <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
 
 ## Automation
 
@@ -256,34 +255,32 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
 
 * <https://danluu.com/branch-prediction/>
 
-
 # Python RTL Tools
+
 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
   An SOC builder written in Python Migen DSL. Allows you to generate functional
   RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
   and parameterizeable CSRs.
 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
-
 * There is a great guy, Robert Baruch, who has a good
   [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
   He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
   [the code](https://github.com/RobertBaruch/n6800) and
   [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
   online.
-
 * [Minerva](https://github.com/lambdaconcept/minerva)
   An SOC written in Python nMigen DSL
-
 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
 
+# Other
 
-## Other
 * <https://wiki.f-si.org/index.php/FSiC2019>
 
 # Real/Physical Projects
+
 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
 * <https://chips4makers.io/blog/>
 * <https://hackaday.io/project/7817-zynqberry>
@@ -293,24 +290,30 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
 * <https://mshahrad.github.io/openpiton-asplos16.html>
 
+# ASIC tape-out pricing
+
+* <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
+
 # Funding
+
 * <https://toyota-ai.ventures/>
 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
 
 # Good Programming/Design Practices
+
 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
 
-
-
 * <https://youtu.be/o5Ihqg72T3c>
 * <http://flopoco.gforge.inria.fr/>
-* Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
+* Fundamentals of Modern VLSI Devices
+  <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
+
+# 12 skills summary
 
-# Broken Links
-* <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
+* <https://www.crnhq.org/cr-kit/>
 
 # Analog Simulation
 
@@ -319,7 +322,7 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
 * <http://ngspice.sourceforge.net/adms.html>
 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
 
-# Libre-RISC-V Standards
+# Libre-SOC Standards
 
 This list auto-generated from a page tag "standards":
 
@@ -327,9 +330,7 @@ This list auto-generated from a page tag "standards":
 
 # Server setup
 
-[[resources/server-setup/web-server]]
-
-[[resources/server-setup/git-mirroring]]
-
-[[resources/server-setup/nagios-monitoring]]
+* [[resources/server-setup/web-server]]
+* [[resources/server-setup/git-mirroring]]
+* [[resources/server-setup/nagios-monitoring]]