(arm_it): Use ARM_IT_MAX_OPERANDS.
(neon_select_shape): Ensure we have matched all operands.
* gas/testsuite/gas/arm/neon-suffix-bad.l: Add testcase.
* gas/testsuite/gas/arm/neon-suffix-bad.s: Likewise.
+2011-11-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * config/tc-arm.c (ARM_IT_MAX_OPERANDS): New define.
+ (arm_it): Use ARM_IT_MAX_OPERANDS.
+ (neon_select_shape): Ensure we have matched all operands.
+
2011-11-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (parse_neon_mov): Update which_operand
IT_INSN /* The IT insn has been parsed. */
};
+/* The maximum number of operands we need. */
+#define ARM_IT_MAX_OPERANDS 6
+
struct arm_it
{
const char * error;
unsigned negative : 1; /* Index register was negated. */
unsigned shifted : 1; /* Shift applied to operation. */
unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
- } operands[6];
+ } operands[ARM_IT_MAX_OPERANDS];
};
static struct arm_it inst;
if (!matches)
break;
}
- if (matches)
+ if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
+ /* We've matched all the entries in the shape table, and we don't
+ have any left over operands which have not been matched. */
break;
}
+2011-11-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * gas/arm/neon-suffix-bad.l: Add testcase.
+ * gas/arm/neon-suffix-bad.s: Likewise.
+
2011-12-05 Richard Earnshaw <rearnsha@arm.com>
* gas/arm/attr-any-armv4t.d: New test.
[^:]*:3: Error: invalid neon suffix for non neon instruction
[^:]*:4: Error: invalid neon suffix for non neon instruction
[^:]*:5: Error: invalid neon suffix for non neon instruction
-[^:]*:8: Error: invalid neon suffix for non neon instruction
+[^:]*:6: Error: invalid instruction shape -- `vcvt.f64.s32 d0,s0,#11'
[^:]*:9: Error: invalid neon suffix for non neon instruction
[^:]*:10: Error: invalid neon suffix for non neon instruction
+[^:]*:11: Error: invalid neon suffix for non neon instruction
+[^:]*:12: Error: invalid instruction shape -- `vcvt.f64.s32 d0,s0,#11'
add.f32 r0, r0, r0
faddd.f32 d0, d0, d0
faddd.f64 d0, d0, d0
+vcvt.f64.s32 d0, s0, #11
.thumb
add.f32 r0, r0, r0
faddd.f32 d0, d0, d0
faddd.f64 d0, d0, d0
-
+vcvt.f64.s32 d0, s0, #11