add store and ldq

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 147bec61d166b46ac91d7a8002cf83fde6caed8b..c4d7e87da4f7bed7a6a387c4059b41d5e1d7b89d 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -194,3 +194,11 @@ ldux RT,RA,RB
     RT <- MEM(EA, 8)
     RA <- EA
 
+# Load Quadword
+
+lq RTp,DQ(RA)
+
+    if RA = 0 then b <-  0
+    else           b <-  (RA)
+    EA <- b + EXTS(DQ || 0b0000)
+    RTp <- MEM(EA, 16)

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
new file mode 100644 (file)
index 0000000..9939232
--- /dev/null
+++ b/openpower/isa/fixedstore.mdwn
@@ -0,0 +1,144 @@
+# Store Byte  
+
+stb RS,D(RA)
+
+    if RA = 0 then b <-  0
+    else           b <-  (RA)
+    EA <- b + EXTS(D)
+    MEM(EA, 1) <- (RS)[56:63]
+
+# Store Byte Indexed  
+
+stbx RS,RA,RB
+
+    if RA = 0 then b <- 0
+    else           b <- (RA)
+    EA <- b + (RB)
+    MEM(EA, 1) <- (RS)[56:63]
+
+# Store Byte with Update 
+
+stbu RS,D(RA)
+
+    EA <- (RA) + EXTS(D)
+    MEM(EA, 1) <- (RS)[56:63]
+    RA <- EA
+
+# Store Byte with Update Indexed 
+
+stbux RS,RA,RB
+
+    EA <- (RA) + (RB)
+    MEM(EA, 1) <- (RS)[56:63]
+    RA <- EA
+# Store Halfword 
+
+sth RS,D(RA)
+
+    if RA = 0 then b <-  0
+    else           b <-  (RA)
+    EA <- b + EXTS(D)
+    MEM(EA, 2) <- (RS)[48:63]
+
+# Store Halfword Indexed 
+
+sthx RS,RA,RB
+
+    if RA = 0 then b <- 0
+    else           b <- (RA)
+    EA <- b + (RB)
+    MEM(EA, 2) <- (RS)[48:63]
+
+# Store Halfword with Update
+
+sthu RS,D(RA)
+
+    EA <- (RA) + EXTS(D)
+    MEM(EA, 2) <- (RS)[48:63]
+    RA <- EA
+
+# Store Halfword with Update Indexed 
+ 
+sthux RS,RA,RB
+
+    EA <- (RA) + (RB)
+    MEM(EA, 2) <- (RS)[48:63]
+    RA <- EA
+
+# Store Word
+
+stw RS,D(RA) 
+
+    if RA = 0 then b <-  0
+    else           b <-  (RA)
+    EA <- b + EXTS(D)
+    MEM(EA, 4) <- (RS)[32:63]
+
+# Store Word Indexed 
+
+stwx RS,RA,RB 
+
+    if RA = 0 then b <- 0
+    else           b <- (RA)
+    EA <- b + (RB)
+    MEM(EA, 4) <- (RS)[32:63]
+
+# Store Word with Update 
+
+stwu RS,D(RA)
+
+    EA <- (RA) + EXTS(D)
+    MEM(EA, 4) <- (RS) 32:63
+    RA <- EA
+
+# Store Word with Update Indexed  
+
+stwux RS,RA,RB 
+
+    EA <- (RA) + (RB)
+    MEM(EA, 4) <- (RS) 32:63
+    RA <- EA
+
+# Store Doubleword  
+
+std RS,DS(RA)
+
+    if RA = 0 then b <-  0
+    else           b <-  (RA)
+    EA <- b + EXTS(DS || 0b00)
+    MEM(EA, 8) <- (RS)
+
+# Store Doubleword Indexed 
+
+stdx RS,RA,RB
+
+    if RA = 0 then b <- 0
+    else           b <- (RA)
+    EA <- b + (RB)
+    MEM(EA, 8) <- (RS)
+
+# Store Doubleword with Update 
+
+stdu RS,DS(RA)
+
+EA <- (RA) + EXTS(DS || 0b00)
+MEM(EA, 8) <- (RS)
+RA <- EA
+
+Store Doubleword with Update Indexed 
+
+stdux RS,RA,RB
+
+    EA <- (RA) + (RB)
+    MEM(EA, 8) <- (RS)
+    RA <- EA
+
+# Store Quadword
+
+stq RSp,DS(RA)
+
+    if RA = 0 then b <-  0
+    else           b <-  (RA)
+    EA <- b + EXTS(DS || 0b00)
+    MEM(EA, 16) <- RSp
+