(no commit message)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 82efc4c3fdb290bf038bc140838e369a652ca5bc..68e37fbe283357fd2a0c08c42411591798904672 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -199,6 +199,8 @@ pseudocode:
                     setting_mode = True # back into "setting" mode
             i += 1
 
+<https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/vmsbf_m.h>
+
 ## sifm
 
 The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.