intel/genxml: add missing MI_PREDICATE compare operations

Doesn't save us a great deal of lines but at least they get decoded in
aubinators.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 9ec311d6cc596e38cdce7df638594207e9762243..7043ab8995de7a5321feecc0df7d3c88ad12be6c 100644 (file)
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3047,6 +3047,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 6ab1f9656506756f854c438249ce8ae56be189d5..3af80a6ed3d77b75c443cb1281638d1ab13c2316 100644 (file)
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3042,6 +3042,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 893c12b8af9ea00d96f3c26102588fbb51886b87..3c44575730035bbea855e97357fbaca248a66c65 100644 (file)
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2051,6 +2051,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 009a123ad698fba8bdf2886febb8b322939f41a5..3df7dc2993967ec9ef825041b24c9ea2c2c547f2 100644 (file)
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2462,6 +2462,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index fd19b0c8b335bc8edc0eb02e6345583e8e6b6c8b..4d1488dae62d3bfbf0c6b5550a3e09be12e3587b 100644 (file)
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2690,6 +2690,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 706d398babb2de474bef80751802586684f535c1..3f02e866d0c730cfcfcb56d907ed1e5f209c1f22 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2973,6 +2973,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 2d94d85d141ea542777150653eaec734a1020d00..cec4819ba4a849484208f356b45506ec84a7d7c2 100644 (file)
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3568,7 +3568,6 @@ void genX(CmdDispatchIndirect)(
    }
 
    /* predicate = !predicate; */
-#define COMPARE_FALSE                           1
    anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
       mip.LoadOperation    = LOAD_LOADINV;
       mip.CombineOperation = COMBINE_OR;