*.o
*.d
.*.swp
-.cproject
-.project
-qtcreator.files
-qtcreator.includes
-qtcreator.config
-qtcreator.creator
-qtcreator.creator.user
-Makefile.conf
-abc
-yosys
-yosys-abc
-yosys-config
-yosys-filterlib
-yosys-svgviewer
+/.cproject
+/.project
+/qtcreator.files
+/qtcreator.includes
+/qtcreator.config
+/qtcreator.creator
+/qtcreator.creator.user
+/Makefile.conf
+/abc
+/yosys
+/yosys-abc
+/yosys-config
+/yosys-filterlib
+/yosys-svgviewer
cell_types.insert("$mux");
cell_types.insert("$pmux");
cell_types.insert("$safe_pmux");
+ cell_types.insert("$lut");
}
void setup_internals_mem()
return true;
if (type == "$fsm" && port == "\\CTRL_OUT")
return true;
+ if (type == "$lut" && port == "\\O")
+ return true;
return false;
}
OBJS += passes/abc/abc.o
OBJS += passes/abc/vlparse.o
+OBJS += passes/abc/blifparse.o
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/log.h"
-#include "vlparse.h"
#include <unistd.h>
#include <stdlib.h>
#include <assert.h>
#include <dirent.h>
#include <sstream>
+#include "vlparse.h"
+#include "blifparse.h"
+
struct gate_t
{
int id;
fclose(dot_f);
}
-static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, bool cleanup)
+static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, bool cleanup, int lut_mode)
{
module = current_module;
map_autoidx = RTLIL::autoidx++;
fclose(f);
free(p);
+ if (lut_mode) {
+ if (asprintf(&p, "%s/lutdefs.txt", tempdir_name) < 0) abort();
+ f = fopen(p, "wt");
+ if (f == NULL)
+ log_error("Opening %s for writing failed: %s\n", p, strerror(errno));
+ for (int i = 0; i < lut_mode; i++)
+ fprintf(f, "%d 1.00 1.00\n", i+1);
+ fclose(f);
+ free(p);
+ }
+
char buffer[1024];
+ int buffer_pos = 0;
if (!liberty_file.empty())
- snprintf(buffer, 1024, "%s -c 'read_verilog %s/input.v; read_liberty %s; "
- "map; write_verilog %s/output.v' 2>&1", exe_file.c_str(), tempdir_name, liberty_file.c_str(), tempdir_name);
+ buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
+ "%s -c 'read_verilog %s/input.v; read_liberty %s; map; ",
+ exe_file.c_str(), tempdir_name, liberty_file.c_str());
else
if (!script_file.empty())
- snprintf(buffer, 1024, "%s -c 'read_verilog %s/input.v; source %s; "
- "map; write_verilog %s/output.v' 2>&1", exe_file.c_str(), tempdir_name, script_file.c_str(), tempdir_name);
+ buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
+ "%s -c 'read_verilog %s/input.v; source %s; ",
+ exe_file.c_str(), tempdir_name, script_file.c_str());
+ else
+ if (lut_mode)
+ buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
+ "%s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; if; ",
+ exe_file.c_str(), tempdir_name, tempdir_name);
else
- snprintf(buffer, 1024, "%s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; "
- "map; write_verilog %s/output.v' 2>&1", exe_file.c_str(), tempdir_name, tempdir_name, tempdir_name);
+ buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
+ "%s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; map; ",
+ exe_file.c_str(), tempdir_name, tempdir_name);
+ if (lut_mode)
+ buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_blif %s/output.blif' 2>&1", tempdir_name);
+ else
+ buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_verilog %s/output.v' 2>&1", tempdir_name);
+
errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand
f = popen(buffer, "r");
if (f == NULL)
}
}
- if (asprintf(&p, "%s/output.v", tempdir_name) < 0) abort();
+ if (asprintf(&p, "%s/%s", tempdir_name, lut_mode ? "output.blif" : "output.v") < 0) abort();
f = fopen(p, "rt");
if (f == NULL)
log_error("Can't open ABC output file `%s'.\n", p);
RTLIL::Design *mapped_design = new RTLIL::Design;
frontend_register["verilog"]->execute(f, p, std::vector<std::string>(), mapped_design);
#else
- RTLIL::Design *mapped_design = abc_parse_verilog(f);
+ RTLIL::Design *mapped_design = lut_mode ? abc_parse_blif(f) : abc_parse_verilog(f);
#endif
fclose(f);
free(p);
}
std::map<std::string, int> cell_stats;
- if (liberty_file.empty() && script_file.empty())
+ if (liberty_file.empty() && script_file.empty() && !lut_mode)
{
for (auto &it : mapped_mod->cells) {
RTLIL::Cell *c = it.second;
}
RTLIL::Cell *cell = new RTLIL::Cell;
cell->type = c->type;
+ cell->parameters = c->parameters;
cell->name = remap_name(c->name);
- for (auto &conn : c->connections)
- cell->connections[conn.first] = RTLIL::SigSpec(module->wires[remap_name(conn.second.chunks[0].wire->name)]);
+ for (auto &conn : c->connections) {
+ RTLIL::SigSpec newsig;
+ for (auto &c : conn.second.chunks) {
+ if (c.width == 0)
+ continue;
+ assert(c.width == 1);
+ newsig.append(module->wires[remap_name(c.wire->name)]);
+ }
+ cell->connections[conn.first] = newsig;
+ }
module->cells[cell->name] = cell;
design->select(module, cell);
}
log(" but keeps using yosys's internal gate library. This option is ignored if\n");
log(" the -script option is also used.\n");
log("\n");
+ log(" -lut <width>\n");
+ log(" generate netlist using luts of (max) the specified width.\n");
+ log("\n");
log(" -nocleanup\n");
log(" when this option is used, the temporary files created by this pass\n");
log(" are not removed. this is useful for debugging.\n");
std::string exe_file = rewrite_yosys_exe("yosys-abc");
std::string script_file, liberty_file;
bool cleanup = true;
+ int lut_mode = 0;
size_t argidx;
char *pwd = get_current_dir_name();
liberty_file = std::string(pwd) + "/" + liberty_file;
continue;
}
+ if (arg == "-lut" && argidx+1 < args.size() && lut_mode == 0) {
+ lut_mode = atoi(args[++argidx].c_str());
+ continue;
+ }
if (arg == "-nocleanup") {
cleanup = false;
continue;
if (mod_it.second->processes.size() > 0)
log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
else
- abc_module(design, mod_it.second, script_file, exe_file, liberty_file, cleanup);
+ abc_module(design, mod_it.second, script_file, exe_file, liberty_file, cleanup, lut_mode);
}
assign_map.clear();
--- /dev/null
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "blifparse.h"
+#include "kernel/log.h"
+#include <stdio.h>
+#include <string.h>
+
+RTLIL::Design *abc_parse_blif(FILE *f)
+{
+ RTLIL::Design *design = new RTLIL::Design;
+ RTLIL::Module *module = new RTLIL::Module;
+
+ RTLIL::Const *lutptr = NULL;
+ RTLIL::State lut_default_state = RTLIL::State::Sx;
+
+ int port_count = 0;
+ module->name = "\\logic";
+ design->modules[module->name] = module;
+
+ char buffer[4096];
+ int line_count = 0;
+
+ while (1)
+ {
+ buffer[0] = 0;
+
+ while (1)
+ {
+ int buffer_len = strlen(buffer);
+ while (buffer_len > 0 && (buffer[buffer_len-1] == ' ' || buffer[buffer_len-1] == '\t' ||
+ buffer[buffer_len-1] == '\r' || buffer[buffer_len-1] == '\n'))
+ buffer[--buffer_len] = 0;
+
+ if (buffer_len == 0 || buffer[buffer_len-1] == '\\') {
+ if (buffer[buffer_len-1] == '\\')
+ buffer[--buffer_len] = 0;
+ line_count++;
+ if (fgets(buffer+buffer_len, 4096-buffer_len, f) == NULL)
+ goto error;
+ } else
+ break;
+ }
+
+ if (buffer[0] == '#')
+ continue;
+
+ if (buffer[0] == '.')
+ {
+ if (lutptr) {
+ for (auto &bit : lutptr->bits)
+ if (bit == RTLIL::State::Sx)
+ bit = lut_default_state;
+ lutptr = NULL;
+ lut_default_state = RTLIL::State::Sx;
+ }
+
+ char *cmd = strtok(buffer, " \t\r\n");
+
+ if (!strcmp(cmd, ".model"))
+ continue;
+
+ if (!strcmp(cmd, ".end"))
+ return design;
+
+ if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) {
+ char *p;
+ while ((p = strtok(NULL, " \t\r\n")) != NULL) {
+ RTLIL::Wire *wire = new RTLIL::Wire;
+ wire->name = stringf("\\%s", p);
+ wire->port_id = ++port_count;
+ if (!strcmp(cmd, ".inputs"))
+ wire->port_input = true;
+ else
+ wire->port_output = true;
+ module->add(wire);
+ }
+ continue;
+ }
+
+ if (!strcmp(cmd, ".names"))
+ {
+ char *p;
+ RTLIL::SigSpec input_sig, output_sig;
+ while ((p = strtok(NULL, " \t\r\n")) != NULL) {
+ RTLIL::Wire *wire;
+ if (module->wires.count(stringf("\\%s", p)) > 0) {
+ wire = module->wires.at(stringf("\\%s", p));
+ } else {
+ wire = new RTLIL::Wire;
+ wire->name = stringf("\\%s", p);
+ module->add(wire);
+ }
+ input_sig.append(wire);
+ }
+ output_sig = input_sig.extract(input_sig.width-1, 1);
+ input_sig = input_sig.extract(0, input_sig.width-1);
+
+ input_sig.optimize();
+ output_sig.optimize();
+
+ RTLIL::Cell *cell = new RTLIL::Cell;
+ cell->name = NEW_ID;
+ cell->type = "$lut";
+ cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.width);
+ cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.width);
+ cell->connections["\\I"] = input_sig;
+ cell->connections["\\O"] = output_sig;
+ lutptr = &cell->parameters.at("\\LUT");
+ lut_default_state = RTLIL::State::Sx;
+ module->add(cell);
+ continue;
+ }
+
+ goto error;
+ }
+
+ if (lutptr == NULL)
+ goto error;
+
+ char *input = strtok(buffer, " \t\r\n");
+ char *output = strtok(NULL, " \t\r\n");
+
+ if (input == NULL || output == NULL || (strcmp(output, "0") && strcmp(output, "1")))
+ goto error;
+
+ int input_len = strlen(input);
+ if (input_len > 8)
+ goto error;
+
+ for (int i = 0; i < (1 << input_len); i++) {
+ for (int j = 0; j < input_len; j++) {
+ char c1 = input[j];
+ if (c1 != '-') {
+ char c2 = (i & (1 << j)) != 0 ? '1' : '0';
+ if (c1 != c2)
+ goto try_next_value;
+ }
+ }
+ lutptr->bits.at(i) = !strcmp(output, "0") ? RTLIL::State::S0 : RTLIL::State::S1;
+ try_next_value:;
+ }
+
+ lut_default_state = !strcmp(output, "0") ? RTLIL::State::S1 : RTLIL::State::S0;
+ }
+
+error:
+ log_error("Syntax error in line %d!\n", line_count);
+ // delete design;
+ // return NULL;
+}
+
--- /dev/null
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef ABC_BLIFPARSE
+#define ABC_BLIFPARSE
+
+#include "kernel/rtlil.h"
+
+extern RTLIL::Design *abc_parse_blif(FILE *f);
+
+#endif
+
// --------------------------------------------------------
+module \$lut (I, O);
+
+parameter WIDTH = 0;
+parameter LUT = 0;
+
+input [WIDTH-1:0] I;
+output reg O;
+
+wire lut0_out, lut1_out;
+
+generate
+ if (WIDTH <= 1) begin:simple
+ assign {lut1_out, lut0_out} = LUT;
+ end else begin:complex
+ \$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .I(I[WIDTH-2:0]), .O(lut0_out) );
+ \$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .I(I[WIDTH-2:0]), .O(lut1_out) );
+ end
+endgenerate
+
+always @*
+ casez ({I[WIDTH-1], lut0_out, lut1_out})
+ 3'b?11: O = 1'b1;
+ 3'b?00: O = 1'b0;
+ 3'b0??: O = lut0_out;
+ 3'b1??: O = lut1_out;
+ default: O = 1'bx;
+ endcase
+
+endmodule
+
+// --------------------------------------------------------
+
module \$dff (CLK, D, Q);
parameter WIDTH = 0;
projects / yosys.git / commitdiff