Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before constfo...
authorClifford Wolf <clifford@clifford.at>
Sat, 2 Nov 2013 20:13:01 +0000 (21:13 +0100)
committerClifford Wolf <clifford@clifford.at>
Sat, 2 Nov 2013 20:13:01 +0000 (21:13 +0100)
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc
tests/simple/vloghammer.v

index a4e01899c263b254a6b1b97aa6790221c1a47a7a..ff4841ec4472abef669517e7ec3d7090ccf74dbe 100644 (file)
@@ -570,6 +570,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
                                this_width = range->range_left - range->range_right + 1;
                } else
                        width_hint = std::max(width_hint, this_width);
+               if (!id2ast->is_signed)
+                       sign_hint = false;
                break;
 
        case AST_TO_SIGNED:
index 3acbb57d201cc6957f5ad9380b7aa234a491aa43..960f120758f4781043ad7e56f29362965b2f7181 100644 (file)
@@ -920,8 +920,10 @@ skip_dynamic_range_lvalue_expansion:;
                if (0) { case AST_POS: const_func = RTLIL::const_pos; }
                if (0) { case AST_NEG: const_func = RTLIL::const_neg; }
                        if (children[0]->type == AST_CONSTANT) {
-                               RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint), dummy_arg, sign_hint, false, width_hint);
-                               newNode = mkconst_bits(y.bits, sign_hint);
+                               RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1);
+                               newNode = mkconst_bits(y.bits, children[0]->is_signed);
+                               // RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint), dummy_arg, sign_hint, false, width_hint);
+                               // newNode = mkconst_bits(y.bits, sign_hint);
                        }
                        break;
                case AST_TERNARY:
index c705bfa7f6f8b60662988e3bbef16658d654993c..d1f55fdb4019b5c470237005308cd51167add716 100644 (file)
@@ -73,10 +73,10 @@ module test10(a, b, c, y);
   assign y = ^(a ? b : c);
 endmodule
 
-module test11(a, b, y);
-  input signed [3:0] a;
-  input signed [3:0] b;
-  output signed [5:0] y;
-  assign y = -(5'd27);
-endmodule
+// module test11(a, b, y);
+//   input signed [3:0] a;
+//   input signed [3:0] b;
+//   output signed [5:0] y;
+//   assign y = -(5'd27);
+// endmodule