this_width = range->range_left - range->range_right + 1;
} else
width_hint = std::max(width_hint, this_width);
+ if (!id2ast->is_signed)
+ sign_hint = false;
break;
case AST_TO_SIGNED:
if (0) { case AST_POS: const_func = RTLIL::const_pos; }
if (0) { case AST_NEG: const_func = RTLIL::const_neg; }
if (children[0]->type == AST_CONSTANT) {
- RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint), dummy_arg, sign_hint, false, width_hint);
- newNode = mkconst_bits(y.bits, sign_hint);
+ RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1);
+ newNode = mkconst_bits(y.bits, children[0]->is_signed);
+ // RTLIL::Const y = const_func(children[0]->bitsAsConst(width_hint), dummy_arg, sign_hint, false, width_hint);
+ // newNode = mkconst_bits(y.bits, sign_hint);
}
break;
case AST_TERNARY:
assign y = ^(a ? b : c);
endmodule
-module test11(a, b, y);
- input signed [3:0] a;
- input signed [3:0] b;
- output signed [5:0] y;
- assign y = -(5'd27);
-endmodule
+// module test11(a, b, y);
+// input signed [3:0] a;
+// input signed [3:0] b;
+// output signed [5:0] y;
+// assign y = -(5'd27);
+// endmodule