+2003-06-10 Alan Modra <amodra@bigpond.net.au>
+ Gary Hade <garyhade@us.ibm.com>
+
+ * elf64-ppc.c (ppc64_elf_relocate_section <*_DS>): Special case lq.
+
2003-06-10 Richard Sandiford <rsandifo@redhat.com>
* archures.c (bfd_mach_h8300sxn): New architecture.
* elf32-v850.c (v850_elf_howto_t): Rename R_V850_32to
R_V850_ABS32. Add entry for R_V850_REL32.
- (v850_elf_reloc_map): Likewise.
- (v850_elf_check_relocs): Likewise.
- (v850_elf_perform_relocation): Likewise.
- (v850_elf_final_link_relocate): Likewise. Include computation
+ (v850_elf_reloc_map): Likewise.
+ (v850_elf_check_relocs): Likewise.
+ (v850_elf_perform_relocation): Likewise.
+ (v850_elf_final_link_relocate): Likewise. Include computation
to make R_V850_REl32 pc-relative.
-
+
2003-06-03 Kaz Kojima <kkojima@rr.iij4u.or.jp>
* elf32-sh.c (sh_elf_size_dynamic_sections): Create .interp section
(allocate_dynrelocs): For undef weak syms with non-default
visibility, a) don't allocate plt entries, b) don't allocate
.got relocs, c) discard dyn rel space
- (sh_elf_relocate_section): d) don't generate .got relocs, e)
- don't generate dynamic relocs.
+ (sh_elf_relocate_section): d) don't generate .got relocs, e)
+ don't generate dynamic relocs.
(sh_elf_copy_indirect_symbol): Don't copy ELF_LINK_NON_GOT_REF
for weakdefs when symbol already adjusted.
bfd_vma relocation;
bfd_boolean unresolved_reloc;
bfd_boolean warned;
- long insn;
+ long insn, mask;
struct ppc_stub_hash_entry *stub_entry;
bfd_vma max_br_offset;
bfd_vma from;
case R_PPC64_TPREL16_LO_DS:
case R_PPC64_DTPREL16_DS:
case R_PPC64_DTPREL16_LO_DS:
- if (((relocation + addend) & 3) != 0)
+ insn = bfd_get_32 (input_bfd, contents + (rel->r_offset & ~3));
+ mask = 3;
+ /* If this reloc is against an lq insn, then the value must be
+ a multiple of 16. This is somewhat of a hack, but the
+ "correct" way to do this by defining _DQ forms of all the
+ _DS relocs bloats all reloc switches in this file. It
+ doesn't seem to make much sense to use any of these relocs
+ in data, so testing the insn should be safe. */
+ if ((insn & (0x3f << 26)) == (56 << 26))
+ mask = 15;
+ if (((relocation + addend) & mask) != 0)
{
(*_bfd_error_handler)
- (_("%s: error: relocation %s not a multiple of 4"),
+ (_("%s: error: relocation %s not a multiple of %d"),
bfd_archive_filename (input_bfd),
- ppc64_elf_howto_table[(int) r_type]->name);
+ ppc64_elf_howto_table[(int) r_type]->name,
+ mask + 1);
bfd_set_error (bfd_error_bad_value);
ret = FALSE;
continue;
+2003-06-10 Alan Modra <amodra@bigpond.net.au>
+ Gary Hade <garyhade@us.ibm.com>
+
+ * config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_DQ.
+ (md_apply_fix3): Special case lq insn.
+
2003-06-10 Richard Sandiford <rsandifo@redhat.com>
* config/tc-h8300.c (get_rtsl_operands): Accept unbracketed register
2003-06-03 Nick Clifton <nickc@redhat.com>
* tc-v850.c (tc-gen_reloc): Translate BFD_RELOC_32 into
- BFD_RELOC_32_PCREL if the reloc is pc-relative. Do this
- before calling bfd_reloc_type_lookup.
-
+ BFD_RELOC_32_PCREL if the reloc is pc-relative. Do this
+ before calling bfd_reloc_type_lookup.
+
2003-06-02 Alan Modra <amodra@bigpond.net.au>
* read.c (emit_expr): Set dot_value.
}
if (ppc_obj64
- && (operand->flags & PPC_OPERAND_DS) != 0)
+ && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
{
switch (reloc)
{
abort ();
{
unsigned char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
- unsigned long val;
+ long val, mask;
if (target_big_endian)
- val = bfd_getb16 (where);
+ val = bfd_getb32 (where - 2);
else
- val = bfd_getl16 (where);
- val |= (value & 0xfffc);
+ val = bfd_getl32 (where);
+ mask = 0xfffc;
+ /* lq insns reserve the four lsbs. */
+ if ((ppc_cpu & PPC_OPCODE_POWER4) != 0
+ && (val & (0x3f << 26)) == (56 << 26))
+ mask = 0xfff0;
+ val |= value & mask;
if (target_big_endian)
bfd_putb16 ((bfd_vma) val, where);
else
+2003-06-10 Gary Hade <garyhade@us.ibm.com>
+
+ * gas/ppc/test2elf64.{s,d}: New test.
+ * gas/ppc/ppc.exp: Run new test.
+
2003-06-10 Richard Sandiford <rsandifo@redhat.com>
* gas/h8300/h8sx_mov_imm.[sd]: New test.
run_dump_test "astest64"
run_dump_test "astest2_64"
run_dump_test "test1elf64"
+ run_dump_test "test2elf64"
} elseif { [istarget powerpc*-*aix*] } then {
run_dump_test "test1xcoff32"
} elseif { [istarget powerpc*-*-*bsd*] \
--- /dev/null
+#objdump: -Drx -Mpower4
+#as: -mpower4
+#name: PowerPC Test 2, 64 bit elf, power4 instructions
+
+.*: +file format elf64-powerpc
+.*
+architecture: powerpc:common64, flags 0x0+11:
+HAS_RELOC, HAS_SYMS
+start address 0x0+
+
+Sections:
+Idx Name +Size +VMA +LMA +File off +Algn
+ +0 \.text +0+68 +0+ +0+ +.*
+ +CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+ +1 \.data +0+10 +0+ +0+ +.*
+ +CONTENTS, ALLOC, LOAD, DATA
+ +2 \.bss +0+ +0+ +0+ +.*
+ +ALLOC
+ +3 \.toc +0+30 +0+ +0+ +.*
+ +CONTENTS, ALLOC, LOAD, RELOC, DATA
+SYMBOL TABLE:
+0+ l +d +\.text 0+
+0+ l +d +\.data 0+
+0+ l +d +\.bss 0+
+0+ l +\.data 0+ dsym0
+0+8 l +\.data 0+ dsym1
+0+ l +d +\.toc 0+
+0+8 l +\.data 0+ usym0
+0+10 l +\.data 0+ usym1
+0+ +\*UND\* 0+ esym0
+0+ +\*UND\* 0+ esym1
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ +0: e0 83 00 00 lq r4,0\(r3\)
+ 2: R_PPC64_ADDR16_LO_DS dsym0
+ +4: e0 83 00 00 lq r4,0\(r3\)
+ 6: R_PPC64_ADDR16_LO_DS dsym1
+ +8: e0 83 00 00 lq r4,0\(r3\)
+ a: R_PPC64_ADDR16_LO_DS usym0
+ +c: e0 83 00 00 lq r4,0\(r3\)
+ e: R_PPC64_ADDR16_LO_DS usym1
+ +10: e0 83 00 00 lq r4,0\(r3\)
+ 12: R_PPC64_ADDR16_LO_DS esym0
+ +14: e0 83 00 00 lq r4,0\(r3\)
+ 16: R_PPC64_ADDR16_LO_DS esym1
+ +18: e0 82 00 00 lq r4,0\(r2\)
+ 1a: R_PPC64_TOC16_DS \.toc
+ +1c: e0 82 00 00 lq r4,0\(r2\)
+ 1e: R_PPC64_TOC16_DS \.toc\+0x8
+ +20: e0 82 00 10 lq r4,16\(r2\)
+ 22: R_PPC64_TOC16_DS \.toc\+0x10
+ +24: e0 82 00 10 lq r4,16\(r2\)
+ 26: R_PPC64_TOC16_DS \.toc\+0x18
+ +28: e0 82 00 20 lq r4,32\(r2\)
+ 2a: R_PPC64_TOC16_DS \.toc\+0x20
+ +2c: e0 82 00 20 lq r4,32\(r2\)
+ 2e: R_PPC64_TOC16_DS \.toc\+0x28
+ +30: e0 c2 00 20 lq r6,32\(r2\)
+ 32: R_PPC64_TOC16_LO_DS \.toc\+0x28
+ +34: e0 80 00 00 lq r4,0\(r0\)
+ 36: R_PPC64_ADDR16_LO_DS \.text
+ +38: e0 c3 00 00 lq r6,0\(r3\)
+ 3a: R_PPC64_GOT16_DS dsym0
+ +3c: e0 c3 00 00 lq r6,0\(r3\)
+ 3e: R_PPC64_GOT16_LO_DS dsym0
+ +40: e0 c3 00 00 lq r6,0\(r3\)
+ 42: R_PPC64_PLT16_LO_DS dsym0
+ +44: e0 c3 00 00 lq r6,0\(r3\)
+ 46: R_PPC64_SECTOFF_DS dsym1
+ +48: e0 c3 00 00 lq r6,0\(r3\)
+ 4a: R_PPC64_SECTOFF_LO_DS dsym1
+ +4c: e0 c4 00 10 lq r6,16\(r4\)
+ +50: f8 c7 00 02 stq r6,0\(r7\)
+ +54: f8 c7 00 12 stq r6,16\(r7\)
+ +58: f8 c7 ff f2 stq r6,-16\(r7\)
+ +5c: f8 c7 80 02 stq r6,-32768\(r7\)
+ +60: f8 c7 7f f2 stq r6,32752\(r7\)
+ +64: 00 00 02 00 attn
+Disassembly of section \.data:
+
+0+ <dsym0>:
+ +0: 00 00 00 00 \.long 0x0
+ +4: de ad be ef stfdu f21,-16657\(r13\)
+
+0+8 <dsym1>:
+ +8: 00 00 00 00 \.long 0x0
+ +c: ca fe ba be lfd f23,-17730\(r30\)
+
+Disassembly of section \.toc:
+
+0+ <\.toc>:
+ \.\.\.
+ 0: R_PPC64_ADDR64 dsym0
+ 8: R_PPC64_ADDR64 dsym1
+ 10: R_PPC64_ADDR64 usym0
+ 18: R_PPC64_ADDR64 usym1
+ 20: R_PPC64_ADDR64 esym0
+ 28: R_PPC64_ADDR64 esym1
--- /dev/null
+
+ .section ".data"
+dsym0: .llong 0xdeadbeef
+dsym1:
+
+
+ .section ".toc"
+.L_tsym0:
+ .tc ignored0[TC],dsym0
+.L_tsym1:
+ .tc ignored1[TC],dsym1
+.L_tsym2:
+ .tc ignored2[TC],usym0
+.L_tsym3:
+ .tc ignored3[TC],usym1
+.L_tsym4:
+ .tc ignored4[TC],esym0
+.L_tsym5:
+ .tc ignored5[TC],esym1
+
+
+ .section ".text"
+ lq 4,dsym0@l(3)
+ lq 4,dsym1@l(3)
+ lq 4,usym0@l(3)
+ lq 4,usym1@l(3)
+ lq 4,esym0@l(3)
+ lq 4,esym1@l(3)
+ lq 4,.L_tsym0@toc(2)
+ lq 4,.L_tsym1@toc(2)
+ lq 4,.L_tsym2@toc(2)
+ lq 4,.L_tsym3@toc(2)
+ lq 4,.L_tsym4@toc(2)
+ lq 4,.L_tsym5@toc(2)
+ lq 6,.L_tsym5@toc@l(2)
+ lq 4,.text@l(0)
+ lq 6,dsym0@got(3)
+ lq 6,dsym0@got@l(3)
+ lq 6,dsym0@plt@l(3)
+ lq 6,dsym1@sectoff(3)
+ lq 6,dsym1@sectoff@l(3)
+ lq 6,usym1-dsym0@l(4)
+ stq 6, 0(7)
+ stq 6, 16(7)
+ stq 6, -16(7)
+ stq 6, -32768(7)
+ stq 6, 32752(7)
+ attn
+
+ .section ".data"
+usym0: .llong 0xcafebabe
+usym1:
+
+2003-06-10 Gary Hade <garyhade@us.ibm.com>
+
+ * ppc.h (PPC_OPERAND_DQ): Define.
+
2003-06-10 Richard Sandiford <rsandifo@redhat.com>
* h8300.h (IMM4_NS, IMM8_NS): New.
2003-06-03 Michael Snyder <msnyder@redhat.com>
* h8sx.h (enum h8_model): Add AV_H8S to distinguish from H8H.
- (ldc): Split ccr ops from exr ops (which are only available
+ (ldc): Split ccr ops from exr ops (which are only available
on H8S or H8SX).
(stc): Ditto.
(andc, orc, xorc): Ditto.
fields.
(h8_opcodes). Modify initializer and initializer macros to no
longer initialize the removed fields.
-
+
2002-11-19 Svein E. Seldal <Svein.Seldal@solidas.com>
* tic4x.h (c4x_insts): Fixed LDHI constraint
* cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE.
2002-09-30 Gavin Romig-Koch <gavin@redhat.com>
- Ken Raeburn <raeburn@cygnus.com>
-
Aldy Hernandez <aldyh@redhat.com>
- Eric Christopher <echristo@redhat.com>
- Richard Sandiford <rsandifo@redhat.com>
+ Ken Raeburn <raeburn@cygnus.com>
+ Aldy Hernandez <aldyh@redhat.com>
+ Eric Christopher <echristo@redhat.com>
+ Richard Sandiford <rsandifo@redhat.com>
* mips.h: Update comment for new opcodes.
(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
Don't match CPU_R4111 with INSN_4100.
2002-08-19 Elena Zannoni <ezannoni@redhat.com>
-
- From matthew green <mrg@redhat.com>
- * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
+ From matthew green <mrg@redhat.com>
+
+ * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
instructions.
- (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
+ (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
e500x2 Integer select, branch locking, performance monitor,
cache locking and machine check APUs, respectively.
2002-05-17 Andrey Volkov <avolkov@sources.redhat.com>
- * h8300.h: Corrected defs of all control regs
+ * h8300.h: Corrected defs of all control regs
and eepmov instr.
-
+
2002-04-11 Alan Modra <amodra@bigpond.net.au>
* i386.h: Add intel mode cmpsd and movsd.
2001-02-02 Patrick Macdonald <patrickm@redhat.com>
- * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
- (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
- (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
+ * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
+ (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
+ (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
2001-01-24 Karsten Keil <kkeil@suse.de>
2000-12-01 Chris Demetriou <cgd@sibyte.com>
- mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
- (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
- OP_*_SYSCALL definitions.
- (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
- 19 bit wait codes.
- (MIPS operand specifier comments): Remove 'm', add 'U' and
- 'J', and update the meaning of 'B' so that it's more general.
-
- * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
- INSN_ISA5): Renumber, redefine to mean the ISA at which the
- instruction was added.
- (INSN_ISA32): New constant.
- (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
- Renumber to avoid new and/or renumbered INSN_* constants.
- (INSN_MIPS32): Delete.
- (ISA_UNKNOWN): New constant to indicate unknown ISA.
- (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
- ISA_MIPS32): New constants, defined to be the mask of INSN_*
- constants available at that ISA level.
- (CPU_UNKNOWN): New constant to indicate unknown CPU.
- (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
- define it with a unique value.
- (OPCODE_IS_MEMBER): Update for new ISA membership-related
- constant meanings.
-
- * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
- definitions.
-
- * mips.h (CPU_SB1): New constant.
+ mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.
+ (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old
+ OP_*_SYSCALL definitions.
+ (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as
+ 19 bit wait codes.
+ (MIPS operand specifier comments): Remove 'm', add 'U' and
+ 'J', and update the meaning of 'B' so that it's more general.
+
+ * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4,
+ INSN_ISA5): Renumber, redefine to mean the ISA at which the
+ instruction was added.
+ (INSN_ISA32): New constant.
+ (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32):
+ Renumber to avoid new and/or renumbered INSN_* constants.
+ (INSN_MIPS32): Delete.
+ (ISA_UNKNOWN): New constant to indicate unknown ISA.
+ (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5,
+ ISA_MIPS32): New constants, defined to be the mask of INSN_*
+ constants available at that ISA level.
+ (CPU_UNKNOWN): New constant to indicate unknown CPU.
+ (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter,
+ define it with a unique value.
+ (OPCODE_IS_MEMBER): Update for new ISA membership-related
+ constant meanings.
+
+ * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
+ definitions.
+
+ * mips.h (CPU_SB1): New constant.
2000-10-20 Jakub Jelinek <jakub@redhat.com>
2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk>
- * d30v.h:
- (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
- (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
- (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
- (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
- (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
- (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
- (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
+ * d30v.h:
+ (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated.
+ (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated.
+ (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated.
+ (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated.
+ (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated.
+ (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated.
+ (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated.
2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au>
2000-02-24 Nick Clifton <nickc@cygnus.com>
* cgen.h (cgen_cpu_desc): Rename field 'flags' to
- 'signed_overflow_ok_p'.
+ 'signed_overflow_ok_p'.
Delete prototypes for cgen_set_flags() and cgen_get_flags().
2000-02-24 Andrew Haley <aph@cygnus.com>
Sun Oct 10 01:46:56 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org>
- * hppa.h (pa_opcodes): Add load and store cache control to
+ * hppa.h (pa_opcodes): Add load and store cache control to
instructions. Add ordered access load and store.
* hppa.h (pa_opcode): Add new entries for addb and addib.
* hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
- * hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
+ * hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
Add supporting args.
- * hppa.h: Document new completers and args.
- * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
+ * hppa.h: Document new completers and args.
+ * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0
extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions
pmenb and pmdis.
- * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
+ * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
hshr, hsub, mixh, mixw, permh.
* hppa.h (pa_opcodes): Change completers in instructions to
use 'c' prefix.
- * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
+ * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments.
- * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
+ * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
fnegabs to use 'I' instead of 'F'.
1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au>
* hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr.
- * hppa.h: Document 64 bit condition completers.
+ * hppa.h: Document 64 bit condition completers.
Thu Aug 5 16:56:07 1999 Jerry Quinn <jquinn@nortelnetworks.com>
* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
- * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
+ * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au>
Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com>
- * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
- (x_FP, d_FP, dls_FP, sldx_FP): Define.
- Change *Suf definitions to include x and d suffixes.
- (movsx): Use w_Suf and b_Suf.
- (movzx): Likewise.
- (movs): Use bwld_Suf.
- (fld): Change ordering. Use sld_FP.
- (fild): Add Intel Syntax equivalent of fildq.
- (fst): Use sld_FP.
- (fist): Use sld_FP.
- (fstp): Use sld_FP. Add x_FP version.
- (fistp): LLongMem version for Intel Syntax.
- (fcom, fcomp): Use sld_FP.
- (fadd, fiadd, fsub): Use sld_FP.
- (fsubr): Use sld_FP.
- (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP.
+ * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
+ (x_FP, d_FP, dls_FP, sldx_FP): Define.
+ Change *Suf definitions to include x and d suffixes.
+ (movsx): Use w_Suf and b_Suf.
+ (movzx): Likewise.
+ (movs): Use bwld_Suf.
+ (fld): Change ordering. Use sld_FP.
+ (fild): Add Intel Syntax equivalent of fildq.
+ (fst): Use sld_FP.
+ (fist): Use sld_FP.
+ (fstp): Use sld_FP. Add x_FP version.
+ (fistp): LLongMem version for Intel Syntax.
+ (fcom, fcomp): Use sld_FP.
+ (fadd, fiadd, fsub): Use sld_FP.
+ (fsubr): Use sld_FP.
+ (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP.
1999-01-27 Doug Evans <devans@casey.cygnus.com>
Tue Mar 25 22:57:26 1997 Stu Grossman (grossman@critters.cygnus.com)
- * v850.h (extract): Make unsigned.
+ * v850.h (extract): Make unsigned.
Mon Mar 24 14:38:15 1997 Ian Lance Taylor <ian@cygnus.com>
Fri Sep 27 18:26:46 1996 Stu Grossman (grossman@critters.cygnus.com)
- * v850.h: Add new flag to indicate this instruction uses a PC
+ * v850.h: Add new flag to indicate this instruction uses a PC
displacement.
Fri Sep 13 14:58:13 1996 Jeffrey A Law (law@cygnus.com)
Sat Jan 21 17:50:38 1995 Pat Rankin (rankin@eql.caltech.edu)
- * vax.h (struct vot_wot, field `args'): Make it pointer to const
+ * vax.h (struct vot_wot, field `args'): Make it pointer to const
char.
- (struct vot, field `name'): ditto.
+ (struct vot, field `name'): ditto.
Thu Jan 19 14:47:53 1995 Ken Raeburn <raeburn@cujo.cygnus.com>
Fri Jul 30 18:41:11 1993 John Gilmore (gnu@cygnus.com)
- * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark
+ * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark
jump instructions, for use in disassemblers.
Thu Jul 22 07:25:27 1993 Ian Lance Taylor (ian@cygnus.com)
Thu Mar 18 13:45:31 1993 Per Bothner (bothner@rtl.cygnus.com)
- * i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com).
- * mips.h: Add casts, to suppress warnings about shifting too much.
- * m68k.h: Document the placement code '9'.
+ * i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com).
+ * mips.h: Add casts, to suppress warnings about shifting too much.
+ * m68k.h: Document the placement code '9'.
Thu Feb 18 02:03:14 1993 John Gilmore (gnu@cygnus.com)
- * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
+ * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
allows callers to break up the large initialized struct full of
opcodes into two half-sized ones. This permits GCC to compile
this module, since it takes exponential space for initializers.
- (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
+ (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
Thu Feb 4 02:06:56 1993 John Gilmore (gnu@cygnus.com)
- * a29k.h: Remove RCS crud, update GPL to v2, update copyrights.
- * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all
+ * a29k.h: Remove RCS crud, update GPL to v2, update copyrights.
+ * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all
initialized structs in it.
Thu Jan 28 21:32:22 1993 John Gilmore (gnu@cygnus.com)
Delta 88 changes inspired by Carl Greco, <cgreco@Creighton.Edu>:
- * m88k.h (PMEM): Avoid previous definition from <sys/param.h>.
- (AND): Change to AND_ to avoid ansidecl.h `AND' conflict.
+ * m88k.h (PMEM): Avoid previous definition from <sys/param.h>.
+ (AND): Change to AND_ to avoid ansidecl.h `AND' conflict.
Sat Jan 23 18:10:49 PST 1993 Ralph Campbell (ralphc@pyramid.com)
Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com)
- * hppa.h: Move handy aliases to the front. Fix masks for extract
+ * hppa.h: Move handy aliases to the front. Fix masks for extract
and deposit instructions.
Sat Dec 12 16:09:48 1992 Ian Lance Taylor (ian@cygnus.com)
Tue Sep 22 00:38:41 1992 John Gilmore (gnu@cygnus.com)
- * mips.h (break): Disassemble the argument. Patch from
+ * mips.h (break): Disassemble the argument. Patch from
jonathan@cs.stanford.edu (Jonathan Stone).
Wed Sep 9 11:25:28 1992 Ian Lance Taylor (ian@cygnus.com)
Fri Aug 14 14:20:38 1992 Per Bothner (bothner@cygnus.com)
- * m68k.h: Merged in patches (mostly m68040-specific) from
+ * m68k.h: Merged in patches (mostly m68040-specific) from
Colin Smith <colin@wrs.com>.
- * m68k.h: Merged m68kmri.h and m68k.h (using the former as a
+ * m68k.h: Merged m68kmri.h and m68k.h (using the former as a
base). Also cleaned up duplicates, re-ordered instructions for
the sake of dis-assembling (so aliases come after standard names).
* m68kmri.h: Now just defines some macros, and #includes m68k.h.
Sun Jun 28 13:29:03 1992 Fred Fish (fnf@cygnus.com)
- * h8300.h: Finish filling in all the holes in the opcode table,
+ * h8300.h: Finish filling in all the holes in the opcode table,
so that the Lucid C compiler can digest this as well...
Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com)
- * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases.
+ * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases.
Fix opcodes on various sizes of fild/fist instructions
(16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix).
Use tabs to indent for comments. Fixes suggested by Minh Tran-Le.
Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com)
- * h8300.h: Fill in all the holes in the opcode table so that the
+ * h8300.h: Fill in all the holes in the opcode table so that the
losing HPUX C compiler can digest this...
Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com)
- * mips.h: Fix decoding of coprocessor instructions, somewhat.
+ * mips.h: Fix decoding of coprocessor instructions, somewhat.
(Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.)
Thu May 28 11:17:44 1992 Jim Wilson (wilson@sphagnum.cygnus.com)
Tue May 5 14:23:27 1992 Per Bothner (bothner@rtl.cygnus.com)
- * mips.h: Add some more opcode synonyms (from Frank Yellin,
+ * mips.h: Add some more opcode synonyms (from Frank Yellin,
fy@lucid.com).
Thu Apr 16 18:25:26 1992 Per Bothner (bothner@cygnus.com)
- * rs6k.h: New version from IBM (Metin).
+ * rs6k.h: New version from IBM (Metin).
Thu Apr 9 00:31:19 1992 Per Bothner (bothner@rtl.cygnus.com)
* rs6k.h: Fix incorrect extended opcode for instructions `fm'
- and `fd'. (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).)
+ and `fd'. (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).)
Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com)
- * rs6k.h: Move from ../../gdb/rs6k-opcode.h.
+ * rs6k.h: Move from ../../gdb/rs6k-opcode.h.
Fri Apr 3 11:30:20 1992 Fred Fish (fnf@cygnus.com)
- * m68k.h (one, two): Cast macro args to unsigned to suppress
+ * m68k.h (one, two): Cast macro args to unsigned to suppress
complaints from compiler and lint about integer overflow during
shift.
Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com)
- * sparc.h (OP): Avoid signed overflow when shifting to high order bit.
+ * sparc.h (OP): Avoid signed overflow when shifting to high order bit.
Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com)
- * mips.h: Make bitfield layout depend on the HOST compiler,
+ * mips.h: Make bitfield layout depend on the HOST compiler,
not on the TARGET system.
Fri Feb 21 01:29:51 1992 K. Richard Pixley (rich@cygnus.com)
Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com)
- * sparc.h: Remove "cypress" architecture. Remove "fitox" and
+ * sparc.h: Remove "cypress" architecture. Remove "fitox" and
similar instructions -- they've been renamed to "fitoq", etc.
REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong
number of arguments.
- * h8300.h: Remove extra ; which produces compiler warning.
+ * h8300.h: Remove extra ; which produces compiler warning.
Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com)
- * sparc.h: fix opcode for tsubcctv.
+ * sparc.h: fix opcode for tsubcctv.
Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com)
Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com)
- * sparc.h (nop): Made the 'lose' field be even tighter,
+ * sparc.h (nop): Made the 'lose' field be even tighter,
so only a standard 'nop' is disassembled as a nop.
Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com)
Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com)
- * m68k.h, sparc.h: ANSIfy enums.
+ * m68k.h, sparc.h: ANSIfy enums.
Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com)
/* ppc.h -- Header file for PowerPC opcode table
- Copyright 1994, 1995, 1999, 2000, 2001, 2002
+ Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
/* This operand is for the DS field in a DS form instruction. */
#define PPC_OPERAND_DS (020000)
+
+/* This operand is for the DQ field in a DQ form instruction. */
+#define PPC_OPERAND_DQ (040000)
\f
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
+2003-06-10 Gary Hade <garyhade@us.ibm.com>
+ Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define.
+ (insert_dq, extract_dq, insert_raq, insert_rtq, insert_rsq): New.
+ (powerpc_opcodes): Add "attn", "lq" and "stq".
+
2003-06-10 Richard Sandiford <rsandifo@redhat.com>
* h8300-dis.c (bfd_h8_disassemble): Don't print brackets round
2003-05-17 Andreas Jaeger <aj@suse.de>
- * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la.
- (libopcodes_la_DEPENDENCIES): Add libbfd.la.
- * Makefile.in: Regenerated.
+ * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la.
+ (libopcodes_la_DEPENDENCIES): Add libbfd.la.
+ * Makefile.in: Regenerated.
2003-05-16 Nick Clifton <nickc@redhat.com>
2003-03-25 Stan Cox <scox@redhat.com>
Nick Clifton <nickc@redhat.com>
-
+
Contribute support for Intel's iWMMXt chip - an ARM variant:
* arm-dis.c (regnames): Add iWMMXt register names.
2002-01-02 Ben Elliston <bje@redhat.com>
Jeff Johnston <jjohnstn@redhat.com>
- * iq2000-asm.c: New file.
- * iq2000-desc.c: Likewise.
- * iq2000-desc.h: Likewise.
- * iq2000-dis.c: Likewise.
- * iq2000-ibld.c: Likewise.
- * iq2000-opc.c: Likewise.
- * iq2000-opc.h: Likewise.
- * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h.
- (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c,
- iq2000-ibld.c, iq2000-opc.c.
- (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo,
- iq2000-ibld.lo, iq2000-opc.lo.
- (CLEANFILES): Add stamp-iq2000.
- (IQ2000_DEPS): New macro.
- (stamp-iq2000): New target.
- * Makefile.in: Regenerate.
- * configure.in: Handle bfd_iq2000_arch.
- * configure: Regenerate.
+ * iq2000-asm.c: New file.
+ * iq2000-desc.c: Likewise.
+ * iq2000-desc.h: Likewise.
+ * iq2000-dis.c: Likewise.
+ * iq2000-ibld.c: Likewise.
+ * iq2000-opc.c: Likewise.
+ * iq2000-opc.h: Likewise.
+ * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h.
+ (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c,
+ iq2000-ibld.c, iq2000-opc.c.
+ (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo,
+ iq2000-ibld.lo, iq2000-opc.lo.
+ (CLEANFILES): Add stamp-iq2000.
+ (IQ2000_DEPS): New macro.
+ (stamp-iq2000): New target.
+ * Makefile.in: Regenerate.
+ * configure.in: Handle bfd_iq2000_arch.
+ * configure: Regenerate.
2003-01-02 Chris Demetriou <cgd@broadcom.com>
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
-
+
2002-11-25 Aldy Hernandez <aldyh@redhat.com>
* ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa,
* xstormy16-desc.c: Regenerate.
* xstormy16-opc.c: Regenerate.
* xstormy16-opc.h: Regenerate.
-
+
2002-11-18 Klee Dienes <kdienes@apple.com>
* avr-dis.c: Include libiberty.h (for xmalloc).
2002-11-07 Klee Dienes <kdienes@apple.com>
- * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir'
- argument to ia64-gen.
+ * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir'
+ argument to ia64-gen.
Regenerate dependencies for ia64-len.lo.
* Makefile.in: Regenerate.
- * ia64-gen.c: Convert to use getopt(). Add the standard GNU
- options, as well as '--srcdir', which controls the directory in
- which ia64-gen looks for the sources it uses to generate the
- output table. Add a 'const' to the declaration of the final
- output table. Call xmalloc_set_program_name to set the program
- name.
+ * ia64-gen.c: Convert to use getopt(). Add the standard GNU
+ options, as well as '--srcdir', which controls the directory in
+ which ia64-gen looks for the sources it uses to generate the
+ output table. Add a 'const' to the declaration of the final
+ output table. Call xmalloc_set_program_name to set the program
+ name.
* ia64-asmtab.c: Regenerate.
-
+
2002-11-07 Nick Clifton <nickc@redhat.com>
* ia64-gen.c: Fix comment formatting and compile time warnings.
2002-11-06 Aldy Hernandez <aldyh@redhat.com>
- * opcodes/ppc-opc.c: Change RD to RS for evmerge*.
+ * opcodes/ppc-opc.c: Change RD to RS for evmerge*.
2002-10-07 Nathan Tallent <eraxxon@alumni.rice.edu>
at the end.
2002-09-30 Gavin Romig-Koch <gavin@redhat.com>
- Ken Raeburn <raeburn@cygnus.com>
-
Aldy Hernandez <aldyh@redhat.com>
- Eric Christopher <echristo@redhat.com>
- Richard Sandiford <rsandifo@redhat.com>
+ Ken Raeburn <raeburn@cygnus.com>
+ Aldy Hernandez <aldyh@redhat.com>
+ Eric Christopher <echristo@redhat.com>
+ Richard Sandiford <rsandifo@redhat.com>
* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
PARAMS ((unsigned long, long, int, const char **));
static long extract_boe
PARAMS ((unsigned long, int, int *));
+static unsigned long insert_dq
+ PARAMS ((unsigned long, long, int, const char **));
+static long extract_dq
+ PARAMS ((unsigned long, int, int *));
static unsigned long insert_ds
PARAMS ((unsigned long, long, int, const char **));
static long extract_ds
PARAMS ((unsigned long, long, int, const char **));
static unsigned long insert_ram
PARAMS ((unsigned long, long, int, const char **));
+static unsigned long insert_raq
+ PARAMS ((unsigned long, long, int, const char **));
static unsigned long insert_ras
PARAMS ((unsigned long, long, int, const char **));
static unsigned long insert_rbs
PARAMS ((unsigned long, long, int, const char **));
static long extract_rbs
PARAMS ((unsigned long, int, int *));
+static unsigned long insert_rsq
+ PARAMS ((unsigned long, long, int, const char **));
+static unsigned long insert_rtq
+ PARAMS ((unsigned long, long, int, const char **));
static unsigned long insert_sh6
PARAMS ((unsigned long, long, int, const char **));
static long extract_sh6
#define DES DE + 1
{ 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+ /* The DQ field in a DQ form instruction. This is like D, but the
+ lower four bits are forced to zero. */
+#define DQ DES + 1
+ { 16, 0, insert_dq, extract_dq,
+ PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
+
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
-#define DS DES + 1
+#define DS DQ + 1
{ 16, 0, insert_ds, extract_ds,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
{ 16, 0, insert_nsi, extract_nsi,
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
- /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
+ /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
#define RA NSI + 1
#define RA_MASK (0x1f << 16)
{ 5, 16, 0, 0, PPC_OPERAND_GPR },
+ /* The RA field in the DQ form lq instruction, which has special
+ value restrictions. */
+#define RAQ RA + 1
+ { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
+
/* The RA field in a D or X form instruction which is an updating
load, which means that the RA field may not be zero and may not
equal the RT field. */
-#define RAL RA + 1
+#define RAL RAQ + 1
{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
/* The RA field in an lmw instruction, which has special value
#define RT_MASK (0x1f << 21)
{ 5, 21, 0, 0, PPC_OPERAND_GPR },
+ /* The RS field of the DS form stq instruction, which has special
+ value restrictions. */
+#define RSQ RS + 1
+ { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
+
+ /* The RT field of the DQ form lq instruction, which has special
+ value restrictions. */
+#define RTQ RSQ + 1
+ { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
+
/* The SH field in an X or M form instruction. */
-#define SH RS + 1
+#define SH RTQ + 1
#define SH_MASK (0x1f << 11)
{ 5, 11, 0, 0, 0 },
return value & 0x1e;
}
+ /* The DQ field in a DQ form instruction. This is like D, but the
+ lower four bits are forced to zero. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_dq (insn, value, dialect, errmsg)
+ unsigned long insn;
+ long value;
+ int dialect ATTRIBUTE_UNUSED;
+ const char ** errmsg ATTRIBUTE_UNUSED;
+{
+ if ((value & 0xf) != 0 && errmsg != NULL)
+ *errmsg = _("offset not a multiple of 16");
+ return insn | (value & 0xfff0);
+}
+
+/*ARGSUSED*/
+static long
+extract_dq (insn, dialect, invalid)
+ unsigned long insn;
+ int dialect ATTRIBUTE_UNUSED;
+ int *invalid ATTRIBUTE_UNUSED;
+{
+ return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
+}
+
static unsigned long
insert_ev2 (insn, value, dialect, errmsg)
unsigned long insn;
return insn | ((value & 0x1f) << 16);
}
+ /* The RA field in the DQ form lq instruction, which has special
+ value restrictions. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_raq (insn, value, dialect, errmsg)
+ unsigned long insn;
+ long value;
+ int dialect ATTRIBUTE_UNUSED;
+ const char **errmsg;
+{
+ long rtvalue = (insn & RT_MASK) >> 21;
+
+ if (value == rtvalue && errmsg != NULL)
+ *errmsg = _("source and target register operands must be different");
+ return insn | ((value & 0x1f) << 16);
+}
+
/* The RA field in a D or X form instruction which is an updating
store or an updating floating point load, which means that the RA
field may not be zero. */
return 0;
}
+ /* The RT field of the DQ form lq instruction, which has special
+ value restrictions. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rtq (insn, value, dialect, errmsg)
+ unsigned long insn;
+ long value;
+ int dialect ATTRIBUTE_UNUSED;
+ const char **errmsg;
+{
+ if ((value & 1) != 0 && errmsg != NULL)
+ *errmsg = _("target register operand must be even");
+ return insn | ((value & 0x1f) << 21);
+}
+
+ /* The RS field of the DS form stq instruction, which has special
+ value restrictions. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rsq (insn, value, dialect, errmsg)
+ unsigned long insn;
+ long value ATTRIBUTE_UNUSED;
+ int dialect ATTRIBUTE_UNUSED;
+ const char **errmsg;
+{
+ if ((value & 1) != 0 && errmsg != NULL)
+ *errmsg = _("source register operand must be even");
+ return insn | ((value & 0x1f) << 21);
+}
+
/* The SH field in an MD form instruction. This is split. */
/*ARGSUSED*/
sorted by major opcode. */
const struct powerpc_opcode powerpc_opcodes[] = {
+{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
+{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
+
{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
+{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
+
{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
projects / binutils-gdb.git / commitdiff