pytholite: fix bit width of selection signal

diff --git a/migen/pytholite/reg.py b/migen/pytholite/reg.py
index 32bb348cd302cdcf6bd38b363ac21c90b9640dc2..5ec49c4a9d5723fac6a53021d4cab38c26fea36f 100644 (file)
--- a/migen/pytholite/reg.py
+++ b/migen/pytholite/reg.py
@@ -40,7 +40,7 @@ class ImplRegister:
        def finalize(self):
                if self.finalized:
                        raise FinalizeError
-               self.sel = Signal(max=len(self.source_encoding)+2, name="pl_regsel_"+self.name)
+               self.sel = Signal(max=len(self.source_encoding)+1, name="pl_regsel_"+self.name)
                self.finalized = True
        
        def get_fragment(self):