if zeroing is set, put zero into input or output as requested

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 09a02006d54d104a5f677d35e5e63111301b59f6..53e023ad6bb68d289bacccc9f5f627936961753e 100644 (file)
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -31,7 +31,9 @@ class CommonInputStage(PipeModBase):
         else:
             comb += a.eq(self.i.a)
 
-        comb += self.o.a.eq(a)
+        # SV zeroing on predicate source zeros the input
+        with m.If(~op.sv_pred_sz):
+            comb += self.o.a.eq(a)
 
         ##### operand B #####
 
@@ -46,7 +48,9 @@ class CommonInputStage(PipeModBase):
         else:
             comb += b.eq(self.i.b)
 
-        comb += self.o.b.eq(b)
+        # SV zeroing on predicate source zeros the input
+        with m.If(~op.sv_pred_sz):
+            comb += self.o.b.eq(b)
 
         ##### carry-in #####
 

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index e5cf3a308506e23207e82acae6e4c4f16eea1807..23e83f57ee4ebe5aa4a1cb26d392882bfe0ccce1 100644 (file)
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -87,11 +87,13 @@ class CommonOutputStage(PipeModBase):
         with m.Else():
             comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative))
 
-        # copy out [inverted?] output, cr0, and context out
-        comb += self.o.o.data.eq(o)
+        with m.If(~op.sv_pred_dz):
+            # copy out [inverted?] output, cr0, and context out
+            comb += self.o.o.data.eq(o)
+            comb += self.o.cr0.data.eq(cr0) # CR0 to be set
+
+        # set output to write
         comb += self.o.o.ok.eq(self.i.o.ok)
-        # CR0 to be set
-        comb += self.o.cr0.data.eq(cr0)
         comb += self.o.cr0.ok.eq(op.write_cr0)
         # context
         comb += self.o.ctx.eq(self.i.ctx)