r600g: properly sync CP with CP DMA on R6xx

This will allow removing useless cache & IB flushes.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 6df1360a034843304d3aff4bfc1d8eccb97b5c3f..808bd27607f2f9ba668635e89b479cf20b249b06 100644 (file)
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -405,7 +405,9 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
                unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
                unsigned src_reloc, dst_reloc;
 
-               r600_need_cs_space(rctx, 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
+               r600_need_cs_space(rctx,
+                                  10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0) +
+                                  3, FALSE);
 
                /* Flush the caches for the first copy only. */
                if (rctx->b.flags) {
@@ -440,6 +442,11 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
                dst_offset += byte_count;
        }
 
+       /* CP_DMA_CP_SYNC doesn't wait for idle on R6xx, but this does. */
+       if (rctx->b.chip_class == R600)
+               radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
+                                     S_008040_WAIT_CP_DMA_IDLE(1));
+
        /* Invalidate the read caches. */
        rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
                         R600_CONTEXT_INV_VERTEX_CACHE |