The type attribute "alu_shfit_imm" is subdivided into
"alu_shift_imm_lsl_1to4" and "alu_shift_imm_other", to accommodate
optimazations of some microarchitectures.
Here is the detailed discussion.
https://gcc.gnu.org/pipermail/gcc/2020-September/233594.html
gcc/
* config/arm/types.md (define_attr "autodetect_type"): New.
(define_attr "type"): Subdivide alu_shift_imm.
* config/arm/common.md: New file.
* config/aarch64/predicates.md:Include common.md.
* config/arm/predicates.md:Include common.md.
* config/aarch64/aarch64.md (*add_<shift>_<mode>): Set autodetect_type.
(*add_<shift>_si_uxtw): Likewise.
(*sub_<shift>_<mode>): Likewise.
(*sub_<shift>_si_uxtw): Likewise.
(*neg_<shift>_<mode>2): Likewise.
(*neg_<shift>_si2_uxtw): Likewise.
* config/arm/arm.md (*addsi3_carryin_shift): Likewise.
(add_not_shift_cin): Likewise.
(*subsi3_carryin_shift): Likewise.
(*subsi3_carryin_shift_alt): Likewise.
(*rsbsi3_carryin_shift): Likewise.
(*rsbsi3_carryin_shift_alt): Likewise.
(*arm_shiftsi3): Likewise.
(*<arith_shift_insn>_multsi): Likewise.
(*<arith_shift_insn>_shiftsi): Likewise.
(subsi3_carryin): Set new type.
(*if_arith_move): Set new type.
(*if_move_arith): Set new type.
(define_attr "core_cycles"): Use new type.
* config/arm/arm-fixed.md (arm_ssatsihi_shift): Set autodetect_type.
* config/arm/thumb2.md (*orsi_not_shiftsi_si): Likewise.
(*thumb2_shiftsi3_short): Set new type.
* config/aarch64/falkor.md (falkor_alu_1_xyz): Use new type.
* config/aarch64/saphira.md (saphira_alu_1_xyz): Likewise.
* config/aarch64/thunderx.md (thunderx_arith_shift): Likewise.
* config/aarch64/thunderx2t99.md (thunderx2t99_alu_shift): Likewise.
* config/aarch64/thunderx3t110.md (thunderx3t110_alu_shift): Likewise.
(thunderx3t110_alu_shift1): Likewise.
* config/aarch64/tsv110.md (tsv110_alu_shift): Likewise.
* config/arm/arm1020e.md (1020alu_shift_op): Likewise.
* config/arm/arm1026ejs.md (alu_shift_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_shift_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu_shift): Likewise.
* config/arm/cortex-a17.md (cortex_a17_alu_shiftimm): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu_shift): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
* config/arm/cortex-a57.md (cortex_a57_alu_shift): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_shift): Likewise.
* config/arm/cortex-a8.md (cortex_a8_alu_shift): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp_shift): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
* config/arm/cortex-m7.md (cortex_m7_alu_shift): Likewise.
* config/arm/cortex-r4.md (cortex_r4_alu_shift): Likewise.
* config/arm/exynos-m1.md (exynos_m1_alu_shift): Likewise.
* config/arm/fa526.md (526_alu_shift_op): Likewise.
* config/arm/fa606te.md (606te_alu_op): Likewise.
* config/arm/fa626te.md (626te_alu_shift_op): Likewise.
* config/arm/fa726te.md (726te_alu_shift_op): Likewise.
* config/arm/fmp626.md (mp626_alu_shift_op): Likewise.
* config/arm/marvell-pj4.md (pj4_shift): Likewise.
(pj4_shift_conds): Likewise.
(pj4_alu_shift): Likewise.
(pj4_alu_shift_conds): Likewise.
* config/arm/xgene1.md (xgene1_alu): Likewise.
* config/arm/arm.c (xscale_sched_adjust_cost): Likewise.
(match_operand:GPI 3 "register_operand" "r")))]
""
"add\\t%<w>0, %<w>3, %<w>1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")]
+ [(set_attr "autodetect_type" "alu_shift_<shift>_op2")]
)
;; zero_extend version of above
(match_operand:SI 3 "register_operand" "r"))))]
""
"add\\t%w0, %w3, %w1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")]
+ [(set_attr "autodetect_type" "alu_shift_<shift>_op2")]
)
(define_insn "*add_<optab><ALLX:mode>_<GPI:mode>"
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))]
""
"sub\\t%<w>0, %<w>3, %<w>1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")]
+ [(set_attr "autodetect_type" "alu_shift_<shift>_op2")]
)
;; zero_extend version of above
(match_operand:QI 2 "aarch64_shift_imm_si" "n")))))]
""
"sub\\t%w0, %w3, %w1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")]
+ [(set_attr "autodetect_type" "alu_shift_<shift>_op2")]
)
(define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>"
(match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))))]
""
"neg\\t%<w>0, %<w>1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")]
+ [(set_attr "autodetect_type" "alu_shift_<shift>_op2")]
)
;; zero_extend version of above
(match_operand:QI 2 "aarch64_shift_imm_si" "n")))))]
""
"neg\\t%w0, %w1, <shift> %2"
- [(set_attr "type" "alu_shift_imm")]
+ [(set_attr "autodetect_type" "alu_shift_<shift>_op2")]
)
(define_insn "mul<mode>3"
(define_insn_reservation "falkor_alu_1_xyz" 1
(and (eq_attr "tune" "falkor")
- (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg"))
+ (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg"))
"falkor_xyz")
;; SIMD Miscellaneous Instructions
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+(include "../arm/common.md")
+
(define_special_predicate "cc_register"
(and (match_code "reg")
(and (match_test "REGNO (op) == CC_REGNUM")
(define_insn_reservation "saphira_alu_1_xyz" 1
(and (eq_attr "tune" "saphira")
- (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg"))
+ (eq_attr "type" "alus_sreg,alus_imm,alus_shift_imm,csel,adc_reg,alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,alus_ext,logic_imm,logic_reg,logic_shift_imm,logics_imm,logics_reg,logics_shift_imm,mov_reg"))
"saphira_xyzb")
;; SIMD Miscellaneous Instructions
(define_insn_reservation "thunderx_arith_shift" 2
(and (eq_attr "tune" "thunderx")
- (eq_attr "type" "alu_ext,alu_shift_imm,alu_shift_reg,alus_ext,logic_shift_imm,logic_shift_reg,logics_shift_imm,logics_shift_reg,alus_shift_imm"))
+ (eq_attr "type" "alu_ext,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_shift_reg,alus_ext,logic_shift_imm,logic_shift_reg,logics_shift_imm,logics_shift_reg,alus_shift_imm"))
"thunderx_pipe0 | thunderx_pipe1")
(define_insn_reservation "thunderx_csel" 2
(define_insn_reservation "thunderx2t99_alu_shift" 2
(and (eq_attr "tune" "thunderx2t99")
- (eq_attr "type" "alu_shift_imm,alu_ext,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\
alus_shift_imm,alus_ext,\
logic_shift_imm,logics_shift_imm"))
"thunderx2t99_i012,thunderx2t99_i012")
; is it actually 1,1/2,{i0,i1} vs 2,1/4,{i0,i1,i2,i3}
(define_insn_reservation "thunderx3t110_alu_shift" 2
(and (eq_attr "tune" "thunderx3t110")
- (eq_attr "type" "alu_shift_imm,alu_ext,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\
alus_shift_imm,alus_ext,\
logic_shift_imm,logics_shift_imm"))
"thunderx3t110_i0123")
(define_insn_reservation "thunderx3t110_alu_shift1" 1
(and (eq_attr "tune" "thunderx3t110")
- (eq_attr "type" "alu_shift_imm,alu_ext,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_ext,\
alus_shift_imm,alus_ext,\
logic_shift_imm,logics_shift_imm"))
"thunderx3t110_i01")
(define_insn_reservation "tsv110_alu_shift" 2
(and (eq_attr "tune" "tsv110")
(eq_attr "type" "extend,\
- alu_shift_imm,alu_shift_reg,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alu_shift_reg,\
crc,logic_shift_imm,logic_shift_reg,\
mov_shift,mvn_shift,\
mov_shift_reg,mvn_shift_reg"))
"ssat%?\\t%0, #16, %2%S1"
[(set_attr "predicable" "yes")
(set_attr "shift" "1")
- (set_attr "type" "alu_shift_imm")])
+ (set_attr "autodetect_type" "alu_shift_operator1")])
(define_insn "arm_usatsihi"
[(set (match_operand:HI 0 "s_register_operand" "=r")
instruction we depend on is another ALU instruction, then we may
have to account for an additional stall. */
if (shift_opnum != 0
- && (attr_type == TYPE_ALU_SHIFT_IMM
+ && (attr_type == TYPE_ALU_SHIFT_IMM_LSL_1TO4
+ || attr_type == TYPE_ALU_SHIFT_IMM_OTHER
|| attr_type == TYPE_ALUS_SHIFT_IMM
|| attr_type == TYPE_LOGIC_SHIFT_IMM
|| attr_type == TYPE_LOGICS_SHIFT_IMM
(define_attr "core_cycles" "single,multi"
(if_then_else (eq_attr "type"
"adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\
- alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\
+ alu_shift_imm_lsl_1to4, alu_shift_imm_other, alu_shift_reg, alu_dsp_reg,\
+ alus_ext, alus_imm, alus_sreg,\
alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
(set_attr "arch" "32,a")
(set_attr "shift" "3")
(set_attr "predicable" "yes")
- (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+ (set_attr "autodetect_type" "alu_shift_operator2")]
)
(define_insn "*addsi3_carryin_clobercc"
[(set_attr "conds" "use")
(set_attr "arch" "*,a,t2")
(set_attr "predicable" "yes")
- (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
+ (set_attr "type" "adc_reg,adc_imm,alu_shift_imm_lsl_1to4")]
)
;; Special canonicalization of the above when operand1 == (const_int 1):
"rsc%?\\t%0, %4, %1%S3"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
- (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+ (set_attr "autodetect_type" "alu_shift_operator3")]
)
(define_insn "cmpsi3_carryin_<CC_EXTEND>out"
(set_attr "arch" "32,a")
(set_attr "shift" "3")
(set_attr "predicable" "yes")
- (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+ (set_attr "autodetect_type" "alu_shift_operator2")]
)
(define_insn "*subsi3_carryin_shift_alt"
(set_attr "arch" "32,a")
(set_attr "shift" "3")
(set_attr "predicable" "yes")
- (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+ (set_attr "autodetect_type" "alu_shift_operator2")]
)
;; No RSC in Thumb2
"rsc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
- (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+ (set_attr "autodetect_type" "alu_shift_operator2")]
)
(define_insn "*rsbsi3_carryin_shift_alt"
"rsc%?\\t%0, %1, %3%S2"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
- (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+ (set_attr "autodetect_type" "alu_shift_operator2")]
)
; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
(set_attr "predicable_short_it" "yes,yes,no,no")
(set_attr "length" "4")
(set_attr "shift" "1")
- (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_imm,alu_shift_reg")]
+ (set_attr "autodetect_type" "alu_shift_operator3")]
)
(define_insn "*shiftsi3_compare0"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
(set_attr "arch" "a,t2")
- (set_attr "type" "alu_shift_imm")])
+ (set_attr "autodetect_type" "alu_shift_mul_op3")])
(define_insn "*<arith_shift_insn>_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
[(set_attr "predicable" "yes")
(set_attr "shift" "3")
(set_attr "arch" "a,t2,a")
- (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")])
+ (set_attr "autodetect_type" "alu_shift_operator2")])
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(set_attr "length" "4,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_shift_imm" )
+ (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other"))
(const_string "alu_shift_reg"))
(const_string "multiple")])]
)
(set_attr "length" "4,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "alu_shift_imm" )
+ (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other"))
(const_string "alu_shift_reg"))
(const_string "multiple")])]
)
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "1020alu_shift_op" 1
(and (eq_attr "tune" "arm10e")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend,mov_shift,mvn_shift"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "alu_shift_op" 1
(and (eq_attr "tune" "arm1026ejs")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend,mov_shift,mvn_shift"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "11_alu_shift_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend,mov_shift,mvn_shift"))
"e_1,e_2,e_3,e_wb")
alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
shift_imm,shift_reg,extend,\
mov_imm,mov_reg,mov_shift,\
--- /dev/null
+;; Common predicate definitions for ARM, Thumb and AArch64
+;; Copyright (C) 2020 Free Software Foundation, Inc.
+;; Contributed by Fujitsu Ltd.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Return true if constant is CONST_INT >= 1 and <= 4
+(define_predicate "const_1_to_4_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), 1, 4)")))
+
+;; Return true if constant is 2 or 4 or 8 or 16
+(define_predicate "const_2_4_8_16_operand"
+ (and (match_code "const_int")
+ (match_test (" INTVAL (op) == 2
+ || INTVAL (op) == 4
+ || INTVAL (op) == 8
+ || INTVAL (op) == 16 "))))
+
+;; Return true if shift type is lsl and amount is in[1,4].
+(define_predicate "alu_shift_operator_lsl_1_to_4"
+ (and (match_code "ashift")
+ (match_test "const_1_to_4_operand (XEXP (op, 1), mode)")))
+
+;; Return true if the operand is register.
+(define_predicate "alu_shift_reg_p"
+ (match_test "register_operand (XEXP (op, 1), mode)"))
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
(eq_attr "type" "extend,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
crc,logic_shift_imm,logics_shift_imm,\
mov_shift,mvn_shift"))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
(define_insn_reservation "cortex_a17_alu_shiftimm" 2
(and (eq_attr "tune" "cortexa17")
- (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm, alus_shift_imm,
+ (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm_lsl_1to4,alu_shift_imm_other, alus_shift_imm,
logic_shift_imm,alu_dsp_reg, logics_shift_imm,shift_imm,\
shift_reg, mov_shift,mvn_shift"))
"ca17_alu")
(define_insn_reservation "cortex_a5_alu_shift" 2
(and (eq_attr "tune" "cortexa5")
(eq_attr "type" "extend,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
(define_insn_reservation "cortex_a53_alu_shift" 3
(and (eq_attr "tune" "cortexa53")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm,
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,
crc,logic_shift_imm,logics_shift_imm,
alu_ext,alus_ext,bfm,bfx,extend,mvn_shift"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a57_alu_shift" 3
(and (eq_attr "tune" "cortexa57")
(eq_attr "type" "bfm,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
crc,logic_shift_imm,logics_shift_imm,\
mov_shift,mvn_shift"))
"ca57_mx")
(define_insn_reservation "cortex_a7_alu_shift" 2
(and (eq_attr "tune" "cortexa7")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
(define_insn_reservation "cortex_a8_alu_shift" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend"))
"cortex_a8_default")
;; An instruction using the shifter will go down E1.
(define_insn_reservation "cortex_a9_dp_shift" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,clz,rbit,rev,alu_dsp_reg,\
shift_imm,shift_reg,extend,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
;; Simple alu with inline shift operation.
(define_insn_reservation "cortex_m7_alu_shift" 2
(and (eq_attr "tune" "cortexm7")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm"))
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm"))
"cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_shf+cm7_branch")
;; Only one ALU can be used for DSP instructions.
(define_insn_reservation "cortex_r4_alu_shift" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
extend,mov_shift,mvn_shift"))
"cortex_r4_alu")
(define_insn_reservation "exynos_m1_alu_shift" 2
(and (eq_attr "tune" "exynosm1")
(eq_attr "type" "alu_ext, alus_ext,\
- alu_shift_imm, alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other, alus_shift_imm,\
logic_shift_imm, logics_shift_imm,\
mov_shift, mvn_shift"))
"(em1_alu)")
(define_insn_reservation "526_alu_shift_op" 2
(and (eq_attr "tune" "fa526")
(eq_attr "type" "extend,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
adr,bfm,rev,\
shift_imm,shift_reg,extend,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
(define_insn_reservation "626te_alu_shift_op" 2
(and (eq_attr "tune" "fa626,fa626te")
(eq_attr "type" "extend,\
- alu_shift_imm,alus_shift_imm,\
+ alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm,\
alu_shift_reg,alus_shift_reg,\
logic_shift_reg,logics_shift_reg,\
;; it takes 3 cycles.
(define_insn_reservation "726te_alu_shift_op" 3
(and (eq_attr "tune" "fa726te")
- (eq_attr "type" "extend,alu_shift_imm,alus_shift_imm,\
+ (eq_attr "type" "extend,alu_shift_imm_lsl_1to4,alu_shift_imm_other,alus_shift_imm,\
logic_shift_imm,logics_shift_imm"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
(define_insn_reservation "mp626_alu_shift_op" 2
(and (eq_attr "tune" "fmp626")
- (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
extend,\
mov_shift,mov_shift_reg,\
(define_insn_reservation "pj4_shift" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\
alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,\
alus_shift_reg,logics_shift_reg,\
(define_insn_reservation "pj4_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\
alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,\
alus_shift_reg,logics_shift_reg,\
(define_insn_reservation "pj4_alu_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(not (eq_attr "conds" "set"))
- (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,\
alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,\
alus_shift_reg,logics_shift_reg,\
(define_insn_reservation "pj4_alu_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "conds" "set")
- (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
+ (eq_attr "type" "alu_shift_imm_lsl_1to4,alu_shift_imm_other,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+(include "common.md")
+
(define_predicate "s_register_operand"
(match_code "reg,subreg")
{
(set_attr "shift" "1")
(set_attr "length" "2")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "alu_shift_imm")
+ (if_then_else (match_operand 3 "alu_shift_operator_lsl_1_to_4")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other"))
(const_string "alu_shift_reg")))]
)
"orn%?\\t%0, %1, %2%S4"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
- (set_attr "type" "alu_shift_imm")]
+ (set_attr "autodetect_type" "alu_shift_operator4")]
)
(define_peephole2
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
+; The insn need to autodetect for specific type attribute
+(define_attr "autodetect_type"
+ "none,
+ alu_shift_lsl_op2,
+ alu_shift_lsr_op2,
+ alu_shift_asr_op2,
+ alu_shift_mul_op3,
+ alu_shift_operator1,
+ alu_shift_operator2,
+ alu_shift_operator3,
+ alu_shift_operator4"
+ (const_string "none"))
+
; TYPE attribute is used to classify instructions for use in scheduling.
;
; Instruction classification:
; or an immediate operand. This excludes
; MOV and MVN but includes MOVT. This also excludes
; DSP-kind instructions. This is also the default.
-; alu_shift_imm any arithmetic instruction that has a source operand
-; shifted by a constant. This excludes simple shifts.
-; alu_shift_reg as alu_shift_imm, with the shift amount specified in a
+; alu_shift_imm_lsl_1to4
+; any arithmetic instruction that has a source operand
+; shifted left by a constant in range 1 to 4. This
+; excludes simple shifts.
+; alu_shift_imm_other
+; as alu_shift_imm_lsl_1to4, with the shift type is LSR or
+; ASR, or the shift amount is greater than or equal 5.
+; alu_shift_reg as alu_shift_imm_*, with the shift amount specified in a
; register.
; alu_dsp_reg any DSP-kind instruction like QSUB8.
; alus_ext From ARMv8-A: as alu_ext, setting condition flags.
; AArch64 Only.
; alus_imm as alu_imm, setting condition flags.
; alus_sreg as alu_sreg, setting condition flags.
-; alus_shift_imm as alu_shift_imm, setting condition flags.
+; alus_shift_imm as alu_shift_imm_*, setting condition flags.
; alus_shift_reg as alu_shift_reg, setting condition flags.
; bfm bitfield move operation.
; bfx bitfield extract operation.
alu_ext,\
alu_imm,\
alu_sreg,\
- alu_shift_imm,\
+ alu_shift_imm_lsl_1to4,\
+ alu_shift_imm_other,\
alu_shift_reg,\
alu_dsp_reg,\
alus_ext,\
mve_move,\
mve_store,\
mve_load"
- (const_string "untyped"))
+ (cond [(eq_attr "autodetect_type" "alu_shift_lsr_op2,alu_shift_asr_op2")
+ (const_string "alu_shift_imm_other")
+ (eq_attr "autodetect_type" "alu_shift_lsl_op2")
+ (if_then_else (match_operand 2 "const_1_to_4_operand")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other"))
+ (eq_attr "autodetect_type" "alu_shift_mul_op3")
+ (if_then_else (match_operand 3 "const_2_4_8_16_operand")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other"))
+ (eq_attr "autodetect_type" "alu_shift_operator1")
+ (if_then_else (match_operand 1 "alu_shift_reg_p")
+ (const_string "alu_shift_reg")
+ (if_then_else (match_operand 1 "alu_shift_operator_lsl_1_to_4")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other")))
+ (eq_attr "autodetect_type" "alu_shift_operator2")
+ (if_then_else (match_operand 2 "alu_shift_reg_p")
+ (const_string "alu_shift_reg")
+ (if_then_else (match_operand 2 "alu_shift_operator_lsl_1_to_4")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other")))
+ (eq_attr "autodetect_type" "alu_shift_operator3")
+ (if_then_else (match_operand 3 "alu_shift_reg_p")
+ (const_string "alu_shift_reg")
+ (if_then_else (match_operand 3 "alu_shift_operator_lsl_1_to_4")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other")))
+ (eq_attr "autodetect_type" "alu_shift_operator4")
+ (if_then_else (match_operand 4 "alu_shift_reg_p")
+ (const_string "alu_shift_reg")
+ (if_then_else (match_operand 4 "alu_shift_operator_lsl_1_to_4")
+ (const_string "alu_shift_imm_lsl_1to4")
+ (const_string "alu_shift_imm_other")))
+ ]
+ (const_string "untyped")))
+
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
(define_attr "mul32" "no,yes"
(define_insn_reservation "xgene1_alu" 1
(and (eq_attr "tune" "xgene1")
- (eq_attr "type" "alu_imm,alu_sreg,alu_shift_imm,\
+ (eq_attr "type" "alu_imm,alu_sreg,alu_shift_imm_lsl_1to4,alu_shift_imm_other,\
alu_ext,adc_reg,logic_imm,\
logic_reg,logic_shift_imm,clz,\
rbit,adr,mov_reg,shift_imm,\
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