RISC-V: Relax tail/j to c.j for RV64.

	2019-03-30  Andrew Waterman  <andrew@sifive.com>
	bfd/
	* elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
	rd == X_RA case.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 6662b708c16c4c2a71aec2a5f1c38b238eace950..2c630be735fa888432855ff296f10076a7109a64 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2019-03-30  Andrew Waterman  <andrew@sifive.com>
+
+       * elfnn-riscv.c (_bfd_riscv_relax_call): Only check ARCH_SIZE for
+       rd == X_RA case.
+
 2019-03-29  Max Filippov  <jcmvbkbc@gmail.com>
 
        * elf32-xtensa.c (shrink_dynamic_reloc_sections): Add

diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index bb114e59c762e3550a7ff5403c775c14ed4cef1c..dba1025994fbc2d5e37d4ac6b2feba181dd8de1c 100644 (file)
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -3416,9 +3416,12 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   auipc = bfd_get_32 (abfd, contents + rel->r_offset);
   jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
   rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
-  rvc = rvc && VALID_RVC_J_IMM (foff) && ARCH_SIZE == 32;
+  rvc = rvc && VALID_RVC_J_IMM (foff);
 
-  if (rvc && (rd == 0 || rd == X_RA))
+  /* C.J exists on RV32 and RV64, but C.JAL is RV32-only.  */
+  rvc = rvc && (rd == 0 || (rd == X_RA && ARCH_SIZE == 32));
+
+  if (rvc)
     {
       /* Relax to C.J[AL] rd, addr.  */
       r_type = R_RISCV_RVC_JUMP;