[sim] Bug fixes in shifts, plus a new test case

diff --git a/riscv/insns/srav.h b/riscv/insns/srav.h
index ec6fee88a0b2c8532a1706d7339925d5d39996ec..e01fcd58ebbf8623cc314f463946bfae6dfe9a90 100644 (file)
--- a/riscv/insns/srav.h
+++ b/riscv/insns/srav.h
@@ -1,2 +1,2 @@
 require64;
-RC = RB >> (RA & 0x3F);
+RC = sreg_t(RB) >> (RA & 0x3F);

diff --git a/riscv/insns/srlvw.h b/riscv/insns/srlvw.h
index 7e1755ffc468931077dc791bae0101a9986d9bfb..c523b59dbe1bc55a3d0cd367ce0db3dc3ad8cc97 100644 (file)
--- a/riscv/insns/srlvw.h
+++ b/riscv/insns/srlvw.h
@@ -1 +1 @@
-RC = sext32(RB >> (RA & 0x1F));
+RC = sext32((uint32_t)RB >> (RA & 0x1F));

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index 0537a1cc5e6e9d2b903d0cd8f28bbb9d104e8265..9e41c8c00851a552faaa78f34cacd4d38e437622 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1 @@
-RC = sext32(RB >> SHAMT);
+RC = sext32((uint32_t)RB >> SHAMT);