-I$(TOP)/src/mesa/math \
-I$(TOP)/src/mesa/transform \
-I$(TOP)/src/mesa/swrast \
- -I$(TOP)/src/mesa/swrast_setup
+ -I$(TOP)/src/mesa/swrast_setup \
+ -I$(TOP)/src/mesa/drivers/dri/drm/shared
##### RULES #####
#include <sys/mman.h>
#include <sys/shm.h>
-#include "sarea.h"
#include "dri_util.h"
/**
pdp->w = width;
pdp->h = height;
pdp->numClipRects = 0;
- pdp->pClipRects = (XF86DRIClipRectPtr) malloc(sizeof(XF86DRIClipRectRec));
+ pdp->pClipRects = (drm_clip_rect_t *) malloc(sizeof(drm_clip_rect_t));
(pdp->pClipRects)[0].x1 = 0;
(pdp->pClipRects)[0].y1 = 0;
(pdp->pClipRects)[0].x2 = width;
#include <inttypes.h>
#include "dri.h" /* public entry points */
-#include "sarea.h" /* for XF86DRISAREAPtr */
+#include "xf86drm.h"
+#include "drm.h"
+#include "drm_sarea.h"
#define _SOLO
int w;
int h;
int numClipRects;
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
/*@}*/
/**
int backY;
int backClipRectType;
int numBackClipRects;
- XF86DRIClipRectPtr pBackClipRects;
+ drm_clip_rect_t *pBackClipRects;
/*@}*/
/**
* - the device lock
* - the device-independent per-drawable and per-context(?) information
*/
- XF86DRISAREAPtr pSAREA;
+ drm_sarea_t *pSAREA;
/**
* \name Direct frame buffer access information
#include "GL/gl.h"
#include "GL/internal/glcore.h"
-/**
- * \brief Clip rectangle definition.
- */
-typedef struct _XF86DRIClipRect {
- unsigned short x1; /**< \brief Upper: inclusive */
- unsigned short y1; /**< \brief Left: inclusive */
- unsigned short x2; /**< \brief Lower: exclusive */
- unsigned short y2; /**< \brief Right: exclusive */
-} XF86DRIClipRectRec, *XF86DRIClipRectPtr;
+#include "drm.h"
+#include "drm_sarea.h"
/**
* \brief DRIDriverContext type.
*/
/*@{*/
int drmFD; /**< \brief DRM device file descriptor */
- struct _XF86DRISAREA *pSAREA;
+ drm_sarea_t *pSAREA;
unsigned int serverContext; /**< \brief DRM context only active on server */
/*@}*/
+++ /dev/null
-/**
- * \file drm.h
- * \brief Header for the Direct Rendering Manager
- *
- * This file defines the DRM device ioctls and the strucutre of respective user
- * arguments.
- *
- * \sa xf86drm.h and xf86drm.c for an user-friendlier interface.
- *
- * \author Rickard E. (Rik) Faith <faith@valinux.com>
- *
- * \par Acknowledgements:
- * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
- */
-
-/*
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-
-#ifndef _DRM_H_
-#define _DRM_H_
-
-#if defined(__linux__)
-#include <linux/config.h>
-#include <asm/ioctl.h> /* For _IO* macros */
-#define DRM_IOCTL_NR(n) _IOC_NR(n)
-#define DRM_IOC_VOID _IOC_NONE
-#define DRM_IOC_READ _IOC_READ
-#define DRM_IOC_WRITE _IOC_WRITE
-#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
-#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
-#elif defined(__FreeBSD__) || defined(__NetBSD__)
-#if defined(__FreeBSD__) && defined(XFree86Server)
-/* Prevent name collision when including sys/ioccom.h */
-#undef ioctl
-#include <sys/ioccom.h>
-#define ioctl(a,b,c) xf86ioctl(a,b,c)
-#else
-#include <sys/ioccom.h>
-#endif /* __FreeBSD__ && xf86ioctl */
-#define DRM_IOCTL_NR(n) ((n) & 0xff)
-#define DRM_IOC_VOID IOC_VOID
-#define DRM_IOC_READ IOC_OUT
-#define DRM_IOC_WRITE IOC_IN
-#define DRM_IOC_READWRITE IOC_INOUT
-#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
-#endif
-
-#define XFREE86_VERSION(major,minor,patch,snap) \
- ((major << 16) | (minor << 8) | patch)
-
-#ifndef CONFIG_XFREE86_VERSION
-#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
-#endif
-
-#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
-#define DRM_PROC_DEVICES "/proc/devices"
-#define DRM_PROC_MISC "/proc/misc"
-#define DRM_PROC_DRM "/proc/drm"
-#define DRM_DEV_DRM "/dev/drm"
-#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
-#define DRM_DEV_UID 0
-#define DRM_DEV_GID 0
-#endif
-
-#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
-#define DRM_MAJOR 226
-#define DRM_MAX_MINOR 15
-#endif
-#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
-#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
-#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
-#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
-
-#define _DRM_LOCK_HELD 0x80000000 /**< Hardware lock is held */
-#define _DRM_LOCK_CONT 0x40000000 /**< Hardware lock is contended */
-#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
-#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
-#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
-
-
-typedef unsigned long drm_handle_t;
-typedef unsigned int drm_context_t;
-typedef unsigned int drm_drawable_t;
-typedef unsigned int drm_magic_t;
-
-
-/**
- * Cliprect.
- *
- * \warning: If you change this structure, make sure you change
- * XF86DRIClipRectRec in the server as well
- *
- * \note KW: Actually it's illegal to change either for
- * backwards-compatibility reasons.
- */
-typedef struct drm_clip_rect {
- unsigned short x1;
- unsigned short y1;
- unsigned short x2;
- unsigned short y2;
-} drm_clip_rect_t;
-
-
-/**
- * Texture region,
- */
-typedef struct drm_tex_region {
- unsigned char next;
- unsigned char prev;
- unsigned char in_use;
- unsigned char padding;
- unsigned int age;
-} drm_tex_region_t;
-
-
-/**
- * \brief DRM_IOCTL_VERSION ioctl argument type.
- *
- * \sa drmGetVersion().
- */
-typedef struct drm_version {
- int version_major; /**< Major version */
- int version_minor; /**< Minor version */
- int version_patchlevel;/**< Patch level */
- size_t name_len; /**< Length of name buffer */
- char *name; /**< Name of driver */
- size_t date_len; /**< Length of date buffer */
- char *date; /**< User-space buffer to hold date */
- size_t desc_len; /**< Length of desc buffer */
- char *desc; /**< User-space buffer to hold desc */
-} drm_version_t;
-
-
-/**
- * \brief DRM_IOCTL_GET_UNIQUE ioctl argument type.
- *
- * \sa drmGetBusid() and drmSetBusId().
- */
-typedef struct drm_unique {
- size_t unique_len; /**< Length of unique */
- char *unique; /**< Unique name for driver instantiation */
-} drm_unique_t;
-
-
-typedef struct drm_list {
- int count; /**< Length of user-space structures */
- drm_version_t *version;
-} drm_list_t;
-
-
-typedef struct drm_block {
- int unused;
-} drm_block_t;
-
-
-/**
- * \brief DRM_IOCTL_CONTROL ioctl argument type.
- *
- * \sa drmCtlInstHandler() and drmCtlUninstHandler().
- */
-typedef struct drm_control {
- enum {
- DRM_ADD_COMMAND,
- DRM_RM_COMMAND,
- DRM_INST_HANDLER,
- DRM_UNINST_HANDLER
- } func;
- int irq;
-} drm_control_t;
-
-
-/**
- * \brief Type of memory to map.
- */
-typedef enum drm_map_type {
- _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
- _DRM_REGISTERS = 1, /**< no caching, no core dump */
- _DRM_SHM = 2, /**< shared, cached */
- _DRM_AGP = 3, /**< AGP/GART */
- _DRM_SCATTER_GATHER = 4 /**< Scatter/gather memory for PCI DMA */
-} drm_map_type_t;
-
-
-/**
- * \brief Memory mapping flags.
- */
-typedef enum drm_map_flags {
- _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
- _DRM_READ_ONLY = 0x02,
- _DRM_LOCKED = 0x04, /**< shared, cached, locked */
- _DRM_KERNEL = 0x08, /**< kernel requires access */
- _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
- _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
- _DRM_REMOVABLE = 0x40 /**< Removable mapping */
-} drm_map_flags_t;
-
-
-typedef struct drm_ctx_priv_map {
- unsigned int ctx_id; /**< Context requesting private mapping */
- void *handle; /**< Handle of map */
-} drm_ctx_priv_map_t;
-
-
-/**
- * \brief DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
- * argument type.
- *
- * \sa drmAddMap().
- */
-typedef struct drm_map {
- unsigned long offset; /**< Requested physical address (0 for SAREA)*/
- unsigned long size; /**< Requested physical size (bytes) */
- drm_map_type_t type; /**< Type of memory to map */
- drm_map_flags_t flags; /**< Flags */
- void *handle; /**< User-space: "Handle" to pass to mmap() */
- /**< Kernel-space: kernel-virtual address */
- int mtrr; /**< MTRR slot used */
- /* Private data */
-} drm_map_t;
-
-
-/**
- * \brief DRM_IOCTL_GET_CLIENT ioctl argument type.
- */
-typedef struct drm_client {
- int idx; /**< Which client desired? */
- int auth; /**< Is client authenticated? */
- unsigned long pid; /**< Process ID */
- unsigned long uid; /**< User ID */
- unsigned long magic; /**< Magic */
- unsigned long iocs; /**< Ioctl count */
-} drm_client_t;
-
-
-typedef enum {
- _DRM_STAT_LOCK,
- _DRM_STAT_OPENS,
- _DRM_STAT_CLOSES,
- _DRM_STAT_IOCTLS,
- _DRM_STAT_LOCKS,
- _DRM_STAT_UNLOCKS,
- _DRM_STAT_VALUE, /**< Generic value */
- _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
- _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
-
- _DRM_STAT_IRQ, /**< IRQ */
- _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
- _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
- _DRM_STAT_DMA, /**< DMA */
- _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
- _DRM_STAT_MISSED /**< Missed DMA opportunity */
-
- /* Add to the *END* of the list */
-} drm_stat_type_t;
-
-
-/**
- * \brief DRM_IOCTL_GET_STATS ioctl argument type.
- */
-typedef struct drm_stats {
- unsigned long count;
- struct {
- unsigned long value;
- drm_stat_type_t type;
- } data[15];
-} drm_stats_t;
-
-
-/**
- * \brief Hardware locking flags.
- */
-typedef enum drm_lock_flags {
- _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
- _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
- _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
- _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
- /* These *HALT* flags aren't supported yet
- -- they will be used to support the
- full-screen DGA-like mode. */
- _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
- _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
-} drm_lock_flags_t;
-
-
-/**
- * \brief DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
- *
- * \sa drmGetLock() and drmUnlock().
- */
-typedef struct drm_lock {
- int context;
- drm_lock_flags_t flags;
-} drm_lock_t;
-
-
-/**
- * \brief DMA flags
- *
- * \warning
- * These values \e must match xf86drm.h.
- *
- * \sa drm_dma.
- */
-typedef enum drm_dma_flags {
- /* Flags for DMA buffer dispatch */
- _DRM_DMA_BLOCK = 0x01, /**<
- * Block until buffer dispatched.
- *
- * \note The buffer may not yet have
- * been processed by the hardware --
- * getting a hardware lock with the
- * hardware quiescent will ensure
- * that the buffer has been
- * processed.
- */
- _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
- _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
-
- /* Flags for DMA buffer request */
- _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
- _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
- _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
-} drm_dma_flags_t;
-
-
-/**
- * \brief DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
- *
- * \sa drmAddBufs().
- */
-typedef struct drm_buf_desc {
- int count; /**< Number of buffers of this size */
- int size; /**< Size in bytes */
- int low_mark; /**< Low water mark */
- int high_mark; /**< High water mark */
- enum {
- _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
- _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
- _DRM_SG_BUFFER = 0x04 /**< Scatter/gather memory buffer */
- } flags;
- unsigned long agp_start; /**<
- * Start address of where the AGP buffers are
- * in the AGP aperture
- */
-} drm_buf_desc_t;
-
-
-/**
- * \brief DRM_IOCTL_INFO_BUFS ioctl argument type.
- */
-typedef struct drm_buf_info {
- int count; /**< Entries in list */
- drm_buf_desc_t *list;
-} drm_buf_info_t;
-
-
-/**
- * \brief DRM_IOCTL_FREE_BUFS ioctl argument type.
- */
-typedef struct drm_buf_free {
- int count;
- int *list;
-} drm_buf_free_t;
-
-
-/**
- * \brief Buffer information
- *
- * \sa drm_buf_map.
- */
-typedef struct drm_buf_pub {
- int idx; /**< Index into the master buffer list */
- int total; /**< Buffer size */
- int used; /**< Amount of buffer in use (for DMA) */
- void *address; /**< Address of buffer */
-} drm_buf_pub_t;
-
-
-/**
- * \brief DRM_IOCTL_MAP_BUFS ioctl argument type.
- */
-typedef struct drm_buf_map {
- int count; /**< Length of the buffer list */
- void *virtual; /**< Mmap'd area in user-virtual */
- drm_buf_pub_t *list; /**< Buffer information */
-} drm_buf_map_t;
-
-
-/**
- * \brief DRM_IOCTL_DMA ioctl argument type.
- *
- * Indices here refer to the offset into the buffer list in drm_buf_get.
- *
- * \sa drmDMA().
- */
-typedef struct drm_dma {
- int context; /**< Context handle */
- int send_count; /**< Number of buffers to send */
- int *send_indices; /**< List of handles to buffers */
- int *send_sizes; /**< Lengths of data to send */
- drm_dma_flags_t flags; /**< Flags */
- int request_count; /**< Number of buffers requested */
- int request_size; /**< Desired size for buffers */
- int *request_indices; /**< Buffer information */
- int *request_sizes;
- int granted_count; /**< Number of buffers granted */
-} drm_dma_t;
-
-
-typedef enum {
- _DRM_CONTEXT_PRESERVED = 0x01,
- _DRM_CONTEXT_2DONLY = 0x02
-} drm_ctx_flags_t;
-
-
-/**
- * \brief DRM_IOCTL_ADD_CTX ioctl argument type.
- *
- * \sa drmCreateContext() and drmDestroyContext().
- */
-typedef struct drm_ctx {
- drm_context_t handle;
- drm_ctx_flags_t flags;
-} drm_ctx_t;
-
-
-/**
- * \brief DRM_IOCTL_RES_CTX ioctl argument type.
- */
-typedef struct drm_ctx_res {
- int count;
- drm_ctx_t *contexts;
-} drm_ctx_res_t;
-
-
-/**
- * \brief DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
- */
-typedef struct drm_draw {
- drm_drawable_t handle;
-} drm_draw_t;
-
-
-/**
- * \brief DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
- */
-typedef struct drm_auth {
- drm_magic_t magic;
-} drm_auth_t;
-
-
-/**
- * \brief DRM_IOCTL_IRQ_BUSID ioctl argument type.
- *
- * \sa drmGetInterruptFromBusID().
- */
-typedef struct drm_irq_busid {
- int irq; /**< IRQ number */
- int busnum; /**< bus number */
- int devnum; /**< device number */
- int funcnum; /**< function number */
-} drm_irq_busid_t;
-
-
-typedef enum {
- _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
- _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
- _DRM_VBLANK_SIGNAL = 0x8000 /**< Send signal instead of blocking */
-} drm_vblank_seq_type_t;
-
-
-#define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL
-
-
-struct drm_wait_vblank_request {
- drm_vblank_seq_type_t type;
- unsigned int sequence;
- unsigned long signal;
-};
-
-
-struct drm_wait_vblank_reply {
- drm_vblank_seq_type_t type;
- unsigned int sequence;
- long tval_sec;
- long tval_usec;
-};
-
-
-/**
- * \brief DRM_IOCTL_WAIT_VBLANK ioctl argument type.
- *
- * \sa drmWaitVBlank().
- */
-typedef union drm_wait_vblank {
- struct drm_wait_vblank_request request;
- struct drm_wait_vblank_reply reply;
-} drm_wait_vblank_t;
-
-
-/**
- * \brief DRM_IOCTL_AGP_ENABLE ioctl argument type.
- *
- * \sa drmAgpEnable().
- */
-typedef struct drm_agp_mode {
- unsigned long mode; /**< AGP mode */
-} drm_agp_mode_t;
-
-
-/**
- * \brief DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
- *
- * \sa drmAgpAlloc() and drmAgpFree().
- */
-typedef struct drm_agp_buffer {
- unsigned long size; /**< In bytes -- will round to page boundary */
- unsigned long handle; /**< Used for binding / unbinding */
- unsigned long type; /**< Type of memory to allocate */
- unsigned long physical; /**< Physical used by i810 */
-} drm_agp_buffer_t;
-
-
-/**
- * \brief DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
- *
- * \sa drmAgpBind() and drmAgpUnbind().
- */
-typedef struct drm_agp_binding {
- unsigned long handle; /**< From drm_agp_buffer */
- unsigned long offset; /**< In bytes -- will round to page boundary */
-} drm_agp_binding_t;
-
-
-/**
- * \brief DRM_IOCTL_AGP_INFO ioctl argument type.
- *
- * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
- * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
- * drmAgpVendorId() and drmAgpDeviceId().
- */
-typedef struct drm_agp_info {
- int agp_version_major;
- int agp_version_minor;
- unsigned long mode;
- unsigned long aperture_base; /* physical address */
- unsigned long aperture_size; /* bytes */
- unsigned long memory_allowed; /* bytes */
- unsigned long memory_used;
-
- /* PCI information */
- unsigned short id_vendor;
- unsigned short id_device;
-} drm_agp_info_t;
-
-
-/**
- * \brief DRM_IOCTL_SG_ALLOC ioctl argument type.
- */
-typedef struct drm_scatter_gather {
- unsigned long size; /**< In bytes -- will round to page boundary */
- unsigned long handle; /**< Used for mapping / unmapping */
-} drm_scatter_gather_t;
-
-
-#define DRM_IOCTL_BASE 'd'
-#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
-#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
-#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
-#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
-
-#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
-#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
-#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
-#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
-#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
-#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
-#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
-
-#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
-#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
-#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
-#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
-#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
-#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
-#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
-#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
-#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
-#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
-#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
-
-#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
-
-#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
-#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
-
-#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
-#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
-#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
-#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
-#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
-#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
-#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
-#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
-#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
-#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
-#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
-#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
-#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
-
-#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
-#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
-#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
-#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
-#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
-#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
-#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
-#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
-
-#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
-#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
-
-#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
-
-/**
- * Device specific ioctls should only be in their respective headers
- * The device specific ioctl range is from 0x40 to 0x79.
- *
- * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
- * drmCommandReadWrite().
- */
-#define DRM_COMMAND_BASE 0x40
-
-#endif
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-/* $Id: miniglx_events.c,v 1.1 2003/08/22 20:11:43 brianp Exp $ */
+/* $Id: miniglx_events.c,v 1.2 2004/03/11 20:35:38 jonsmirl Exp $ */
#include <assert.h>
#include "miniglxP.h"
#include "xf86drm.h"
-#include "sarea.h"
+#include "dri_util.h"
#define MINIGLX_FIFO_NAME "/tmp/miniglx.fifo"
+++ /dev/null
-/**
- * \file sarea.h
- * \brief SAREA definitions.
- *
- * The SAREA is a memory region is shared by the DRM device, the X server and
- * the clients.
- *
- * This file defines its layout in user space.
- *
- * \author Kevin E. Martin <kevin@precisioninsight.com>
- * \author Jens Owen <jens@tungstengraphics.com>
- * \author Rickard E. (Rik) Faith <faith@valinux.com>
- */
-
-/*
- * Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef _SAREA_H_
-#define _SAREA_H_
-
-#include "xf86drm.h"
-
-/* SAREA area needs to be at least a page */
-#if defined(__alpha__)
-#define SAREA_MAX 0x2000
-#elif defined(__ia64__)
-#define SAREA_MAX 0x10000 /* 64kB */
-#else
-/* Intel 830M driver needs at least 8k SAREA */
-#define SAREA_MAX 0x2000
-#endif
-
-#define SAREA_MAX_DRAWABLES 256
-
-#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
-
-/**
- * \brief SAREA per drawable information.
- *
- * \sa _XF86DRISAREA.
- */
-typedef struct _XF86DRISAREADrawable {
- unsigned int stamp;
- unsigned int flags;
-} XF86DRISAREADrawableRec, *XF86DRISAREADrawablePtr;
-
-/**
- * \brief SAREA frame information.
- *
- * \sa _XF86DRISAREA.
- */
-typedef struct _XF86DRISAREAFrame {
- unsigned int x;
- unsigned int y;
- unsigned int width;
- unsigned int height;
- unsigned int fullscreen;
-} XF86DRISAREAFrameRec, *XF86DRISAREAFramePtr;
-
-/**
- * \brief SAREA definition.
- */
-typedef struct _XF86DRISAREA {
- /** first thing is always the DRM locking structure */
- drmLock lock;
- /** \todo Use readers/writer lock for drawable_lock */
- drmLock drawable_lock;
- XF86DRISAREADrawableRec drawableTable[SAREA_MAX_DRAWABLES];
- XF86DRISAREAFrameRec frame;
- drmContext dummy_context;
-} XF86DRISAREARec, *XF86DRISAREAPtr;
-
-#endif
TOP = ../../../../..
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
MESA_MODULES = $(TOP)/src/mesa/mesa.a
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
{
FFBDRIPtr gDRIPriv = (FFBDRIPtr) fmesa->driScreen->pDevPriv;
ffb_fbcPtr ffb = fmesa->regs;
- XF86DRIClipRectPtr box = dPriv->pClipRects;
+ drm_clip_rect_t *box = dPriv->pClipRects;
int nc = dPriv->numClipRects;
cy = dPriv->h - cy - cheight;
} ffb_dri_state_t;
#define FFB_DRISHARE(SAREA) \
- ((ffb_dri_state_t *) (((char *)(SAREA)) + sizeof(XF86DRISAREARec)))
+ ((ffb_dri_state_t *) (((char *)(SAREA)) + sizeof(drm_sarea_t)))
typedef struct {
drmHandle hFbcRegs;
-# $Id: Makefile.solo,v 1.2 2004/01/20 02:49:27 brianp Exp $
+# $Id: Makefile.solo,v 1.3 2004/03/11 20:35:38 jonsmirl Exp $
# Mesa 3-D graphics library
# Version: 5.0
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
gammaContextPtr gmesa;
gammaScreenPtr gammascrn;
GLINTSAREADRIPtr saPriv=(GLINTSAREADRIPtr)(((char*)sPriv->pSAREA)+
- sizeof(XF86DRISAREARec));
+ sizeof(drm_sarea_t));
struct dd_function_table functions;
gmesa = (gammaContextPtr) CALLOC( sizeof(*gmesa) );
/* Mirrors of some DRI state
*/
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
int driFd;
GLuint numClipRects; /* Cliprects for the draw buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
dmaBuf buf; /* DMA buffer for regular cmds */
int bufIndex;
int src, dst, x0, y0, x1, h;
int i;
int nRect = dPriv->numClipRects;
- XF86DRIClipRectPtr pRect = dPriv->pClipRects;
+ drm_clip_rect_t *pRect = dPriv->pClipRects;
__DRIscreenPrivate *driScrnPriv = gmesa->driScreen;
GLINTDRIPtr gDRIPriv = (GLINTDRIPtr)driScrnPriv->pDevPriv;
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
int drawX; /* origin of drawable in draw buffer */
int drawY;
GLuint numClipRects; /* cliprects for that buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
int lastSwap;
int texAge;
GLboolean scissor;
- XF86DRIClipRectRec draw_rect;
- XF86DRIClipRectRec scissor_rect;
+ drm_clip_rect_t draw_rect;
+ drm_clip_rect_t scissor_rect;
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
int driFd;
__DRIdrawablePrivate *driDrawable;
for (i = 0 ; i < imesa->numClipRects ; )
{
int nr = MIN2(i + I810_NR_SAREA_CLIPRECTS, imesa->numClipRects);
- XF86DRIClipRectPtr box = imesa->pClipRects;
- XF86DRIClipRectPtr b = imesa->sarea->boxes;
+ drm_clip_rect_t *box = imesa->pClipRects;
+ drm_clip_rect_t *b = imesa->sarea->boxes;
int n = 0;
if (!all) {
}
} else {
for ( ; i < nr ; i++) {
- *b++ = *(XF86DRIClipRectPtr)&box[i];
+ *b++ = box[i];
n++;
}
}
void i810CopyBuffer( const __DRIdrawablePrivate *dPriv )
{
i810ContextPtr imesa;
- XF86DRIClipRectPtr pbox;
+ drm_clip_rect_t *pbox;
int nbox, i, tmp;
assert(dPriv);
for (i = 0 ; i < nbox ; )
{
int nr = MIN2(i + I810_NR_SAREA_CLIPRECTS, dPriv->numClipRects);
- XF86DRIClipRectRec *b = (XF86DRIClipRectRec *)imesa->sarea->boxes;
+ drm_clip_rect_t *b = imesa->sarea->boxes;
imesa->sarea->nbox = nr - i;
LOCK_HARDWARE( imesa );
if (dPriv->pClipRects) {
- *(XF86DRIClipRectRec *)imesa->sarea->boxes = dPriv->pClipRects[0];
+ *imesa->sarea->boxes = dPriv->pClipRects[0];
imesa->sarea->nbox = 1;
}
ret = drmCommandNone(imesa->driFd, DRM_I810_FLIP);
-static int intersect_rect( XF86DRIClipRectPtr out,
- XF86DRIClipRectPtr a,
- XF86DRIClipRectPtr b )
+static int intersect_rect( drm_clip_rect_t *out,
+ drm_clip_rect_t *a,
+ drm_clip_rect_t *b )
{
*out = *a;
if (b->x1 > out->x1) out->x1 = b->x1;
void i810FlushPrimsLocked( i810ContextPtr imesa )
{
- XF86DRIClipRectPtr pbox = (XF86DRIClipRectPtr)imesa->pClipRects;
+ drm_clip_rect_t *pbox = imesa->pClipRects;
int nbox = imesa->numClipRects;
drmBufPtr buffer = imesa->vertex_buffer;
I810SAREAPtr sarea = imesa->sarea;
for (i = 0 ; i < nbox ; )
{
int nr = MIN2(i + I810_NR_SAREA_CLIPRECTS, nbox);
- XF86DRIClipRectPtr b = sarea->boxes;
+ drm_clip_rect_t *b = sarea->boxes;
if (imesa->scissor) {
sarea->nbox = 0;
unsigned int dirty;
unsigned int nbox;
- XF86DRIClipRectRec boxes[I810_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
/* Maintain an LRU of contiguous regions of texture space. If
* you think you own a region of texture memory, and it has an
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
int drawX; /* origin of drawable in draw buffer */
int drawY;
GLuint numClipRects; /* cliprects for that buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
int lastSwap;
int texAge;
int do_irqs;
GLboolean scissor;
- XF86DRIClipRectRec draw_rect;
- XF86DRIClipRectRec scissor_rect;
+ drm_clip_rect_t draw_rect;
+ drm_clip_rect_t scissor_rect;
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
int driFd;
__DRIdrawablePrivate *driDrawable;
for (i = 0 ; i < imesa->numClipRects ; )
{
int nr = MIN2(i + I830_NR_SAREA_CLIPRECTS, imesa->numClipRects);
- XF86DRIClipRectRec *box = imesa->pClipRects;
+ drm_clip_rect_t *box = imesa->pClipRects;
drm_clip_rect_t *b = (drm_clip_rect_t *)imesa->sarea->boxes;
int n = 0;
void i830CopyBuffer( const __DRIdrawablePrivate *dPriv )
{
i830ContextPtr imesa;
- XF86DRIClipRectPtr pbox;
+ drm_clip_rect_t *pbox;
int nbox, i, tmp;
assert(dPriv);
for (i = 0 ; i < nbox ; )
{
int nr = MIN2(i + I830_NR_SAREA_CLIPRECTS, dPriv->numClipRects);
- XF86DRIClipRectRec *b = (XF86DRIClipRectRec *)imesa->sarea->boxes;
+ drm_clip_rect_t *b = (drm_clip_rect_t *)imesa->sarea->boxes;
imesa->sarea->nbox = nr - i;
imesa->perf_boxes = 0;
if (dPriv->pClipRects) {
- *(XF86DRIClipRectRec *)imesa->sarea->boxes = dPriv->pClipRects[0];
+ *(drm_clip_rect_t *)imesa->sarea->boxes = dPriv->pClipRects[0];
imesa->sarea->nbox = 1;
}
void i830FlushPrimsLocked( i830ContextPtr imesa )
{
- XF86DRIClipRectPtr pbox = (XF86DRIClipRectPtr)imesa->pClipRects;
+ drm_clip_rect_t *pbox = imesa->pClipRects;
int nbox = imesa->numClipRects;
drmBufPtr buffer = imesa->vertex_buffer;
I830SAREAPtr sarea = imesa->sarea;
}
for (i = 0 ; i < nbox ; i = nr ) {
- XF86DRIClipRectPtr b = sarea->boxes;
+ drm_clip_rect_t *b = sarea->boxes;
int j;
nr = MIN2(i + I830_NR_SAREA_CLIPRECTS, nbox);
unsigned int dirty;
unsigned int nbox;
- XF86DRIClipRectRec boxes[I830_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS];
/* Maintain an LRU of contiguous regions of texture space. If
* you think you own a region of texture memory, and it has an
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
* Authors:
* Gareth Hughes <gareth@valinux.com>
* Leif Delgass <ldelgass@retinalburn.net>
- * José Fonseca <j_r_fonseca@yahoo.co.uk>
+ * Jos�Fonseca <j_r_fonseca@yahoo.co.uk>
*/
#include "glheader.h"
mach64Screen->driScreen->myNum, "mach64");
mmesa->sarea = (ATISAREAPrivPtr)((char *)driScreen->pSAREA +
- sizeof(XF86DRISAREARec));
+ sizeof(drm_sarea_t));
mmesa->CurrentTexObj[0] = NULL;
mmesa->CurrentTexObj[1] = NULL;
* Authors:
* Gareth Hughes <gareth@valinux.com>
* Leif Delgass <ldelgass@retinalburn.net>
- * José Fonseca <j_r_fonseca@yahoo.co.uk>
+ * Jos�Fonseca <j_r_fonseca@yahoo.co.uk>
*/
#ifndef __MACH64_CONTEXT_H__
typedef void (*mach64_point_func)( mach64ContextPtr,
mach64Vertex * );
-#if TEXMEM
+#ifdef TEXMEM
struct mach64_texture_object {
driTextureObject base;
/* Texture object bookkeeping
*/
mach64TexObjPtr CurrentTexObj[2];
-#if TEXMEM
+#ifdef TEXMEM
unsigned nr_heaps;
driTexHeap * texture_heaps[ R128_NR_TEX_HEAPS ];
driTextureObject swapped;
GLint readOffset, readPitch;
GLuint numClipRects; /* Cliprects for the draw buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
GLint scissor;
- XF86DRIClipRectRec ScissorRect; /* Current software scissor */
+ drm_clip_rect_t ScissorRect; /* Current software scissor */
/* Mirrors of some DRI state
*/
unsigned int lastStamp; /* mirror driDrawable->lastStamp */
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
int driFd;
mach64ScreenPtr mach64Screen; /* Screen private DRI data */
* Authors:
* Gareth Hughes <gareth@valinux.com>
* Leif Delgass <ldelgass@retinalburn.net>
- * José Fonseca <j_r_fonseca@yahoo.co.uk>
+ * Jos�Fonseca <j_r_fonseca@yahoo.co.uk>
*/
#include <errno.h>
void mach64FlushVerticesLocked( mach64ContextPtr mmesa )
{
- XF86DRIClipRectPtr pbox = mmesa->pClipRects;
+ drm_clip_rect_t *pbox = mmesa->pClipRects;
int nbox = mmesa->numClipRects;
void *buffer = mmesa->vert_buf;
int count = mmesa->vert_used;
for ( i = 0 ; i < nbox ; ) {
int nr = MIN2( i + MACH64_NR_SAREA_CLIPRECTS, nbox );
- XF86DRIClipRectPtr b = mmesa->sarea->boxes;
+ drm_clip_rect_t *b = mmesa->sarea->boxes;
int discard = 0;
mmesa->sarea->nbox = nr - i;
{
mach64ContextPtr mmesa;
GLint nbox, i, ret;
- XF86DRIClipRectPtr pbox;
+ drm_clip_rect_t *pbox;
GLboolean missed_target;
assert(dPriv);
for ( i = 0 ; i < nbox ; ) {
GLint nr = MIN2( i + MACH64_NR_SAREA_CLIPRECTS , nbox );
- XF86DRIClipRectPtr b = mmesa->sarea->boxes;
+ drm_clip_rect_t *b = mmesa->sarea->boxes;
GLint n = 0;
for ( ; i < nr ; i++ ) {
GLuint color;
GLint nbox;
GLint x1, y1, x2, y2;
- XF86DRIClipRectPtr b = mmesa->sarea->boxes;
+ drm_clip_rect_t *b = mmesa->sarea->boxes;
/* save cliprects */
nbox = mmesa->sarea->nbox;
for ( i = 0 ; i < mmesa->numClipRects ; ) {
int nr = MIN2( i + MACH64_NR_SAREA_CLIPRECTS, mmesa->numClipRects );
- XF86DRIClipRectPtr box = mmesa->pClipRects;
- XF86DRIClipRectPtr b = mmesa->sarea->boxes;
+ drm_clip_rect_t *box = mmesa->pClipRects;
+ drm_clip_rect_t *b = mmesa->sarea->boxes;
GLint n = 0;
if ( !all ) {
* Authors:
* Gareth Hughes <gareth@valinux.com>
* Leif Delgass <ldelgass@retinalburn.net>
- * José Fonseca <j_r_fonseca@yahoo.co.uk>
+ * Jos�Fonseca <j_r_fonseca@yahoo.co.uk>
*/
#include "mach64_context.h"
switch ( mode ) {
case GL_FRONT_LEFT:
mmesa->numClipRects = dPriv->numClipRects;
- mmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pClipRects;
+ mmesa->pClipRects = dPriv->pClipRects;
mmesa->drawX = dPriv->x;
mmesa->drawY = dPriv->y;
break;
case GL_BACK_LEFT:
if ( dPriv->numBackClipRects == 0 ) {
mmesa->numClipRects = dPriv->numClipRects;
- mmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pClipRects;
+ mmesa->pClipRects = dPriv->pClipRects;
mmesa->drawX = dPriv->x;
mmesa->drawY = dPriv->y;
} else {
mmesa->numClipRects = dPriv->numBackClipRects;
- mmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pBackClipRects;
+ mmesa->pClipRects = dPriv->pBackClipRects;
mmesa->drawX = dPriv->backX;
mmesa->drawY = dPriv->backY;
}
/* The current cliprects, or a subset thereof.
*/
- XF86DRIClipRectRec boxes[MACH64_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
unsigned int nbox;
/* Counter for throttling of rendering clients.
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
int drawX, drawY; /* origin of drawable in draw buffer */
int lastX, lastY; /* detect DSTORG bug */
GLuint numClipRects; /* cliprects for the draw buffer */
- XF86DRIClipRectPtr pClipRects;
- XF86DRIClipRectRec draw_rect;
- XF86DRIClipRectRec scissor_rect;
+ drm_clip_rect_t *pClipRects;
+ drm_clip_rect_t draw_rect;
+ drm_clip_rect_t scissor_rect;
int scissor;
- XF86DRIClipRectRec tmp_boxes[2][MGA_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t tmp_boxes[2][MGA_NR_SAREA_CLIPRECTS];
/* Texture aging and DMA based aging.
/* Mirrors of some DRI state.
*/
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
int driFd;
__DRIdrawablePrivate *driDrawable;
__DRIdrawablePrivate *driReadable;
for (i = 0 ; i < mmesa->numClipRects ; )
{
int nr = MIN2(i + MGA_NR_SAREA_CLIPRECTS, mmesa->numClipRects);
- XF86DRIClipRectPtr box = mmesa->pClipRects;
- XF86DRIClipRectPtr b = mmesa->sarea->boxes;
+ drm_clip_rect_t *box = mmesa->pClipRects;
+ drm_clip_rect_t *b = mmesa->sarea->boxes;
int n = 0;
if (!all) {
}
} else {
for ( ; i < nr ; i++) {
- *b++ = *(XF86DRIClipRectPtr)&box[i];
+ *b++ = box[i];
n++;
}
}
void mgaCopyBuffer( const __DRIdrawablePrivate *dPriv )
{
mgaContextPtr mmesa;
- XF86DRIClipRectPtr pbox;
+ drm_clip_rect_t *pbox;
GLint nbox;
GLint ret;
GLint i;
for (i = 0 ; i < nbox ; )
{
int nr = MIN2(i + MGA_NR_SAREA_CLIPRECTS, dPriv->numClipRects);
- XF86DRIClipRectPtr b = mmesa->sarea->boxes;
+ drm_clip_rect_t *b = mmesa->sarea->boxes;
mmesa->sarea->nbox = nr - i;
}
-static GLboolean intersect_rect( XF86DRIClipRectPtr out,
- const XF86DRIClipRectPtr a,
- const XF86DRIClipRectPtr b )
+static GLboolean intersect_rect( drm_clip_rect_t *out,
+ const drm_clip_rect_t *a,
+ const drm_clip_rect_t *b )
{
*out = *a;
if (b->x1 > out->x1) out->x1 = b->x1;
void mgaFlushVerticesLocked( mgaContextPtr mmesa )
{
- XF86DRIClipRectPtr pbox = mmesa->pClipRects;
+ drm_clip_rect_t *pbox = mmesa->pClipRects;
int nbox = mmesa->numClipRects;
drmBufPtr buffer = mmesa->vertex_dma_buffer;
drmMGAVertex vertex;
for (i = 0 ; i < nbox ; )
{
int nr = MIN2(i + MGA_NR_SAREA_CLIPRECTS, nbox);
- XF86DRIClipRectPtr b = mmesa->sarea->boxes;
+ drm_clip_rect_t *b = mmesa->sarea->boxes;
int discard = 0;
if (mmesa->scissor) {
__DRIdrawablePrivate *driDrawable = mmesa->driDrawable;
if (driDrawable->numClipRects == 0) {
- static XF86DRIClipRectRec zeroareacliprect = {0,0,0,0};
+ static drm_clip_rect_t zeroareacliprect = {0,0,0,0};
mmesa->numClipRects = 1;
mmesa->pClipRects = &zeroareacliprect;
} else {
if (driDrawable->numBackClipRects == 0)
{
if (driDrawable->numClipRects == 0) {
- static XF86DRIClipRectRec zeroareacliprect = {0,0,0,0};
+ static drm_clip_rect_t zeroareacliprect = {0,0,0,0};
mmesa->numClipRects = 1;
mmesa->pClipRects = &zeroareacliprect;
} else {
#include "mga_dri.h"
#include "mga_sarea.h"
-#include "sarea.h"
-
-
/* Quiescence, locking
*/
memset( &init, 0, sizeof(drmMGAInit) );
init.func = MGA_INIT_DMA;
- init.sarea_priv_offset = sizeof(XF86DRISAREARec);
+ init.sarea_priv_offset = sizeof(drm_sarea_t);
switch ( pMga->Chipset ) {
case PCI_CHIP_MGAG550:
pMGADRI->primary.size = pMga->primary.size;
pMGADRI->buffers.handle = pMga->buffers.handle;
pMGADRI->buffers.size = pMga->buffers.size;
- pMGADRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
+ pMGADRI->sarea_priv_offset = sizeof(drm_sarea_t);
#endif
}
{
MGASAREAPrivPtr pSAREAPriv;
pSAREAPriv = (MGASAREAPrivPtr)(((char*)ctx->pSAREA) +
- sizeof(XF86DRISAREARec));
+ sizeof(drm_sarea_t));
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
}
pMGADRI->primary.size = pMga->primary.size;
pMGADRI->buffers.handle = pMga->buffers.handle;
pMGADRI->buffers.size = pMga->buffers.size;
- pMGADRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
+ pMGADRI->sarea_priv_offset = sizeof(drm_sarea_t);
print_client_msg( pMGADRI );
/* The current cliprects, or a subset thereof.
*/
- XF86DRIClipRectRec boxes[MGA_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
unsigned int nbox;
/* Information about the most recently used 3d drawable. The
unsigned int exported_nback;
int exported_back_x, exported_front_x, exported_w;
int exported_back_y, exported_front_y, exported_h;
- XF86DRIClipRectRec exported_boxes[MGA_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
/* Counters for aging textures and for client-side throttling.
*/
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
GLint readOffset, readPitch;
GLuint numClipRects; /* Cliprects for the draw buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
GLuint scissor;
- XF86DRIClipRectRec ScissorRect; /* Current software scissor */
+ drm_clip_rect_t ScissorRect; /* Current software scissor */
/* Mirrors of some DRI state
*/
unsigned int lastStamp; /* mirror driDrawable->lastStamp */
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
int driFd;
r128ScreenPtr r128Screen; /* Screen private DRI data */
void r128FlushVerticesLocked( r128ContextPtr rmesa )
{
- XF86DRIClipRectPtr pbox = rmesa->pClipRects;
+ drm_clip_rect_t *pbox = rmesa->pClipRects;
int nbox = rmesa->numClipRects;
drmBufPtr buffer = rmesa->vert_buf;
int count = rmesa->num_verts;
{
for ( i = 0 ; i < nbox ; ) {
int nr = MIN2( i + R128_NR_SAREA_CLIPRECTS, nbox );
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
int discard = 0;
rmesa->sarea->nbox = nr - i;
for ( i = 0 ; i < nbox ; ) {
GLint nr = MIN2( i + R128_NR_SAREA_CLIPRECTS , nbox );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
GLint n = 0;
for ( ; i < nr ; i++ ) {
- *b++ = *(XF86DRIClipRectRec *)&box[i];
+ *b++ = box[i];
n++;
}
rmesa->sarea->nbox = n;
for ( i = 0 ; i < rmesa->numClipRects ; ) {
GLint nr = MIN2( i + R128_NR_SAREA_CLIPRECTS , rmesa->numClipRects );
- XF86DRIClipRectPtr box = rmesa->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = rmesa->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
GLint n = 0;
if ( !all ) {
}
} else {
for ( ; i < nr ; i++ ) {
- *b++ = *(XF86DRIClipRectPtr)&box[i];
+ *b++ = box[i];
n++;
}
}
const GLdepth depth[],
const GLubyte mask[] )
{
- XF86DRIClipRectPtr pbox = rmesa->pClipRects;
+ drm_clip_rect_t *pbox = rmesa->pClipRects;
drmR128Depth d;
int nbox = rmesa->numClipRects;
int fd = rmesa->driScreen->fd;
{
for (i = 0 ; i < nbox ; ) {
int nr = MIN2( i + R128_NR_SAREA_CLIPRECTS, nbox );
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
rmesa->sarea->nbox = nr - i;
for ( ; i < nr ; i++) {
const GLdepth depth[],
const GLubyte mask[] )
{
- XF86DRIClipRectPtr pbox = rmesa->pClipRects;
+ drm_clip_rect_t *pbox = rmesa->pClipRects;
drmR128Depth d;
int nbox = rmesa->numClipRects;
int fd = rmesa->driScreen->fd;
{
for (i = 0 ; i < nbox ; ) {
int nr = MIN2( i + R128_NR_SAREA_CLIPRECTS, nbox );
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
rmesa->sarea->nbox = nr - i;
for ( ; i < nr ; i++) {
void r128ReadDepthSpanLocked( r128ContextPtr rmesa,
GLuint n, GLint x, GLint y )
{
- XF86DRIClipRectPtr pbox = rmesa->pClipRects;
+ drm_clip_rect_t *pbox = rmesa->pClipRects;
drmR128Depth d;
int nbox = rmesa->numClipRects;
int fd = rmesa->driScreen->fd;
{
for (i = 0 ; i < nbox ; ) {
int nr = MIN2( i + R128_NR_SAREA_CLIPRECTS, nbox );
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
rmesa->sarea->nbox = nr - i;
for ( ; i < nr ; i++) {
void r128ReadDepthPixelsLocked( r128ContextPtr rmesa, GLuint n,
const GLint x[], const GLint y[] )
{
- XF86DRIClipRectPtr pbox = rmesa->pClipRects;
+ drm_clip_rect_t *pbox = rmesa->pClipRects;
drmR128Depth d;
int nbox = rmesa->numClipRects;
int fd = rmesa->driScreen->fd;
{
for (i = 0 ; i < nbox ; ) {
int nr = MIN2( i + R128_NR_SAREA_CLIPRECTS, nbox );
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
rmesa->sarea->nbox = nr - i;
for ( ; i < nr ; i++) {
*
*/
-#include "sarea.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "driver.h"
#include "drm.h"
-#include "sarea.h"
#include "r128.h"
#include "r128_dri.h"
#include "r128_macros.h"
memset( &drmInfo, 0, sizeof(drmR128Init) );
drmInfo.func = DRM_R128_INIT_CCE;
- drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
+ drmInfo.sarea_priv_offset = sizeof(drm_sarea_t);
drmInfo.is_pci = info->IsPCI;
drmInfo.cce_mode = info->CCEMode;
drmInfo.cce_secure = info->CCESecure;
R128SAREAPrivPtr pSAREAPriv;
pSAREAPriv = (R128SAREAPrivPtr)(((char*)ctx->pSAREA) +
- sizeof(XF86DRISAREARec));
+ sizeof(drm_sarea_t));
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
/* This is the struct passed to radeon_dri.so for its initialization */
pR128DRI->agpTexMapSize = info->agpTexMapSize;
pR128DRI->log2AGPTexGran = info->log2AGPTexGran;
pR128DRI->agpTexOffset = info->agpTexStart;
- pR128DRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
+ pR128DRI->sarea_priv_offset = sizeof(drm_sarea_t);
return GL_TRUE;
}
#if defined(XF86DRI) | defined(_SOLO)
/* The current cliprects, or a subset thereof.
*/
- XF86DRIClipRectRec boxes[R128_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t boxes[R128_NR_SAREA_CLIPRECTS];
unsigned int nbox;
#endif
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
$(ASM_SOURCES:.S=.o)
SYMLINKS = \
- server/radeon_common.h \
server/radeon_dri.c \
server/radeon_dri.h \
server/radeon.h \
server/radeon_macros.h \
- server/radeon_reg.h \
- server/radeon_sarea.h \
+ server/radeon_reg.h
+# server/radeon_sarea.h \
+# server/radeon_common.h \
$(SYMLINKS):
GLuint primitive,
GLuint vertex_nr )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
assert(!(primitive & R200_VF_PRIM_WALK_IND));
fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__,
rmesa->store.cmd_used/4, primitive, vertex_nr);
- cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, 3 * sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 3 * sizeof(*cmd),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
GLuint primitive,
GLuint min_nr )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
GLushort *retval;
if (R200_DEBUG & DEBUG_IOCTL)
r200EmitState( rmesa );
- cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa,
+ cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa,
12 + min_nr*2,
__FUNCTION__ );
cmd[0].i = 0;
GLuint vertex_size,
GLuint offset )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (R200_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
- cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, 5 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 5 * sizeof(int),
__FUNCTION__ );
cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
GLuint nr,
GLuint offset )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
int sz = 3 + ((nr/2)*3) + ((nr&1)*2);
int i;
int *tmp;
if (R200_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s nr arrays: %d\n", __FUNCTION__, nr);
- cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, sz * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sz * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
GLint dstx, GLint dsty,
GLuint w, GLuint h )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (R200_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
assert( w < (1<<16) );
assert( h < (1<<16) );
- cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 8 * sizeof(int),
__FUNCTION__ );
void r200EmitWait( r200ContextPtr rmesa, GLuint flags )
{
if (rmesa->dri.drmMinor >= 6) {
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
- cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, 1 * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
rmesa->dri.drmMinor = sPriv->drmMinor;
rmesa->r200Screen = screen;
- rmesa->sarea = (RADEONSAREAPrivPtr)((GLubyte *)sPriv->pSAREA +
+ rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
screen->sarea_priv_offset);
screen->texSize[i],
12,
RADEON_NR_TEX_REGIONS,
- rmesa->sarea->texList[i],
- & rmesa->sarea->texAge[i],
+ (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
+ & rmesa->sarea->tex_age[i],
& rmesa->swapped,
sizeof( r200TexObj ),
(destroy_texture_object_t *) r200DestroyTexObj );
#ifdef GLX_DIRECT_RENDERING
#include <inttypes.h>
+#include "drm.h"
+#include "radeon_drm.h"
#include "dri_util.h"
-#include "radeon_common.h"
#include "texmem.h"
#include "macros.h"
};
struct r200_scissor_state {
- XF86DRIClipRectRec rect;
+ drm_clip_rect_t rect;
GLboolean enabled;
GLuint numClipRects; /* Cliprects active */
GLuint numAllocedClipRects; /* Cliprects available */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
};
struct r200_stencilbuffer_state {
brought into the
texunit. */
- drmRadeonTexImage image[6][RADEON_MAX_TEXTURE_LEVELS];
+ drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
/* Six, for the cube faces */
GLuint pp_txfilter; /* hardware register values */
__DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */
drmContext hwContext;
- drmLock *hwLock;
+ drm_hw_lock_t *hwLock;
int fd;
int drmMinor;
};
GLuint do_usleeps;
GLuint do_irqs;
GLuint irqsEmitted;
- drmRadeonIrqWait iw;
+ drm_radeon_irq_wait_t iw;
/* Clientdata textures;
*/
/* Drawable, cliprect and scissor information
*/
GLuint numClipRects; /* Cliprects for the draw buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
unsigned int lastStamp;
GLboolean lost_context;
r200ScreenPtr r200Screen; /* Screen private DRI data */
- RADEONSAREAPrivPtr sarea; /* Private SAREA data */
+ drm_radeon_sarea_t *sarea; /* Private SAREA data */
/* TCL stuff
*/
int r200FlushCmdBufLocked( r200ContextPtr rmesa, const char * caller )
{
int ret, i;
- drmRadeonCmdBuffer cmd;
+ drm_radeon_cmd_buffer_t cmd;
if (R200_DEBUG & DEBUG_IOCTL) {
fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
if (rmesa->state.scissor.enabled) {
cmd.nbox = rmesa->state.scissor.numClipRects;
- cmd.boxes = (drmClipRect *)rmesa->state.scissor.pClipRects;
+ cmd.boxes = (drm_clip_rect_t *)rmesa->state.scissor.pClipRects;
} else {
cmd.nbox = rmesa->numClipRects;
- cmd.boxes = (drmClipRect *)rmesa->pClipRects;
+ cmd.boxes = (drm_clip_rect_t *)rmesa->pClipRects;
}
ret = drmCommandWrite( rmesa->dri.fd,
rmesa->dma.flush( rmesa );
if (--region->buf->refcount == 0) {
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_DMA))
fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__,
region->buf->buf->idx);
- cmd = (drmRadeonCmdHeader *)r200AllocCmdBuf( rmesa, sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)r200AllocCmdBuf( rmesa, sizeof(*cmd),
__FUNCTION__ );
cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD;
cmd->dma.buf_idx = region->buf->buf->idx;
static CARD32 r200GetLastFrame(r200ContextPtr rmesa)
{
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
int ret;
CARD32 frame;
static void r200EmitIrqLocked( r200ContextPtr rmesa )
{
- drmRadeonIrqEmit ie;
+ drm_radeon_irq_emit_t ie;
int ret;
ie.irq_seq = &rmesa->iw.irq_seq;
static void r200WaitForFrameCompletion( r200ContextPtr rmesa )
{
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
if (rmesa->do_irqs) {
if (r200GetLastFrame(rmesa) < sarea->last_frame) {
r200ContextPtr rmesa;
GLint nbox, i, ret;
GLboolean missed_target;
- uint64_t ust;
+ int64_t ust;
assert(dPriv);
assert(dPriv->driContextPriv);
for ( i = 0 ; i < nbox ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
GLint n = 0;
for ( ; i < nr ; i++ ) {
/* Need to do this for the perf box placement:
*/
{
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
b[0] = box[0];
rmesa->sarea->nbox = 1;
}
/* Throttle the number of clear ioctls we do.
*/
while ( 1 ) {
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
int ret;
int clear;
for ( i = 0 ; i < dPriv->numClipRects ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
- drmRadeonClearType clear;
- drmRadeonClearRect depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
+ drm_radeon_clear_t clear;
+ drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
GLint n = 0;
if ( !all ) {
n--;
b = rmesa->sarea->boxes;
for ( ; n >= 0 ; n-- ) {
- depth_boxes[n].f[RADEON_CLEAR_X1] = (float)b[n].x1;
- depth_boxes[n].f[RADEON_CLEAR_Y1] = (float)b[n].y1;
- depth_boxes[n].f[RADEON_CLEAR_X2] = (float)b[n].x2;
- depth_boxes[n].f[RADEON_CLEAR_Y2] = (float)b[n].y2;
- depth_boxes[n].f[RADEON_CLEAR_DEPTH] = ctx->Depth.Clear;
+ depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
+ depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
+ depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
+ depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
+ depth_boxes[n].f[CLEAR_DEPTH] = ctx->Depth.Clear;
}
ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR,
- &clear, sizeof(drmRadeonClearType));
+ &clear, sizeof(clear));
if ( ret ) {
GET_CURRENT_CONTEXT(ctx);
r200ContextPtr rmesa;
int region_offset;
- drmRadeonMemAlloc alloc;
+ drm_radeon_mem_alloc_t alloc;
int ret;
if (R200_DEBUG & DEBUG_IOCTL)
GET_CURRENT_CONTEXT(ctx);
r200ContextPtr rmesa;
int region_offset;
- drmRadeonMemFree memfree;
+ drm_radeon_mem_free_t memfree;
int ret;
if (R200_DEBUG & DEBUG_IOCTL)
#include "r200_lock.h"
#include "xf86drm.h"
-#include "radeon_common.h"
+#include "drm.h"
+#include "radeon_drm.h"
extern void r200EmitState( r200ContextPtr rmesa );
extern void r200EmitVertexAOS( r200ContextPtr rmesa,
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
-
+#include <string.h>
+
#include "r200_context.h"
#include "r200_lock.h"
#include "r200_tex.h"
r200UpdatePageFlipping( r200ContextPtr rmesa )
{
int use_back;
- rmesa->doPageFlip = rmesa->sarea->pfAllowPageFlip;
+ rmesa->doPageFlip = rmesa->sarea->pfState;
use_back = (rmesa->glCtx->Color._DrawDestMask == BACK_LEFT_BIT);
use_back ^= (rmesa->sarea->pfCurrentPage == 1);
{
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
__DRIscreenPrivate *sPriv = rmesa->dri.screen;
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
int i;
drmGetLock( rmesa->dri.fd, rmesa->dri.hwContext, flags );
rmesa->lastStamp = dPriv->lastStamp;
}
- if ( sarea->ctxOwner != rmesa->dri.hwContext ) {
- sarea->ctxOwner = rmesa->dri.hwContext;
+ if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
+ sarea->ctx_owner = rmesa->dri.hwContext;
}
for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
/* If using new packets, can choose either verts or arrays.
* Otherwise, must use verts.
*/
+#include <string.h>
+
#include "r200_context.h"
#define R200_MAOS_VERTS 0
#if (R200_MAOS_VERTS) || (R200_OLD_PACKETS)
int src_pitch = rmesa->state.color.drawPitch * rmesa->r200Screen->cpp;
int dst_offset = r200GartOffsetFromVirtual( rmesa, pixels );
int dst_pitch = pitch * rmesa->r200Screen->cpp;
- XF86DRIClipRectRec *box = dPriv->pClipRects;
+ drm_clip_rect_t *box = dPriv->pClipRects;
int i;
r200EmitWait( rmesa, RADEON_WAIT_3D );
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
- XF86DRIClipRectPtr box = dPriv->pClipRects;
+ drm_clip_rect_t *box = dPriv->pClipRects;
int nbox = dPriv->numClipRects;
int i;
int blit_format;
static int radeon_emit_packets(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int id = (int)header.packet.packet_id;
int sz = packet[id].len;
static int radeon_emit_scalars(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
static int radeon_emit_scalars2(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
* Check: table start, end, nr, etc.
*/
static int radeon_emit_vectors(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.vectors.count;
int *data = (int *)cmdbuf->buf;
/* build in knowledge about each packet type
*/
-static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
{
int cmdsz;
int *cmd = (int *)cmdbuf->buf;
/* Check cliprects for bounds, then pass on to above:
*/
-static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
{
- XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
+ drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes;
int i = 0;
if (VERBOSE && total_changed) {
int r200SanityCmdBuffer( r200ContextPtr rmesa,
int nbox,
- XF86DRIClipRectRec *boxes )
+ drm_clip_rect_t *boxes )
{
int idx;
- drmRadeonCmdBuffer cmdbuf;
- drmRadeonCmdHeader header;
+ drm_radeon_cmd_buffer_t cmdbuf;
+ drm_radeon_cmd_header_t header;
static int inited = 0;
if (!inited) {
cmdbuf.buf = rmesa->store.cmd_buf;
cmdbuf.bufsz = rmesa->store.cmd_used;
- cmdbuf.boxes = (drmClipRect *)boxes;
+ cmdbuf.boxes = (drm_clip_rect_t *)boxes;
cmdbuf.nbox = nbox;
while ( cmdbuf.bufsz >= sizeof(header) ) {
extern int r200SanityCmdBuffer( r200ContextPtr rmesa,
int nbox,
- XF86DRIClipRectRec *boxes );
+ drm_clip_rect_t *boxes );
#endif
{
int ret;
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
gp.value = &screen->gart_buffer_offset;
screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
if ( sPriv->drmMinor >= 10 ) {
- drmRadeonSetParam sp;
+ drm_radeon_setparam_t sp;
sp.param = RADEON_SETPARAM_FB_LOCATION;
sp.value = screen->fbLocation;
screen->depthOffset = dri_priv->depthOffset;
screen->depthPitch = dri_priv->depthPitch;
- screen->texOffset[RADEON_CARD_HEAP] = dri_priv->textureOffset
+ screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
+ screen->fbLocation;
- screen->texSize[RADEON_CARD_HEAP] = dri_priv->textureSize;
- screen->logTexGranularity[RADEON_CARD_HEAP] =
+ screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
+ screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
dri_priv->log2TexGran;
if ( !screen->gartTextures.map ) {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
- screen->texOffset[RADEON_GART_HEAP] = 0;
- screen->texSize[RADEON_GART_HEAP] = 0;
- screen->logTexGranularity[RADEON_GART_HEAP] = 0;
+ screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
+ screen->texSize[RADEON_GART_TEX_HEAP] = 0;
+ screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
} else {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
- screen->texOffset[RADEON_GART_HEAP] = screen->gart_texture_offset;
- screen->texSize[RADEON_GART_HEAP] = dri_priv->gartTexMapSize;
- screen->logTexGranularity[RADEON_GART_HEAP] =
+ screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
+ screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
+ screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
dri_priv->log2GARTTexGran;
}
#ifdef GLX_DIRECT_RENDERING
-#include "dri_util.h"
#include "xf86drm.h"
-#include "radeon_common.h"
-#include "radeon_sarea.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "dri_util.h"
#include "xmlconfig.h"
typedef struct {
*/
-static GLboolean intersect_rect( XF86DRIClipRectPtr out,
- XF86DRIClipRectPtr a,
- XF86DRIClipRectPtr b )
+static GLboolean intersect_rect( drm_clip_rect_t *out,
+ drm_clip_rect_t *a,
+ drm_clip_rect_t *b )
{
*out = *a;
if ( b->x1 > out->x1 ) out->x1 = b->x1;
void r200RecalcScissorRects( r200ContextPtr rmesa )
{
- XF86DRIClipRectPtr out;
+ drm_clip_rect_t *out;
int i;
/* Grow cliprect store?
rmesa->state.scissor.pClipRects =
MALLOC( rmesa->state.scissor.numAllocedClipRects *
- sizeof(XF86DRIClipRectRec) );
+ sizeof(drm_clip_rect_t) );
if ( rmesa->state.scissor.pClipRects == NULL ) {
rmesa->state.scissor.numAllocedClipRects = 0;
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
GLuint i;
- drmRadeonStipple stipple;
+ drm_radeon_stipple_t stipple;
/* Must flip pattern upside down.
*/
*/
stipple.mask = rmesa->state.stipple.mask;
drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE,
- &stipple, sizeof(drmRadeonStipple) );
+ &stipple, sizeof(stipple) );
UNLOCK_HARDWARE( rmesa );
}
switch ( mode ) {
case GL_FRONT_LEFT:
rmesa->numClipRects = dPriv->numClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pClipRects;
+ rmesa->pClipRects = dPriv->pClipRects;
break;
case GL_BACK_LEFT:
/* Can't ignore 2d windows if we are page flipping.
*/
if ( dPriv->numBackClipRects == 0 || rmesa->doPageFlip ) {
rmesa->numClipRects = dPriv->numClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pClipRects;
+ rmesa->pClipRects = dPriv->pClipRects;
}
else {
rmesa->numClipRects = dPriv->numBackClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pBackClipRects;
+ rmesa->pClipRects = dPriv->pBackClipRects;
}
break;
default:
static int cmdpkt( int id )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.packet.cmd_type = RADEON_CMD_PACKET;
h.packet.packet_id = id;
static int cmdvec( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.vectors.cmd_type = RADEON_CMD_VECTORS;
h.vectors.offset = offset;
static int cmdscl( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.scalars.cmd_type = RADEON_CMD_SCALARS;
h.scalars.offset = offset;
static int cmdscl2( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.scalars.cmd_type = RADEON_CMD_SCALARS2;
h.scalars.offset = offset - 0x100;
(2 << R200_TXFORMAT_WIDTH_SHIFT) |
(2 << R200_TXFORMAT_HEIGHT_SHIFT));
rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
- rmesa->r200Screen->texOffset[RADEON_CARD_HEAP];
+ rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
(/* R200_TEXCOORD_PROJ | */
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
- rmesa->r200Screen->texOffset[RADEON_CARD_HEAP];
+ rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
- rmesa->r200Screen->texOffset[RADEON_CARD_HEAP];
+ rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
- rmesa->r200Screen->texOffset[RADEON_CARD_HEAP];
+ rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
- rmesa->r200Screen->texOffset[RADEON_CARD_HEAP];
+ rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
- rmesa->r200Screen->texOffset[RADEON_CARD_HEAP];
+ rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
}
rmesa->hw.pix[0].cmd[PIX_PP_TXCBLEND] =
GLuint offset;
GLint imageWidth, imageHeight;
GLint ret;
- drmRadeonTexture tex;
- drmRadeonTexImage tmp;
+ drm_radeon_texture_t tex;
+ drm_radeon_tex_image_t tmp;
const int level = hwlevel + t->base.firstLevel;
if ( R200_DEBUG & DEBUG_TEXTURE ) {
t->image[face][hwlevel].data = texImage->Data;
- /* Init the DRM_RADEON_TEXTURE command / drmRadeonTexture struct.
+ /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
* NOTE: we're always use a 1KB-wide blit and I8 texture format.
* We used to use 1, 2 and 4-byte texels and used to use the texture
* width to dictate the blit width - but that won't work for compressed
tex.image = &tmp;
/* copy (x,y,width,height,data) */
- memcpy( &tmp, &t->image[face][hwlevel], sizeof(drmRadeonTexImage) );
+ memcpy( &tmp, &t->image[face][hwlevel], sizeof(tmp) );
LOCK_HARDWARE( rmesa );
do {
ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE,
- &tex, sizeof(drmRadeonTexture) );
+ &tex, sizeof(drm_radeon_texture_t) );
if (ret) {
if (R200_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n");
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
ifeq ($(EMBEDDED),true)
static void radeonCompatEmitPacket( radeonContextPtr rmesa,
struct radeon_state_atom *state )
{
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
- radeon_context_regs_t *ctx = &sarea->ContextState;
- radeon_texture_regs_t *tex0 = &sarea->TexState[0];
- radeon_texture_regs_t *tex1 = &sarea->TexState[1];
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
+ drm_radeon_context_regs_t *ctx = &sarea->context_state;
+ drm_radeon_texture_regs_t *tex0 = &sarea->tex_state[0];
+ drm_radeon_texture_regs_t *tex1 = &sarea->tex_state[1];
int i;
int *buf = state->cmd;
for ( i = 0 ; i < state->cmd_size ; ) {
- drmRadeonCmdHeader *header = (drmRadeonCmdHeader *)&buf[i++];
+ drm_radeon_cmd_header_t *header = (drm_radeon_cmd_header_t *)&buf[i++];
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s %d: %s\n", __FUNCTION__, header->packet.packet_id,
static void radeonCompatEmitPrimitiveLocked( radeonContextPtr rmesa,
GLuint hw_primitive,
GLuint nverts,
- XF86DRIClipRectPtr pbox,
+ drm_clip_rect_t *pbox,
GLuint nbox )
{
int i;
for ( i = 0 ; i < nbox ; ) {
int nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, nbox );
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
- drmRadeonVertex vtx;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
+ drm_radeon_vertex_t vtx;
rmesa->sarea->dirty |= RADEON_UPLOAD_CLIPRECTS;
rmesa->sarea->nbox = nr - i;
rmesa->dri.drmMinor = sPriv->drmMinor;
rmesa->radeonScreen = screen;
- rmesa->sarea = (RADEONSAREAPrivPtr)((GLubyte *)sPriv->pSAREA +
+ rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
screen->sarea_priv_offset);
screen->texSize[i],
12,
RADEON_NR_TEX_REGIONS,
- rmesa->sarea->texList[i],
- & rmesa->sarea->texAge[i],
+ (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
+ & rmesa->sarea->tex_age[i],
& rmesa->swapped,
sizeof( radeonTexObj ),
(destroy_texture_object_t *) radeonDestroyTexObj );
#include <inttypes.h>
#include "dri_util.h"
-#include "radeon_common.h"
#include "texmem.h"
#include "macros.h"
};
struct radeon_scissor_state {
- XF86DRIClipRectRec rect;
+ drm_clip_rect_t rect;
GLboolean enabled;
GLuint numClipRects; /* Cliprects active */
GLuint numAllocedClipRects; /* Cliprects available */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
};
struct radeon_stencilbuffer_state {
brought into the
texunit. */
- drmRadeonTexImage image[6][RADEON_MAX_TEXTURE_LEVELS];
+ drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
/* Six, for the cube faces */
GLuint pp_txfilter; /* hardware register values */
__DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */
drmContext hwContext;
- drmLock *hwLock;
+ drm_hw_lock_t *hwLock;
int fd;
int drmMinor;
};
GLuint do_usleeps;
GLuint do_irqs;
GLuint irqsEmitted;
- drmRadeonIrqWait iw;
+ drm_radeon_irq_wait_t iw;
/* Drawable, cliprect and scissor information
*/
GLuint numClipRects; /* Cliprects for the draw buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
unsigned int lastStamp;
GLboolean lost_context;
radeonScreenPtr radeonScreen; /* Screen private DRI data */
- RADEONSAREAPrivPtr sarea; /* Private SAREA data */
+ drm_radeon_sarea_t *sarea; /* Private SAREA data */
/* TCL stuff
*/
GLuint primitive,
GLuint vertex_nr )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
rmesa->store.cmd_used/4);
#if RADEON_OLD_PACKETS
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 6 * sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 6 * sizeof(*cmd),
__FUNCTION__ );
cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM | (3 << 16);
__FUNCTION__,
cmd[1].i, cmd[2].i, cmd[4].i, cmd[5].i);
#else
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 4 * sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 4 * sizeof(*cmd),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
GLuint primitive,
GLuint min_nr )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
GLushort *retval;
if (RADEON_DEBUG & DEBUG_IOCTL)
radeonEmitState( rmesa );
#if RADEON_OLD_PACKETS
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa,
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa,
24 + min_nr*2,
__FUNCTION__ );
cmd[0].i = 0;
retval = (GLushort *)(cmd+6);
#else
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa,
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa,
16 + min_nr*2,
__FUNCTION__ );
cmd[0].i = 0;
rmesa->ioctl.vertex_size = vertex_size;
rmesa->ioctl.vertex_offset = offset;
#else
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 5 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 5 * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
rmesa->ioctl.vertex_offset =
(component[0]->aos_start + offset * component[0]->aos_stride * 4);
#else
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
int sz = 3 + (nr/2 * 3) + (nr & 1) * 2;
int i;
int *tmp;
fprintf(stderr, "%s\n", __FUNCTION__);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, sz * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sz * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
GLint dstx, GLint dsty,
GLuint w, GLuint h )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
assert( w < (1<<16) );
assert( h < (1<<16) );
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int),
__FUNCTION__ );
void radeonEmitWait( radeonContextPtr rmesa, GLuint flags )
{
if (rmesa->dri.drmMinor >= 6) {
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
const char * caller )
{
int ret, i;
- drmRadeonCmdBuffer cmd;
+ drm_radeon_cmd_buffer_t cmd;
if (RADEON_DEBUG & DEBUG_IOCTL) {
fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
if (rmesa->state.scissor.enabled) {
cmd.nbox = rmesa->state.scissor.numClipRects;
- cmd.boxes = (drmClipRect *)rmesa->state.scissor.pClipRects;
+ cmd.boxes = rmesa->state.scissor.pClipRects;
} else {
cmd.nbox = rmesa->numClipRects;
- cmd.boxes = (drmClipRect *)rmesa->pClipRects;
+ cmd.boxes = rmesa->pClipRects;
}
ret = drmCommandWrite( rmesa->dri.fd,
UNLOCK_HARDWARE( rmesa );
if (ret) {
- fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret);
+ fprintf(stderr, "drm_radeon_cmd_buffer_t: %d (exiting)\n", ret);
exit(ret);
}
}
rmesa->dma.flush( rmesa );
if (--region->buf->refcount == 0) {
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA))
fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__,
region->buf->buf->idx);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sizeof(*cmd),
__FUNCTION__ );
cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD;
cmd->dma.buf_idx = region->buf->buf->idx;
CARD32 frame;
if (rmesa->dri.screen->drmMinor >= 4) {
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_LAST_FRAME;
gp.value = (int *)&frame;
}
#endif
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
exit(1);
}
static void radeonEmitIrqLocked( radeonContextPtr rmesa )
{
- drmRadeonIrqEmit ie;
+ drm_radeon_irq_emit_t ie;
int ret;
ie.irq_seq = &rmesa->iw.irq_seq;
ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT,
&ie, sizeof(ie) );
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret );
exit(1);
}
}
static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
{
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
if (rmesa->do_irqs) {
if (radeonGetLastFrame(rmesa) < sarea->last_frame) {
radeonContextPtr rmesa;
GLint nbox, i, ret;
GLboolean missed_target;
- uint64_t ust;
+ int64_t ust;
assert(dPriv);
assert(dPriv->driContextPriv);
for ( i = 0 ; i < nbox ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
GLint n = 0;
for ( ; i < nr ; i++ ) {
*/
if (dPriv->numClipRects)
{
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
b[0] = box[0];
rmesa->sarea->nbox = 1;
}
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
CARD32 clear;
GLuint flags = 0;
int ret;
if (rmesa->dri.screen->drmMinor >= 4) {
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_LAST_CLEAR;
gp.value = (int *)&clear;
}
#endif
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
exit(1);
}
if ( RADEON_DEBUG & DEBUG_IOCTL ) {
for ( i = 0 ; i < dPriv->numClipRects ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
- drmRadeonClearType clear;
- drmRadeonClearRect depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
+ drm_radeon_clear_t clear;
+ drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
GLint n = 0;
if ( !all ) {
n--;
b = rmesa->sarea->boxes;
for ( ; n >= 0 ; n-- ) {
- depth_boxes[n].f[RADEON_CLEAR_X1] = (float)b[n].x1;
- depth_boxes[n].f[RADEON_CLEAR_Y1] = (float)b[n].y1;
- depth_boxes[n].f[RADEON_CLEAR_X2] = (float)b[n].x2;
- depth_boxes[n].f[RADEON_CLEAR_Y2] = (float)b[n].y2;
- depth_boxes[n].f[RADEON_CLEAR_DEPTH] =
+ depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
+ depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
+ depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
+ depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
+ depth_boxes[n].f[CLEAR_DEPTH] =
(float)rmesa->state.depth.clear;
}
ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR,
- &clear, sizeof(drmRadeonClearType));
+ &clear, sizeof(drm_radeon_clear_t));
if ( ret ) {
UNLOCK_HARDWARE( rmesa );
int use_back;
- rmesa->doPageFlip = rmesa->sarea->pfAllowPageFlip;
+ rmesa->doPageFlip = rmesa->sarea->pfState;
use_back = (rmesa->glCtx->Color._DrawDestMask == BACK_LEFT_BIT);
use_back ^= (rmesa->sarea->pfCurrentPage == 1);
{
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
__DRIscreenPrivate *sPriv = rmesa->dri.screen;
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
drmGetLock( rmesa->dri.fd, rmesa->dri.hwContext, flags );
rmesa->lastStamp = dPriv->lastStamp;
}
- if ( sarea->ctxOwner != rmesa->dri.hwContext ) {
+ if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
int i;
- sarea->ctxOwner = rmesa->dri.hwContext;
+ sarea->ctx_owner = rmesa->dri.hwContext;
for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
DRI_AGE_TEXTURES( rmesa->texture_heaps[ i ] );
static int radeon_emit_packets(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int id = (int)header.packet.packet_id;
int sz = packet[id].len;
static int radeon_emit_scalars(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
static int radeon_emit_scalars2(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
* Check: table start, end, nr, etc.
*/
static int radeon_emit_vectors(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.vectors.count;
int *data = (int *)cmdbuf->buf;
/* build in knowledge about each packet type
*/
-static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
{
int cmdsz;
int *cmd = (int *)cmdbuf->buf;
/* Check cliprects for bounds, then pass on to above:
*/
-static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
{
- XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
+ drm_clip_rect_t *boxes = cmdbuf->boxes;
int i = 0;
if (VERBOSE && total_changed) {
int radeonSanityCmdBuffer( radeonContextPtr rmesa,
int nbox,
- XF86DRIClipRectRec *boxes )
+ drm_clip_rect_t *boxes )
{
int idx;
- drmRadeonCmdBuffer cmdbuf;
- drmRadeonCmdHeader header;
+ drm_radeon_cmd_buffer_t cmdbuf;
+ drm_radeon_cmd_header_t header;
static int inited = 0;
if (!inited) {
cmdbuf.buf = rmesa->store.cmd_buf;
cmdbuf.bufsz = rmesa->store.cmd_used;
- cmdbuf.boxes = (drmClipRect *)boxes;
+ cmdbuf.boxes = boxes;
cmdbuf.nbox = nbox;
while ( cmdbuf.bufsz >= sizeof(header) ) {
extern int radeonSanityCmdBuffer( radeonContextPtr rmesa,
int nbox,
- XF86DRIClipRectRec *boxes );
+ drm_clip_rect_t *boxes );
#endif
{
int ret;
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
gp.value = &screen->gart_buffer_offset;
&gp, sizeof(gp));
if (ret) {
FREE( screen );
- fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
+ fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
return NULL;
}
&gp, sizeof(gp));
if (ret) {
FREE( screen );
- fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_IRQ_NR): %d\n", ret);
+ fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
return NULL;
}
}
screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
if ( sPriv->drmMinor >= 10 ) {
- drmRadeonSetParam sp;
+ drm_radeon_setparam_t sp;
sp.param = RADEON_SETPARAM_FB_LOCATION;
sp.value = screen->fbLocation;
screen->depthOffset = dri_priv->depthOffset;
screen->depthPitch = dri_priv->depthPitch;
- screen->texOffset[RADEON_CARD_HEAP] = dri_priv->textureOffset
+ screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
+ screen->fbLocation;
- screen->texSize[RADEON_CARD_HEAP] = dri_priv->textureSize;
- screen->logTexGranularity[RADEON_CARD_HEAP] =
+ screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
+ screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
dri_priv->log2TexGran;
if ( !screen->gartTextures.map
|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
- screen->texOffset[RADEON_GART_HEAP] = 0;
- screen->texSize[RADEON_GART_HEAP] = 0;
- screen->logTexGranularity[RADEON_GART_HEAP] = 0;
+ screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
+ screen->texSize[RADEON_GART_TEX_HEAP] = 0;
+ screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
} else {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
- screen->texOffset[RADEON_GART_HEAP] = screen->gart_texture_offset;
- screen->texSize[RADEON_GART_HEAP] = dri_priv->gartTexMapSize;
- screen->logTexGranularity[RADEON_GART_HEAP] =
+ screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
+ screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
+ screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
dri_priv->log2GARTTexGran;
}
#ifndef _SOLO
* definitions that we need.
*/
#include "dri_util.h"
-#include "radeon_common.h"
#include "radeon_dri.h"
#include "radeon_reg.h"
-#include "radeon_sarea.h"
+#include "drm_sarea.h"
#include "xmlconfig.h"
*/
-static GLboolean intersect_rect( XF86DRIClipRectPtr out,
- XF86DRIClipRectPtr a,
- XF86DRIClipRectPtr b )
+static GLboolean intersect_rect( drm_clip_rect_t *out,
+ drm_clip_rect_t *a,
+ drm_clip_rect_t *b )
{
*out = *a;
if ( b->x1 > out->x1 ) out->x1 = b->x1;
void radeonRecalcScissorRects( radeonContextPtr rmesa )
{
- XF86DRIClipRectPtr out;
+ drm_clip_rect_t *out;
int i;
/* Grow cliprect store?
rmesa->state.scissor.pClipRects =
MALLOC( rmesa->state.scissor.numAllocedClipRects *
- sizeof(XF86DRIClipRectRec) );
+ sizeof(drm_clip_rect_t) );
if ( rmesa->state.scissor.pClipRects == NULL ) {
rmesa->state.scissor.numAllocedClipRects = 0;
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
GLuint i;
- drmRadeonStipple stipple;
+ drm_radeon_stipple_t stipple;
/* Must flip pattern upside down.
*/
*/
stipple.mask = rmesa->state.stipple.mask;
drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE,
- &stipple, sizeof(drmRadeonStipple) );
+ &stipple, sizeof(drm_radeon_stipple_t) );
UNLOCK_HARDWARE( rmesa );
}
switch ( mode ) {
case GL_FRONT_LEFT:
rmesa->numClipRects = dPriv->numClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pClipRects;
+ rmesa->pClipRects = dPriv->pClipRects;
break;
case GL_BACK_LEFT:
/* Can't ignore 2d windows if we are page flipping.
*/
if ( dPriv->numBackClipRects == 0 || rmesa->doPageFlip ) {
rmesa->numClipRects = dPriv->numClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pClipRects;
+ rmesa->pClipRects = dPriv->pClipRects;
}
else {
rmesa->numClipRects = dPriv->numBackClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pBackClipRects;
+ rmesa->pClipRects = dPriv->pBackClipRects;
}
break;
default:
static int cmdpkt( int id )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.packet.cmd_type = RADEON_CMD_PACKET;
h.packet.packet_id = id;
static int cmdvec( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.vectors.cmd_type = RADEON_CMD_VECTORS;
h.vectors.offset = offset;
static int cmdscl( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.scalars.cmd_type = RADEON_CMD_SCALARS;
h.scalars.offset = offset;
/* Initialize the texture offset to the start of the card texture heap */
rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
- rmesa->radeonScreen->texOffset[RADEON_CARD_HEAP];
+ rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
GLuint offset;
GLint imageWidth, imageHeight;
GLint ret;
- drmRadeonTexture tex;
- drmRadeonTexImage tmp;
+ drm_radeon_texture_t tex;
+ drm_radeon_tex_image_t tmp;
const int level = hwlevel + t->base.firstLevel;
if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
t->image[face][hwlevel].data = texImage->Data;
- /* Init the DRM_RADEON_TEXTURE command / drmRadeonTexture struct.
+ /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
* NOTE: we're always use a 1KB-wide blit and I8 texture format.
* We used to use 1, 2 and 4-byte texels and used to use the texture
* width to dictate the blit width - but that won't work for compressed
tex.image = &tmp;
/* copy (x,y,width,height,data) */
- memcpy( &tmp, &t->image[face][hwlevel], sizeof(drmRadeonTexImage) );
+ memcpy( &tmp, &t->image[face][hwlevel], sizeof(drm_radeon_tex_image_t) );
LOCK_HARDWARE( rmesa );
do {
ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE,
- &tex, sizeof(drmRadeonTexture) );
+ &tex, sizeof(drm_radeon_texture_t) );
} while ( ret && errno == EAGAIN );
UNLOCK_HARDWARE( rmesa );
#include "radeon_dri.h"
#include "radeon_macros.h"
#include "radeon_reg.h"
-#include "radeon_sarea.h"
-#include "sarea.h"
+#include "drm_sarea.h"
/* HACK - for now, put this here... */
*/
static int RADEONEngineShutdown( const DRIDriverContext *ctx )
{
- drmRadeonCPStop stop;
+ drm_radeon_cp_stop_t stop;
int ret, i;
stop.flush = 1;
stop.idle = 1;
ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drmRadeonCPStop));
+ sizeof(drm_radeon_cp_stop_t));
if (ret == 0) {
return 0;
i = 0;
do {
ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drmRadeonCPStop));
+ sizeof(drm_radeon_cp_stop_t));
} while (ret && errno == EBUSY && i++ < 10);
if (ret == 0) {
stop.idle = 0;
if (drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP,
- &stop, sizeof(drmRadeonCPStop))) {
+ &stop, sizeof(drm_radeon_cp_stop_t))) {
return -errno;
} else {
return 0;
* \return non-zero on success, or zero on failure.
*
* This function is a wrapper around the DRM_RADEON_CP_INIT command, passing
- * all the parameters in a drmRadeonInit structure.
+ * all the parameters in a drm_radeon_init_t structure.
*/
static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
RADEONInfoPtr info)
{
int cpp = ctx->bpp / 8;
- drmRadeonInit drmInfo;
+ drm_radeon_init_t drmInfo;
int ret;
- memset(&drmInfo, 0, sizeof(drmRadeonInit));
+ memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
if ( (info->ChipFamily == CHIP_FAMILY_R200) ||
(info->ChipFamily == CHIP_FAMILY_RV250) ||
(info->ChipFamily == CHIP_FAMILY_M9) ||
(info->ChipFamily == CHIP_FAMILY_RV280) )
- drmInfo.func = DRM_RADEON_INIT_R200_CP;
+ drmInfo.func = RADEON_INIT_R200_CP;
else
- drmInfo.func = DRM_RADEON_INIT_CP;
+ drmInfo.func = RADEON_INIT_CP;
/* This is the struct passed to the kernel module for its initialization */
- drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
+ drmInfo.sarea_priv_offset = sizeof(drm_sarea_t);
drmInfo.is_pci = 0;
drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE;
drmInfo.gart_size = info->gartSize*1024*1024;
drmInfo.gart_textures_offset = info->gartTexHandle;
ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo,
- sizeof(drmRadeonInit));
+ sizeof(drm_radeon_init_t));
return ret >= 0;
}
static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx,
RADEONInfoPtr info)
{
- drmRadeonMemInitHeap drmHeap;
+ drm_radeon_mem_init_heap_t drmHeap;
/* Start up the simple memory manager for gart space */
drmHeap.region = RADEON_MEM_REGION_GART;
/* Initialize the SAREA private data structure */
{
- RADEONSAREAPrivPtr pSAREAPriv;
- pSAREAPriv = (RADEONSAREAPrivPtr)(((char*)ctx->pSAREA) +
- sizeof(XF86DRISAREARec));
+ drm_radeon_sarea_t *pSAREAPriv;
+ pSAREAPriv = (drm_radeon_sarea_t *)(((char*)ctx->pSAREA) +
+ sizeof(drm_sarea_t));
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
- pSAREAPriv->pfAllowPageFlip = 1;
+ pSAREAPriv->pfState = 1;
}
pRADEONDRI->gartTexMapSize = info->gartTexMapSize;
pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran;
pRADEONDRI->gartTexOffset = info->gartTexStart;
- pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
+ pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t);
/* Don't release the lock now - let the VT switch handler do it. */
#define _RADEON_DRI_
#include "xf86drm.h"
-#include "radeon_common.h"
+#include "drm.h"
+#include "radeon_drm.h"
/* DRI Driver defaults */
#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
GLint dirtyflags = GFLAG_ENABLESETTING | GFLAG_ENABLESETTING2 |
GFLAG_CLIPPING | GFLAG_DESTSETTING;
int count;
- XF86DRIClipRectPtr pExtents;
+ drm_clip_rect_t *pExtents;
bClrColor = (mask & (DD_BACK_LEFT_BIT | DD_FRONT_LEFT_BIT)) != 0;
bClrDepth = (mask & DD_DEPTH_BIT) != 0;
int count;
GLuint depth = smesa->bytesPerPixel;
- XF86DRIClipRectPtr pExtents = NULL;
+ drm_clip_rect_t *pExtents = NULL;
GLint xx, yy;
GLint x0, y0, width0, height0;
unsigned int lastStamp; /* mirror driDrawable->lastStamp */
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
sisScreenPtr sisScreen; /* Screen private DRI data */
SISSAREAPrivPtr sarea; /* Private SAREA data */
sisScreen->deviceID = sisDRIPriv->deviceID;
sisScreen->AGPCmdBufOffset = sisDRIPriv->AGPCmdBufOffset;
sisScreen->AGPCmdBufSize = sisDRIPriv->AGPCmdBufSize;
- sisScreen->sarea_priv_offset = sizeof(XF86DRISAREARec);
+ sisScreen->sarea_priv_offset = sizeof(drm_sarea_t);
sisScreen->mmio.handle = sisDRIPriv->regs.handle;
sisScreen->mmio.size = sisDRIPriv->regs.size;
stEngPacket.stdwCmd.cCmd1 = CMD1_DIR_X_INC | CMD1_DIR_Y_INC;
for (i = 0; i < dPriv->numClipRects; i++) {
- XF86DRIClipRectPtr box = &dPriv->pClipRects[i];
+ drm_clip_rect_t *box = &dPriv->pClipRects[i];
stEngPacket.stdwSrcPos.wY = box->y1 - dPriv->y;
stEngPacket.stdwSrcPos.wX = box->x1 - dPriv->x;
stEngPacket.stdwDestPos.wY = box->y1;
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
int textureOffset, int textureSize,
volatile int *fifoPtr, volatile int *fifoRead );
extern void grDRIPosition( int x, int y, int w, int h,
- int numClip, XF86DRIClipRectPtr pClip );
+ int numClip, drm_clip_rect_t *pClip );
extern void grDRILostContext( void );
extern void grDRIImportFifo( int fifoPtr, int fifoRead );
extern void grDRIInvalidateAll( void );
__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
tdfxScreenPrivate *fxScreen = (tdfxScreenPrivate *) sPriv->private;
TDFXSAREAPriv *saPriv = (TDFXSAREAPriv *) ((char *) sPriv->pSAREA +
- sizeof(XF86DRISAREARec));
+ sizeof(drm_sarea_t));
struct dd_function_table functions;
/* Allocate tdfx context */
int textureOffset, int textureSize,
volatile int *fifoPtr, volatile int *fifoRead );
void (*grDRIPosition)( int x, int y, int w, int h,
- int numClip, XF86DRIClipRectPtr pClip );
+ int numClip, drm_clip_rect_t *pClip );
void (*grDRILostContext)( void );
void (*grDRIImportFifo)( int fifoPtr, int fifoRead );
void (*grDRIInvalidateAll)( void );
__DRIcontextPrivate *driContext;
__DRIdrawablePrivate *driDrawable;
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
int driFd;
tdfxScreenPrivate *fxScreen;
TDFXSAREAPriv *sarea;
int y_delta; /* distance from window bottom to screen bottom */
int numClipRects;
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
GLboolean scissoredClipRects; /* if true, pClipRects is private storage */
GuTexPalette glbPalette; /* global texture palette */
#define HW_READ_CLIPLOOP() \
do { \
const __DRIdrawablePrivate *dPriv = fxMesa->driDrawable; \
- XF86DRIClipRectPtr rect = dPriv->pClipRects; \
+ drm_clip_rect_t *rect = dPriv->pClipRects; \
int _nc = dPriv->numClipRects; \
while (_nc--) { \
const int minx = rect->x1 - fxMesa->x_offset; \
/* turn on flags for all visible pixels */
for (i = 0; i < fxMesa->numClipRects; i++) {
- const XF86DRIClipRectPtr rect = &fxMesa->pClipRects[i];
+ const drm_clip_rect_t *rect = &fxMesa->pClipRects[i];
if (y >= rect->y1 && y < rect->y2) {
if (x >= rect->x1 && x + n <= rect->x2) {
{
int i;
for (i = 0; i < fxMesa->numClipRects; i++) {
- const XF86DRIClipRectPtr rect = &fxMesa->pClipRects[i];
+ const drm_clip_rect_t *rect = &fxMesa->pClipRects[i];
if (scrX >= rect->x1 &&
scrX < rect->x2 &&
scrY >= rect->y1 && scrY < rect->y2) return GL_TRUE;
* Clipping
*/
-static int intersect_rect( XF86DRIClipRectPtr out,
- const XF86DRIClipRectPtr a,
- const XF86DRIClipRectPtr b)
+static int intersect_rect( drm_clip_rect_t *out,
+ const drm_clip_rect_t *a,
+ const drm_clip_rect_t *b)
{
*out = *a;
if (b->x1 > out->x1) out->x1 = b->x1;
/* intersect OpenGL scissor box with all cliprects to make a new
* list of cliprects.
*/
- XF86DRIClipRectRec scissor;
+ drm_clip_rect_t scissor;
int x1 = ctx->Scissor.X + fxMesa->x_offset;
int y1 = fxMesa->screen_height - fxMesa->y_delta
- ctx->Scissor.Y - ctx->Scissor.Height;
assert(scissor.y2 >= scissor.y1);
fxMesa->pClipRects = malloc(dPriv->numClipRects
- * sizeof(XF86DRIClipRectRec));
+ * sizeof(drm_clip_rect_t));
if (fxMesa->pClipRects) {
int i;
fxMesa->numClipRects = 0;
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
DEFINES += \
#endif
#include "dri_util.h"
-#include "sarea.h"
#include "via_context.h"
#include "via_dri.h"
int err;
#if 0
- ctx->shared.SAREASize = ((sizeof(XF86DRISAREARec) + 0xfff) & 0x1000);
+ ctx->shared.SAREASize = ((sizeof(drm_sarea_t) + 0xfff) & 0x1000);
#else
- if (sizeof(XF86DRISAREARec)+sizeof(VIASAREAPriv) > SAREA_MAX) {
+ if (sizeof(drm_sarea_t)+sizeof(VIASAREAPriv) > SAREA_MAX) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Data does not fit in SAREA\n");
return FALSE;
VIASAREAPriv *saPriv;
saPriv=(VIASAREAPriv*)(((char*)ctx->pSAREA) +
- sizeof(XF86DRISAREARec));
+ sizeof(drm_sarea_t));
assert(saPriv);
memset(saPriv, 0, sizeof(*saPriv));
saPriv->CtxOwner = -1;
pVIADRI->height=ctx->shared.virtualHeight;
pVIADRI->mem=ctx->shared.fbSize;
pVIADRI->bytesPerPixel= (ctx->bpp+7) / 8;
- pVIADRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
+ pVIADRI->sarea_priv_offset = sizeof(drm_sarea_t);
/* TODO */
pVIADRI->scrnX=pVIADRI->width;
pVIADRI->scrnY=pVIADRI->height;
{
drmVIAInit drmInfo;
memset(&drmInfo, 0, sizeof(drmVIAInit));
- drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
+ drmInfo.sarea_priv_offset = sizeof(drm_sarea_t);
drmInfo.fb_offset = pVia->FrameBufferBase;
drmInfo.mmio_offset = pVia->registerHandle;
if (pVia->IsPCI)
#else
#include "via_regs.h"
-#include "sarea.h"
#include "dri.h"
#include "via_dri.h"
#endif
#endif
}
- vmesa->pSaamRects = (XF86DRIClipRectPtr) malloc(sizeof(XF86DRIClipRectRec));
+ vmesa->pSaamRects = (drm_clip_rect_t *) malloc(sizeof(drm_clip_rect_t));
return GL_TRUE;
}
XineramaScreenInfo *xsi;
#endif
int drawXoffSaam;
- XF86DRIClipRectPtr pSaamRects;
+ drm_clip_rect_t *pSaamRects;
int drawXSaam;
int drawYSaam;
GLuint numSaamRects;
int readPitch;
int drawXoff;
GLuint numClipRects; /* cliprects for that buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
int lastSwap;
int texAge;
drm_clip_rect_t scissorRect;
drmContext hHWContext;
- drmLock *driHwLock;
+ drm_hw_lock_t *driHwLock;
int driFd;
#ifndef _SOLO
Display *display;
if (vmesa->numClipRects) {
int nr = MIN2(i + VIA_NR_SAREA_CLIPRECTS, vmesa->numClipRects);
- XF86DRIClipRectRec *box = vmesa->pClipRects;
+ drm_clip_rect_t *box = vmesa->pClipRects;
drm_clip_rect_t *b = vmesa->sarea->boxes;
int n = 0;
void viaCopyBuffer(const __DRIdrawablePrivate *dPriv)
{
viaContextPtr vmesa;
- XF86DRIClipRectPtr pbox;
+ drm_clip_rect_t *pbox;
int nbox, i;
GLuint scrn = 0, side = 0;
#ifdef DEBUG
if (!vmesa->saam) {
for (i = 0; i < nbox; ) {
int nr = MIN2(i + VIA_NR_SAREA_CLIPRECTS, dPriv->numClipRects);
- XF86DRIClipRectRec *b = (XF86DRIClipRectRec *)vmesa->sarea->boxes;
+ drm_clip_rect_t *b = (drm_clip_rect_t *)vmesa->sarea->boxes;
vmesa->sarea->nbox = nr - i;
else if (scrn == S0 || scrn == S1) {
for (i = 0; i < nbox; ) {
int nr = MIN2(i + VIA_NR_SAREA_CLIPRECTS, vmesa->numClipRects);
- XF86DRIClipRectRec *b = (XF86DRIClipRectRec *)vmesa->sarea->boxes;
+ drm_clip_rect_t *b = (drm_clip_rect_t *)vmesa->sarea->boxes;
vmesa->sarea->nbox = nr - i;
else {
for (i = 0; i < nbox; ) {
int nr = MIN2(i + VIA_NR_SAREA_CLIPRECTS, dPriv->numClipRects);
- XF86DRIClipRectRec *b = (XF86DRIClipRectRec *)vmesa->sarea->boxes;
+ drm_clip_rect_t *b = (drm_clip_rect_t *)vmesa->sarea->boxes;
vmesa->sarea->nbox = nr - i;
for (i = 0; i < nbox; ) {
int nr = MIN2(i + VIA_NR_SAREA_CLIPRECTS, vmesa->numSaamRects);
- XF86DRIClipRectRec *b = (XF86DRIClipRectRec *)vmesa->sarea->boxes;
+ drm_clip_rect_t *b = (drm_clip_rect_t *)vmesa->sarea->boxes;
vmesa->sarea->nbox = nr - i;
#define _ENUMS_H_
-#if _HAVE_FULL_GL
+#ifdef _HAVE_FULL_GL
extern const char *_mesa_lookup_enum_by_nr( int nr );
extern int _mesa_lookup_enum_by_name( const char *symbol );
projects / mesa.git / commitdiff