[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Sat, 23 May 2020 19:09:27 +0000 (19:09 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sat, 23 May 2020 19:09:28 +0000 (20:09 +0100)
37/78b24b7b83ddba4f79faef69c0482d1944edcd [new file with mode: 0644]

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+Date: Sat, 23 May 2020 19:09:27 +0000
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+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
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+Message-ID: <bug-336-13-J37GcYwq3b@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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