re PR target/48090 (gcc 4.5.2 miscompilation when building on arm)

Fix PR target/48090

2011-04-12  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

       PR target/48090
       * config/arm/arm.md (*arm_negdi2): Fix early clobber constraints.

From-SVN: r172318

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4a1ec50bbc3bd16ea38f5305a38a7e5c69614a1d..6c130b3b3ec03131b01c86c81ded09fd9b78816a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2011-04-12  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+       PR target/48090
+       * config/arm/arm.md (*arm_negdi2): Fix early clobber constraints.
+
 2011-04-12  Richard Sandiford  <richard.sandiford@linaro.org>
 
        * recog.h (insn_operand_data): Add an "allows_mem" field.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index e703a73fba07526c4852e3220b498d65928fb232..5e7b4023d12745873decc43bdb25249af537050e 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3696,7 +3696,7 @@
 ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
 ;; The first alternative allows the common case of a *full* overlap.
 (define_insn "*arm_negdi2"
-  [(set (match_operand:DI         0 "s_register_operand" "=&r,r")
+  [(set (match_operand:DI         0 "s_register_operand" "=r,&r")
        (neg:DI (match_operand:DI 1 "s_register_operand"  "0,r")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_ARM"