add elwidth override on MV.X

diff --git a/simple_v_extension/specification/mv.x.rst b/simple_v_extension/specification/mv.x.rst
index 078e5fe23c9e58746149b30e398a8c88460bc1c7..a921b4aa53d77e7d6224a391894bfeb8c84f4674 100644 (file)
--- a/simple_v_extension/specification/mv.x.rst
+++ b/simple_v_extension/specification/mv.x.rst
@@ -8,7 +8,7 @@ swizzle needs a MV.  see below for a potential way to use the funct7 to do a swi
 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 | RV32-I-type   + imm[11:0]                      + rs1[4:0] + funct3 | rd[4:0]  + opcode + 0b11   |
 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
-| RV32-I-type   + fn4[11:8] swizzle[7:0]         + rs1[4:0] + 0b000  | rd[4:0]  + OP-V   + 0b11   |
+| RV32-I-type   + fn4[3:0]    + swizzle[7:0]     + rs1[4:0] + 0b000  | rd[4:0]  + OP-V   + 0b11   |
 +---------------+-------------+-------+----------+----------+--------+----------+--------+--------+
 
 * funct3 = MV
@@ -16,6 +16,8 @@ swizzle needs a MV.  see below for a potential way to use the funct7 to do a swi
 * fn4 = 4 bit function.
 * fn4 = 0b0000 - INT MV-SWIZZLE ?
 * fn4 = 0b0001 - FP MV-SWIZZLE ?
+* fn4 = 0bNN10 - INT MV-X, NN=elwidth (default/8/16/32)
+* fn4 = 0bNN11 - FP MV-X NN=elwidth (default/8/16/32)
 
 swizzle (only active on SV or P48/P64 when SUBVL!=0):
 
@@ -25,6 +27,43 @@ swizzle (only active on SV or P48/P64 when SUBVL!=0):
 |   w |   z |   y |   x |
 +-----+-----+-----+-----+
 
+Pseudocode for element width part of MV.X:
+
+.. code:: python
+    def mv_x(rd, rs1, funct4):
+        elwidth = (funct4>>2) & 0x3
+        bitwidth = {0:XLEN, 1:8, 2:16, 3:32}[elwidth] # get bits per el
+        bytewidth = bitwidth / 8 # get bytes per el
+        for i in range(VL):
+            addr = (unsigned char *)&regs[rs1]
+            offset = addr + bytewidth # get offset within regfile as SRAM
+            # TODO, actually, needs to respect rd and rs1 element width,
+            # here, as well.  this pseudocode just illustrates that the
+            # MV.X operation contains a way to compact the indices into
+            # less space.
+            regs[rd] = (unsigned char*)(regs)[offset]
+
+The idea here is to allow 8-bit indices to be stored inside XLEN-sized
+registers, such that rather than doing this:
+
+.. parsed-literal::
+    ldimm x8, 1
+    ldimm x9, 3
+    ldimm x10, 2
+    ldimm x11, 0
+    {SVP.VL=4} MV.X x3, x8, elwidth=default
+
+The alternative is this:
+
+.. parsed-literal::
+    ldimm x8, 0x00020301
+    {SVP.VL=4} MV.X x3, x8, elwidth=8
+
+Thus compacting four indices into the one register.  x3 and x8's element
+width are *independent* of the MV.X elwidth, thus allowing both source
+and element element widths of the *elements* to be moved to be over-ridden,
+whilst *at the same time* allowing the *indices* to be compacted, as well.
+
 ----
 
 potential MV.X?  register-version of MV-swizzle?
@@ -39,9 +78,9 @@ potential MV.X?  register-version of MV-swizzle?
 
 * funct3 = MV.X
 * OP-V = 0b1010111
-* funct7 = 0b0000000 - INT MV.X
-* funct7 = 0b0000001 - FP MV.X
-* funct7 = 0b0000010 - INT MV.swizzle to say that rs2 is a swizzle argument?
+* funct7 = 0b000NN00 - INT MV.X, elwidth=NN (default/8/16/32)
+* funct7 = 0b000NN10 - FP MV.X, elwidth=NN (default/8/16/32)
+* funct7 = 0b0000001 - INT MV.swizzle to say that rs2 is a swizzle argument?
 * funct7 = 0b0000011 - FP MV.swizzle to say that rs2 is a swizzle argument?
 
 question: do we need a swizzle MV.X as well?