change test cases to use TestRunnerBase in order to not need soc

diff --git a/src/openpower/decoder/isa/test_caller_alu.py b/src/openpower/decoder/isa/test_caller_alu.py
index 155d1a98011cb7b02aa28de11dafc353ab42a921..9011ef62cb878cfe848b5838c0092b54c7fc2e5a 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_alu.py
+++ b/src/openpower/decoder/isa/test_caller_alu.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.alu.alu_cases import ALUTestCase
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/openpower/decoder/isa/test_caller_bitmanip.py b/src/openpower/decoder/isa/test_caller_bitmanip.py
index 4c5db09154ca7b6fbc1e29dc3e8a6096cc57a8b0..6ba5f661885083e9aa0a7ff394e0f270232dce57 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_bitmanip.py
+++ b/src/openpower/decoder/isa/test_caller_bitmanip.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.bitmanip.bitmanip_cases import BitManipTestCase
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/openpower/decoder/isa/test_caller_bitmanip_av.py b/src/openpower/decoder/isa/test_caller_bitmanip_av.py
index 9c4788fcd8de9f54a1b925f62d7bed3ac3e3eb1e..4e5cf97a9f259661a42672733375732c1415a1d7 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_bitmanip_av.py
+++ b/src/openpower/decoder/isa/test_caller_bitmanip_av.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.bitmanip.av_cases import AVTestCase
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/openpower/decoder/isa/test_caller_fmvis.py b/src/openpower/decoder/isa/test_caller_fmvis.py
index 63e923d6accb0f1aaa83a5e670134092de755acd..1c7638a4c8e1583c5bdaa57728e3aca04eb3ae9f 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fmvis.py
+++ b/src/openpower/decoder/isa/test_caller_fmvis.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.alu.fmvis_cases import FMVISTestCase
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/openpower/decoder/isa/test_caller_logical.py b/src/openpower/decoder/isa/test_caller_logical.py
index eb3282b43fb468fc3954f3ca51c09cc41c267c9a..9546319f4f66c9149833195d2c251e863b50f907 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_logical.py
+++ b/src/openpower/decoder/isa/test_caller_logical.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.logical.logical_cases import LogicalTestCase
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/openpower/decoder/isa/test_caller_mul.py b/src/openpower/decoder/isa/test_caller_mul.py
index cb2e218de49f8872f2f6380db8ee6bb6478cae04..824d3a93f2cf4f1b620c30e8ccefc36b07090d78 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_mul.py
+++ b/src/openpower/decoder/isa/test_caller_mul.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.mul.mul_cases import MulTestCases2Arg
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/openpower/decoder/isa/test_caller_shift_rot.py b/src/openpower/decoder/isa/test_caller_shift_rot.py
index 04a0e4a94db3dbb75d088aa7af8ef55514dffb97..6d0a949f274c0d50303aeda4687d1de116fdfa90 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_shift_rot.py
+++ b/src/openpower/decoder/isa/test_caller_shift_rot.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.shift_rot.shift_rot_cases2 import ShiftRotTestCase2
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/openpower/decoder/isa/test_caller_svp64_alu.py b/src/openpower/decoder/isa/test_caller_svp64_alu.py
index c46d31a00ff16aa46bf4115c9cada5a6898ea36a..1a294d5decdf4223d3dccf7d4014260ac50e3a5e 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_alu.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_alu.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.alu.svp64_cases import SVP64ALUTestCase
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/openpower/decoder/isa/test_caller_svp64_logical.py b/src/openpower/decoder/isa/test_caller_svp64_logical.py
index 483b24775b77ba5daea6028ca66782f8c01f8806..bc600cf739f8afd181ae32a8e83162f6920e6a32 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_logical.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_logical.py
@@ -10,7 +10,7 @@ import sys
 
 # These tests utilize the run_hdl=False parameter to compare
 # simulator with expected states
-from soc.simple.test.test_runner import TestRunner
+from openpower.test.runner import TestRunnerBase
 from openpower.test.logical.svp64_cases import SVP64LogicalTestCase
 
 
@@ -32,7 +32,7 @@ if __name__ == "__main__":
     # walk through all tests, those requested get added
     for tname, data in tests.items():
         if tname in testing:
-            suite.addTest(TestRunner(data, run_hdl=False))
+            suite.addTest(TestRunnerBase(data))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)