Fixed xilinx/example_sim_counter test bench

diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh
index e26d00db1d2429f6d112eefcf719ce65271900d7..b8354c0029241e0f3938a0efceaad7abf6078530 100644 (file)
--- a/techlibs/xilinx/example_sim_counter/run_sim.sh
+++ b/techlibs/xilinx/example_sim_counter/run_sim.sh
@@ -8,7 +8,7 @@ XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
 
 iverilog -o testbench_gold counter_tb.v counter.v
 iverilog -o testbench_gate counter_tb.v testbench_synth.v \
-       $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
+       $XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v
 
 ./testbench_gold > testbench_gold.txt
 ./testbench_gate > testbench_gate.txt