Fix wrong T1 signal
authorJean THOMAS <git0@pub.jeanthomas.me>
Mon, 27 Jul 2020 14:41:29 +0000 (16:41 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Mon, 27 Jul 2020 14:41:29 +0000 (16:41 +0200)
gram/phy/ecp5ddrphy.py

index 73cd997458ccad85e7ad975142090e03f11c36b6..6d579c6618d06ca89d3ecce4084016ded234de41 100644 (file)
@@ -341,7 +341,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                     i_SCLK=ClockSignal(),
                     i_DQSW=dqsw,
                     i_T0=~(dqs_oe | dqs_postamble),
-                    i_T1=~(dqs_oe | dqs_postamble),
+                    i_T1=~(dqs_oe | dqs_preamble),
                     o_Q=dqs_oe_n),
                 Instance("BB",
                     i_I=dqs,