Rework xilinx_dsp postAdd for new wreduce call

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index bca44c08db02b75519934d38b905a35792f9b230..e256f7d7eab7b0ac0fbf4c29bec85adb59b0c8ac 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -271,9 +271,9 @@ match postAdd
        filter !ffMcemux || nusers(port(postAdd, AB)) == 3
 
        index <SigBit> port(postAdd, AB)[0] === sigP[0]
-       filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
-       filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
-       filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1
+       filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
+       filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
+       filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP))
        set postAddAB AB
        optional
 endmatch