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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 17 Oct 2023 15:29:30 +0000 (16:29 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:21 +0000 (19:26 +0000)
openpower/isa/pifixedload.mdwn patch | blob | history

diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn
index a1fe93c122d877c396393077dbaa9b36b0316466..0418b1cd4e89ec350842d373190343fcd1c72893 100644 (file)
--- a/openpower/isa/pifixedload.mdwn
+++ b/openpower/isa/pifixedload.mdwn
@@ -231,7 +231,8 @@ Pseudo-code:
 Description:
 
     Let the effective address (EA) be the register RA.
-    The word in storage addressed by EA is loaded into RT[32:63].RT[0:31] are filled with a copy of bit 0 of the loaded word.
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are filled with a copy of bit 0 of the loaded word.
 
     The sum (RA) + (RB) is placed into register RA.