tools/litex_sim: add ethernet local/remote-ip arguments.

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 2a70b49c6d810f9fbc8abccdd195b78251ffa89d..6d50e7814f2d19be48e206317e8bdc54694b5cf2 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -255,22 +255,24 @@ def main():
     parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--threads",              default=1,             help="Set number of threads (default=1)")
-    parser.add_argument("--rom-init",             default=None,          help="rom_init file")
-    parser.add_argument("--ram-init",             default=None,          help="ram_init file")
-    parser.add_argument("--with-sdram",           action="store_true",   help="Enable SDRAM support")
-    parser.add_argument("--sdram-module",         default="MT48LC16M16", help="Select SDRAM chip")
-    parser.add_argument("--sdram-data-width",     default=32,            help="Set SDRAM chip data width")
-    parser.add_argument("--sdram-init",           default=None,          help="SDRAM init file")
-    parser.add_argument("--sdram-no-timing",      action="store_true",   help="Disable SDRAM timing verification checks")
-    parser.add_argument("--sdram-verbose-timing", action="store_true",   help="Enable SDRAM verbose timing logging")
-    parser.add_argument("--with-ethernet",        action="store_true",   help="Enable Ethernet support")
-    parser.add_argument("--with-etherbone",       action="store_true",   help="Enable Etherbone support")
-    parser.add_argument("--with-analyzer",        action="store_true",   help="Enable Analyzer support")
-    parser.add_argument("--trace",                action="store_true",   help="Enable VCD tracing")
-    parser.add_argument("--trace-start",          default=0,             help="Cycle to start VCD tracing")
-    parser.add_argument("--trace-end",            default=-1,            help="Cycle to end VCD tracing")
-    parser.add_argument("--opt-level",            default="O3",          help="Compilation optimization level")
+    parser.add_argument("--threads",              default=1,               help="Set number of threads (default=1)")
+    parser.add_argument("--rom-init",             default=None,            help="rom_init file")
+    parser.add_argument("--ram-init",             default=None,            help="ram_init file")
+    parser.add_argument("--with-sdram",           action="store_true",     help="Enable SDRAM support")
+    parser.add_argument("--sdram-module",         default="MT48LC16M16",   help="Select SDRAM chip")
+    parser.add_argument("--sdram-data-width",     default=32,              help="Set SDRAM chip data width")
+    parser.add_argument("--sdram-init",           default=None,            help="SDRAM init file")
+    parser.add_argument("--sdram-no-timing",      action="store_true",     help="Disable SDRAM timing verification checks")
+    parser.add_argument("--sdram-verbose-timing", action="store_true",     help="Enable SDRAM verbose timing logging")
+    parser.add_argument("--with-ethernet",        action="store_true",     help="Enable Ethernet support")
+    parser.add_argument("--with-etherbone",       action="store_true",     help="Enable Etherbone support")
+    parser.add_argument("--local-ip",             default="192.168.1.50",  help="Local IP address of SoC")
+    parser.add_argument("--remote-ip",            default="192.168.1.100", help="Remote IP address of TFTP server")
+    parser.add_argument("--with-analyzer",        action="store_true",     help="Enable Analyzer support")
+    parser.add_argument("--trace",                action="store_true",     help="Enable VCD tracing")
+    parser.add_argument("--trace-start",          default=0,               help="Cycle to start VCD tracing")
+    parser.add_argument("--trace-end",            default=-1,              help="Cycle to end VCD tracing")
+    parser.add_argument("--opt-level",            default="O3",            help="Compilation optimization level")
     args = parser.parse_args()
 
     soc_kwargs     = soc_sdram_argdict(args)
@@ -301,7 +303,7 @@ def main():
         soc_kwargs["sdram_verbose_timings"] = args.sdram_verbose_timing
 
     if args.with_ethernet or args.with_etherbone:
-        sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
+        sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})
 
     # SoC ------------------------------------------------------------------------------------------
     soc = SimSoC(
@@ -313,6 +315,11 @@ def main():
         **soc_kwargs)
     if args.ram_init is not None:
         soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
+    if args.with_ethernet:
+        for i in range(4):
+            soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))
+        for i in range(4):
+            soc.add_constant("REMOTEIP{}".format(i+1), int(args.remote_ip.split(".")[i]))
 
     # Build/Run ------------------------------------------------------------------------------------
     builder_kwargs["csr_csv"] = "csr.csv"