Ooops AREG and BREG to default to -1

diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 714316808eb07566b74f0b983fa927ea2394c77e..6f4ac584974257e7c814ebd5bb055294f6b332fc 100644 (file)
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -146,7 +146,7 @@ code next
 endcode
 
 code argQ clock AREG
-       AREG = 0;
+       AREG = -1;
        if (next) {
                Cell *prev = std::get<0>(chain.back());
                if (param(prev, \AREG, 2).as_int() > 0 &&
@@ -175,7 +175,7 @@ reject_AREG:                        ;
 endcode
 
 code argQ clock BREG
-       BREG = 0;
+       BREG = -1;
        if (next) {
                Cell *prev = std::get<0>(chain.back());
                if (param(prev, \BREG, 2).as_int() > 0 &&