RISC-V: Updated the default ISA spec to 20191213.

Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1.  Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions.  Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.

bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
	recognize zicsr and zifencei.
gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
	* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
	* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
	* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
	into Tag_RISCV_arch since it is added implied when i's version is
	larger than 2.1.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 8409c0254e594c1f295fb0b054b84ae5a6c987f7..9f52bb545ac55814a1e480668eb3d9daf271d874 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1562,7 +1562,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
        rps->error_handler
          (_("x ISA extension `%s' must be set with the versions"),
           subset);
-      else
+      /* Allow old ISA spec can recognize zicsr and zifencei.  */
+      else if (strcmp (subset, "zicsr") != 0
+              && strcmp (subset, "zifencei") != 0)
        rps->error_handler
          (_("cannot find default versions of the ISA extension `%s'"),
           subset);

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5f8e1181baa82c7ac1bc5b5e602e45f2e1a60643..1eed63cb38f0563aa786662cd30ab0cda9261f9e 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -104,7 +104,7 @@ struct riscv_csr_extra
 
 /* Need to sync the version with RISC-V compiler.  */
 #ifndef DEFAULT_RISCV_ISA_SPEC
-#define DEFAULT_RISCV_ISA_SPEC "2.2"
+#define DEFAULT_RISCV_ISA_SPEC "20191213"
 #endif
 
 #ifndef DEFAULT_RISCV_PRIV_SPEC

diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index ee56ae31f0c77ce2a7254ce2c27a221ca0d2b37d..88da7240a782ce42fd867cbb0462ad8b30dbcfed 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.10
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.10
 #source: csr.s
 #warning_output: csr-version-1p10.l
 #objdump: -dr -Mpriv-spec=1.10

diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index a1d8169d7f732ec2e84a386b4943c6048bfccad4..b40c1d5d6b9733200e94db13d181a781848a36a9 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.11
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.11
 #source: csr.s
 #warning_output: csr-version-1p11.l
 #objdump: -dr -Mpriv-spec=1.11

diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index c4c211829b21b2e83805e8fb43ea3057c5c45d09..fbc30ee2fcca16c18d63563f75e626aba03511a2 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.12
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.12
 #source: csr.s
 #warning_output: csr-version-1p12.l
 #objdump: -dr -Mpriv-spec=1.12

diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index 01e05ae4fbc42289fa88d358c094c9dee22d0490..a96e8c9dbec31c6982b53935f41352bc01f9ec85 100644 (file)
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i -mcsr-check -mpriv-spec=1.9.1
+#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1
 #source: csr.s
 #warning_output: csr-version-1p9p1.l
 #objdump: -dr -Mpriv-spec=1.9.1

diff --git a/gas/testsuite/gas/riscv/option-arch-03.d b/gas/testsuite/gas/riscv/option-arch-03.d
index b621d036c29e3ba4fc046576e2aa2eec904e9037..62d7f7d5ed21db19d193867467b144a2d2f74741 100644 (file)
--- a/gas/testsuite/gas/riscv/option-arch-03.d
+++ b/gas/testsuite/gas/riscv/option-arch-03.d
@@ -4,5 +4,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_c2p0"
+  Tag_RISCV_arch: "rv32i2p1_c2p0"
 #...

diff --git a/gas/testsuite/gas/riscv/option-arch-03.s b/gas/testsuite/gas/riscv/option-arch-03.s
index d982a0b09858619eb4593c3b1151c1b7e5b9b9e9..ccdb1c354b0ffb87e9c3496e30aff9821d675a42 100644 (file)
--- a/gas/testsuite/gas/riscv/option-arch-03.s
+++ b/gas/testsuite/gas/riscv/option-arch-03.s
@@ -1,3 +1,3 @@
 .attribute arch, "rv64ic"
 .option arch, +d2p0, -c
-.option arch, rv32ic
+.option arch, rv32i2p1c2p0

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index c148cdbc4f425fe07449794cdc2c0859c22a3990..a4b0322a3d926e50410cb16fd9f3f5e19bc05dd6 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
index acc98a53cf5021416313e085fd9fe8cd2d57571f..ea097f99b04263fc4af76d5f86812bf3737d0a1a 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p0_m2p0"
+       .attribute arch, "rv32i2p1_m2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
index acc98a53cf5021416313e085fd9fe8cd2d57571f..ea097f99b04263fc4af76d5f86812bf3737d0a1a 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p0_m2p0"
+       .attribute arch, "rv32i2p1_m2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index bc0e0fd13841f113887c79a13d69531655a0b032..852fd55ae08270a399e7505a5a53384b43a89b09 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
index acc98a53cf5021416313e085fd9fe8cd2d57571f..ea097f99b04263fc4af76d5f86812bf3737d0a1a 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p0_m2p0"
+       .attribute arch, "rv32i2p1_m2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
index 65d0fefd5afe6b1decb74c573003866ad43f3f20..610c7e53c1a75d092fd7721219bc361da39c0348 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p0"
+       .attribute arch, "rv32i2p1"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index 374a043c69ed9613365651dd56e2b622cc2a6c61..c1cf8081dc7ee811bb58f790d5ef328bf94ff68e 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
index b86cc558fbfa61b850d89a1276eadb30e40bec75..3a9fb97ac4eb79fe109e2eb7c694302043cdb99a 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p0_m2p0_xfoo2p0"
+       .attribute arch, "rv32i2p1_m2p0_xfoo2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
index 376e3737b2c0ed6c1ec167254540d3fc99477b03..878f2de8e5312f3e51415ee2463ed3998da26bec 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
@@ -1 +1 @@
-       .attribute arch, "rv32i2p0_xbar2p0"
+       .attribute arch, "rv32i2p1_xbar2p0"

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
index 3f4935df54c7b08ce4c73de1aaf46edf333d475a..2f2638ace22189851b94f88e8e94442c3265f10d 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
@@ -23,5 +23,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_xunknown4p0"
+  Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_zifencei2p0_xunknown4p0"
 #..

diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index c6022bec262a4a5bf1aaf46a294af4784bb12d45..f8f022982320eb9a7756f3459271557f4ddea06c 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -3,7 +3,7 @@
 #source: call-relax-1.s
 #source: call-relax-2.s
 #source: call-relax-3.s
-#as: -march=rv32ic -mno-arch-attr
+#as: -march=rv32ic_zicsr -mno-arch-attr
 #ld: -m[riscv_choose_ilp32_emul]
 #objdump: -d
 #pass