[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

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+Date: Fri, 03 Apr 2020 13:42:15 +0000
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+X-Bugzilla-Product: Libre-SOC's first SoC
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: whitequark@whitequark.org
+X-Bugzilla-Status: CONFIRMED
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+Message-ID: <bug-276-13-5ND3uLuvrS@http.bugs.libre-riscv.org/>
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+Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
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