i965/hiz: Start to separate miptree out from hiz buffers

Today we allocate a miptree's for the hiz buffer. We needed this in
the past because we would point the hardware at offsets of the hiz
buffer. Since the hiz format is not documented, this is not a good
idea.

Since moving to support layered rendering on Gen7+, we no longer point
at an offset into the buffer on Gen7+.

Therefore, to support hiz on Gen7+, we don't need a full miptree
structure allocated.

This patch starts to create a new auxiliary buffer structure
(intel_miptree_aux_buffer) that can be a more simplistic miptree
side-band buffer associated with a miptree. (For example, to serve the
needs of the hiz buffer.)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 190cdf76135c98a215b4f92c49b725bb2137ae4c..bc810769793f8c816aaea41eaa6fb883abc6bb2b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -172,7 +172,7 @@ brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
 
       if (intel_miptree_level_has_hiz(depth_mt, depth_level)) {
          uint32_t hiz_tile_mask_x, hiz_tile_mask_y;
-         intel_miptree_get_tile_masks(depth_mt->hiz_mt,
+         intel_miptree_get_tile_masks(depth_mt->hiz_buf->mt,
                                       &hiz_tile_mask_x, &hiz_tile_mask_y,
                                       false);
 
@@ -632,7 +632,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
 
       /* Emit hiz buffer. */
       if (hiz) {
-         struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
+         struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
         BEGIN_BATCH(3);
         OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
         OUT_BATCH(hiz_mt->pitch - 1);

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 372846b07163685ea5d4bb1e388e60e8bbb99973..e45705afe91314ef93bd806ff6be368bf5baf441 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -857,7 +857,7 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
-      struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
+      struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_buf->mt;
       uint32_t offset = 0;
 
       if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {

diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index effb9c638cc35e49a2a0fcd23998ef753a063b74..1df0bd475714a29fe51941d4dd2b8e7ea7ebb75e 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -156,7 +156,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 
       /* Emit hiz buffer. */
       if (hiz) {
-         struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
+         struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
          uint32_t offset = 0;
 
          if (hiz_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 206a6ff6d5da8dac9a26da04085e87e30e970c3d..6ba65d67f6cce9d9be0071e4071bffd4146e58da 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -695,7 +695,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
-      struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
+      struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_buf->mt;
 
       BEGIN_BATCH(3);
       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 33d4ade4fe516fc390f2d444c0a9a91df3a03652..cc74570ee372646e635ff37c909f0af810d7764c 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -145,7 +145,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
-      struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
+      struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
       BEGIN_BATCH(3);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
       OUT_BATCH((mocs << 25) |

diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 5c56d518eb8527d15a1e515db081a2d6ef40ccaf..9af9898cad3ca97e2e58c97de3b126840cea6581 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -92,10 +92,10 @@ emit_depth_packets(struct brw_context *brw,
    } else {
       BEGIN_BATCH(5);
       OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
-      OUT_BATCH((depth_mt->hiz_mt->pitch - 1) | mocs_wb << 25);
-      OUT_RELOC64(depth_mt->hiz_mt->bo,
+      OUT_BATCH((depth_mt->hiz_buf->mt->pitch - 1) | mocs_wb << 25);
+      OUT_RELOC64(depth_mt->hiz_buf->mt->bo,
                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-      OUT_BATCH(depth_mt->hiz_mt->qpitch >> 2);
+      OUT_BATCH(depth_mt->hiz_buf->mt->qpitch >> 2);
       ADVANCE_BATCH();
    }
 

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index 57cf583cbe8672dcf047f2742b34291d7d248f5e..2cf4771d539c6d571e7ed35370eb6f4415ae3119 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -561,9 +561,9 @@ intel_renderbuffer_update_wrapper(struct brw_context *brw,
 
    intel_renderbuffer_set_draw_offset(irb);
 
-   if (mt->hiz_mt == NULL && brw_is_hiz_depth_format(brw, rb->Format)) {
+   if (mt->hiz_buf == NULL && brw_is_hiz_depth_format(brw, rb->Format)) {
       intel_miptree_alloc_hiz(brw, mt);
-      if (!mt->hiz_mt)
+      if (!mt->hiz_buf)
         return false;
    }
 

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 36c3b26668b17a248f9737560a3e3a10b8e649a5..6c4cc7fef2d99eb945586bd9e399034f292a44d1 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -883,7 +883,10 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
 
       drm_intel_bo_unreference((*mt)->bo);
       intel_miptree_release(&(*mt)->stencil_mt);
-      intel_miptree_release(&(*mt)->hiz_mt);
+      if ((*mt)->hiz_buf) {
+         intel_miptree_release(&(*mt)->hiz_buf->mt);
+         free((*mt)->hiz_buf);
+      }
       intel_miptree_release(&(*mt)->mcs_mt);
       intel_resolve_map_clear(&(*mt)->hiz_map);
 
@@ -1415,7 +1418,7 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
                                struct intel_mipmap_tree *mt,
                                uint32_t level)
 {
-   assert(mt->hiz_mt);
+   assert(mt->hiz_buf);
 
    if (brw->gen >= 8 || brw->is_haswell) {
       uint32_t width = minify(mt->physical_width0, level);
@@ -1439,27 +1442,49 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
 }
 
 
+static struct intel_miptree_aux_buffer *
+intel_hiz_miptree_buf_create(struct brw_context *brw,
+                             struct intel_mipmap_tree *mt)
+{
+   struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
+   const bool force_all_slices_at_each_lod = brw->gen == 6;
+
+   if (!buf)
+      return NULL;
+
+   buf->mt = intel_miptree_create(brw,
+                                  mt->target,
+                                  mt->format,
+                                  mt->first_level,
+                                  mt->last_level,
+                                  mt->logical_width0,
+                                  mt->logical_height0,
+                                  mt->logical_depth0,
+                                  true,
+                                  mt->num_samples,
+                                  INTEL_MIPTREE_TILING_ANY,
+                                  force_all_slices_at_each_lod);
+   if (!buf->mt) {
+      free(buf);
+      return NULL;
+   }
+
+   buf->bo = buf->mt->bo;
+   buf->pitch = buf->mt->pitch;
+   buf->qpitch = buf->mt->qpitch;
+
+   return buf;
+}
+
 
 bool
 intel_miptree_alloc_hiz(struct brw_context *brw,
                        struct intel_mipmap_tree *mt)
 {
-   assert(mt->hiz_mt == NULL);
-   const bool force_all_slices_at_each_lod = brw->gen == 6;
-   mt->hiz_mt = intel_miptree_create(brw,
-                                     mt->target,
-                                     mt->format,
-                                     mt->first_level,
-                                     mt->last_level,
-                                     mt->logical_width0,
-                                     mt->logical_height0,
-                                     mt->logical_depth0,
-                                     true,
-                                     mt->num_samples,
-                                     INTEL_MIPTREE_TILING_ANY,
-                                     force_all_slices_at_each_lod);
+   assert(mt->hiz_buf == NULL);
+   mt->hiz_buf = intel_hiz_miptree_buf_create(brw, mt);
 
-   if (!mt->hiz_mt)
+   if (!mt->hiz_buf)
       return false;
 
    /* Mark that all slices need a HiZ resolve. */

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index ee9cf1ea4a9a892fdae17a97e1677b64b1400946..41b60363f6c3ea32afde6e61f2cbc9c02c87cbbb 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -307,6 +307,29 @@ enum miptree_array_layout {
    ALL_SLICES_AT_EACH_LOD,
 };
 
+/**
+ * Miptree aux buffer. These buffers are associated with a miptree, but the
+ * format is managed by the hardware.
+ *
+ * For Gen7+, we always give the hardware the start of the buffer, and let it
+ * handle all accesses to the buffer. Therefore we don't need the full miptree
+ * layout structure for this buffer.
+ *
+ * For Gen6, we need a hiz miptree structure for this buffer so we can program
+ * offsets to slices & miplevels.
+ */
+struct intel_miptree_aux_buffer
+{
+   /** Buffer object containing the pixel data. */
+   drm_intel_bo *bo;
+
+   uint32_t pitch; /**< pitch in bytes. */
+
+   uint32_t qpitch; /**< The distance in rows between array slices. */
+
+   struct intel_mipmap_tree *mt; /**< hiz miptree used with Gen6 */
+};
+
 struct intel_mipmap_tree
 {
    /** Buffer object containing the pixel data. */
@@ -411,15 +434,15 @@ struct intel_mipmap_tree
    uint32_t offset;
 
    /**
-    * \brief HiZ miptree
+    * \brief HiZ aux buffer
     *
     * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz
-    * miptree, use intel_miptree_alloc_hiz().
+    * buffer, use intel_miptree_alloc_hiz().
     *
     * To determine if hiz is enabled, do not check this pointer. Instead, use
     * intel_miptree_slice_has_hiz().
     */
-   struct intel_mipmap_tree *hiz_mt;
+   struct intel_miptree_aux_buffer *hiz_buf;
 
    /**
     * \brief Map of miptree slices to needed resolves.