examples: remove old-style declarations

diff --git a/examples/corelogic_conv.py b/examples/corelogic_conv.py
index be3602c4009f666e99636756b7aaea6cc6084b7f..9ea4282d591c98b5b6b0ec635f60274c0f20dc7e 100644 (file)
--- a/examples/corelogic_conv.py
+++ b/examples/corelogic_conv.py
@@ -1,4 +1,3 @@
-from migen.fhdl import structure as f
 from migen.fhdl import verilog
 from migen.corelogic import roundrobin, divider
 

diff --git a/examples/lm32_inst.py b/examples/lm32_inst.py
index c6e043ce6b946884487a03396c420e308a782b41..54e75ae231453ad8362730961259db65bd1002d1 100644 (file)
--- a/examples/lm32_inst.py
+++ b/examples/lm32_inst.py
@@ -1,47 +1,47 @@
-from migen.fhdl import structure as f
+from migen.fhdl.structure import *
 from migen.fhdl import verilog
 
 class LM32:
        def __init__(self):
-               self.inst = f.Instance("lm32_top",
-                       [("I_ADR_O", f.BV(32)),
-                       ("I_DAT_O", f.BV(32)),
-                       ("I_SEL_O", f.BV(4)),
-                       ("I_CYC_O", f.BV(1)),
-                       ("I_STB_O", f.BV(1)),
-                       ("I_WE_O", f.BV(1)),
-                       ("I_CTI_O", f.BV(3)),
-                       ("I_LOCK_O", f.BV(1)),
-                       ("I_BTE_O", f.BV(1)),
-                       ("D_ADR_O", f.BV(32)),
-                       ("D_DAT_O", f.BV(32)),
-                       ("D_SEL_O", f.BV(4)),
-                       ("D_CYC_O", f.BV(1)),
-                       ("D_STB_O", f.BV(1)),
-                       ("D_WE_O", f.BV(1)),
-                       ("D_CTI_O", f.BV(3)),
-                       ("D_LOCK_O", f.BV(1)),
-                       ("D_BTE_O", f.BV(1))],
-                       [("interrupt", f.BV(32)),
-                       ("ext_break", f.BV(1)),
-                       ("I_DAT_I", f.BV(32)),
-                       ("I_ACK_I", f.BV(1)),
-                       ("I_ERR_I", f.BV(1)),
-                       ("I_RTY_I", f.BV(1)),
-                       ("D_DAT_I", f.BV(32)),
-                       ("D_ACK_I", f.BV(1)),
-                       ("D_ERR_I", f.BV(1)),
-                       ("D_RTY_I", f.BV(1))],
+               self.inst = Instance("lm32_top",
+                       [("I_ADR_O", BV(32)),
+                       ("I_DAT_O", BV(32)),
+                       ("I_SEL_O", BV(4)),
+                       ("I_CYC_O", BV(1)),
+                       ("I_STB_O", BV(1)),
+                       ("I_WE_O", BV(1)),
+                       ("I_CTI_O", BV(3)),
+                       ("I_LOCK_O", BV(1)),
+                       ("I_BTE_O", BV(1)),
+                       ("D_ADR_O", BV(32)),
+                       ("D_DAT_O", BV(32)),
+                       ("D_SEL_O", BV(4)),
+                       ("D_CYC_O", BV(1)),
+                       ("D_STB_O", BV(1)),
+                       ("D_WE_O", BV(1)),
+                       ("D_CTI_O", BV(3)),
+                       ("D_LOCK_O", BV(1)),
+                       ("D_BTE_O", BV(1))],
+                       [("interrupt", BV(32)),
+                       ("ext_break", BV(1)),
+                       ("I_DAT_I", BV(32)),
+                       ("I_ACK_I", BV(1)),
+                       ("I_ERR_I", BV(1)),
+                       ("I_RTY_I", BV(1)),
+                       ("D_DAT_I", BV(32)),
+                       ("D_ACK_I", BV(1)),
+                       ("D_ERR_I", BV(1)),
+                       ("D_RTY_I", BV(1))],
                        [],
                        "clk_i",
                        "rst_i",
                        "lm32")
        
        def get_fragment(self):
-               return f.Fragment(instances=[self.inst])
+               return Fragment(instances=[self.inst])
 
 cpus = [LM32() for i in range(4)]
-frag = f.Fragment()
+frag = Fragment()
 for cpu in cpus:
        frag += cpu.get_fragment()
 print(verilog.Convert(frag, set([cpus[0].inst.ins["interrupt"], cpus[0].inst.outs["I_WE_O"]])))

diff --git a/examples/simple_gpio.py b/examples/simple_gpio.py
index b6d0943cd7cc0712a015f7757c63735b9d4d3885..da2bd28b3496f71871a73ea4999d4e774ee66bd8 100644 (file)
--- a/examples/simple_gpio.py
+++ b/examples/simple_gpio.py
@@ -1,4 +1,4 @@
-from migen.fhdl import structure as f
+from migen.fhdl.structure import *
 from migen.fhdl import verilog
 from migen.bank import description, csrgen
 
@@ -11,11 +11,11 @@ ireg = description.Register("i")
 ifield = description.Field(ireg, "val", ninputs, description.READ_ONLY, description.WRITE_ONLY)
 
 # input path
-gpio_in = f.Signal(f.BV(ninputs), name="gpio_in")
-gpio_in_s = f.Signal(f.BV(ninputs), name="gpio_in_s") # synchronizer
-incomb = [f.Assign(ifield.dev_we, 1)]
-insync = [f.Assign(gpio_in_s, gpio_in), f.Assign(ifield.dev_w, gpio_in_s)]
-inf = f.Fragment(incomb, insync)
+gpio_in = Signal(BV(ninputs))
+gpio_in_s = Signal(BV(ninputs)) # synchronizer
+incomb = [ifield.dev_we.eq(1)]
+insync = [gpio_in_s.eq(gpio_in), ifield.dev_w.eq(gpio_in_s)]
+inf = Fragment(incomb, insync)
 
 bank = csrgen.Bank([oreg, ireg])
 f = bank.get_fragment() + inf

diff --git a/examples/wb_intercon/intercon_conv.py b/examples/wb_intercon/intercon_conv.py
index 2bd788ff6c5f853aa2ece6e2022f4b46f3fc151a..28cffb28f32fa57dd6f9278927ba47fe99874eb3 100644 (file)
--- a/examples/wb_intercon/intercon_conv.py
+++ b/examples/wb_intercon/intercon_conv.py
@@ -1,5 +1,4 @@
 from migen.fhdl import verilog
-from migen.fhdl import structure as f
 from migen.bus import wishbone
 
 m1 = wishbone.Master("m1")