sim: cris: update testsuite output after strsignal change

diff --git a/sim/testsuite/sim/cris/ChangeLog b/sim/testsuite/sim/cris/ChangeLog
index eb8efc99fab858154d56c32bd810b8e11fa09007..f206a4055f248e14571fbe32d97dda90bf92db51 100644 (file)
--- a/sim/testsuite/sim/cris/ChangeLog
+++ b/sim/testsuite/sim/cris/ChangeLog
@@ -1,3 +1,16 @@
+2012-03-21  Mike Frysinger  <vapier@gentoo.org>
+
+       * asm/addqpc.ms: Update output to ignore decoded signal string.
+       * asm/boundmv32.ms, asm/fidxd.ms, asm/fidxi.ms, asm/ftagd.ms,
+       asm/ftagi.ms, asm/halt.ms, asm/io6.ms, asm/io7.ms, asm/io8.ms,
+       asm/io9.ms, asm/movecpc.ms, asm/movempc.ms, asm/movepcb.ms,
+       asm/movepcd.ms, asm/movepcw.ms, asm/moveqpc.ms, asm/moverbpc.ms,
+       asm/moverdpc.ms, asm/moverpcb.ms, asm/moverpcw.ms, asm/moverwpc.ms,
+       asm/movppc.ms, asm/movrss.ms, asm/movscpc.ms, asm/movsmpc.ms,
+       asm/movsrpc.ms, asm/movssr.ms, asm/movucpc.ms, asm/movumpc.ms,
+       asm/movurpc.ms, asm/msteppc1.ms, asm/msteppc2.ms, asm/msteppc3.ms,
+       asm/rfg.ms, asm/sbfs.ms, asm/subqpc.ms: Likewise.
+
 2010-10-07  Hans-Peter Nilsson  <hp@axis.com>
 
        * c/seek3.c, c/seek4.c: New tests.

diff --git a/sim/testsuite/sim/cris/asm/addqpc.ms b/sim/testsuite/sim/cris/asm/addqpc.ms
index 13e293e07ac27658dd2c7d16cebbf5c665fb5151..ba5a1ec239c93a33955735e807bdbb68a0eb1c16 100644 (file)
--- a/sim/testsuite/sim/cris/asm/addqpc.ms
+++ b/sim/testsuite/sim/cris/asm/addqpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/boundmv32.ms b/sim/testsuite/sim/cris/asm/boundmv32.ms
index 4aad1ef58ef6b99c4a6ec6165f3a43201de7e031..560276eae612186492a67fe1ace0ac76af669c87 100644 (file)
--- a/sim/testsuite/sim/cris/asm/boundmv32.ms
+++ b/sim/testsuite/sim/cris/asm/boundmv32.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: program stopped with signal 4.\n
+# output: program stopped with signal 4 (*).\n
  .include "testutils.inc"
 
 ; Check that bound with a memory operand is invalid.

diff --git a/sim/testsuite/sim/cris/asm/fidxd.ms b/sim/testsuite/sim/cris/asm/fidxd.ms
index 447e397e178f5ac6be2e3f29a40b644c3e1f8391..8158682117dd30e9c5077633244d4a03a1bae1ef 100644 (file)
--- a/sim/testsuite/sim/cris/asm/fidxd.ms
+++ b/sim/testsuite/sim/cris/asm/fidxd.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: FIDXD isn't implemented\nprogram stopped with signal 5.\n
+# output: FIDXD isn't implemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/fidxi.ms b/sim/testsuite/sim/cris/asm/fidxi.ms
index fdee4483d5484155971e47971f84ec07f70a6f78..1c41ed4c2f60e390e9d79dcfeb51db7e35a3c1e8 100644 (file)
--- a/sim/testsuite/sim/cris/asm/fidxi.ms
+++ b/sim/testsuite/sim/cris/asm/fidxi.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: FIDXI isn't implemented\nprogram stopped with signal 5.\n
+# output: FIDXI isn't implemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/ftagd.ms b/sim/testsuite/sim/cris/asm/ftagd.ms
index 87c7f130adf00ad2659c3e206342e005063b01a4..74d4de34130dbeaf03aa09563ad7edcefcd09323 100644 (file)
--- a/sim/testsuite/sim/cris/asm/ftagd.ms
+++ b/sim/testsuite/sim/cris/asm/ftagd.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: FTAGD isn't implemented\nprogram stopped with signal 5.\n
+# output: FTAGD isn't implemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/ftagi.ms b/sim/testsuite/sim/cris/asm/ftagi.ms
index 506847648dbd1160d1037ae0d5fd1444e1e0cf5f..187d22d33a403321a645315cc65339da161d4926 100644 (file)
--- a/sim/testsuite/sim/cris/asm/ftagi.ms
+++ b/sim/testsuite/sim/cris/asm/ftagi.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: FTAGI isn't implemented\nprogram stopped with signal 5.\n
+# output: FTAGI isn't implemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/halt.ms b/sim/testsuite/sim/cris/asm/halt.ms
index 368c367479b50631589733fead2aafd995103b29..fb4dcb0be57d1723a0826cdff4830703e3344d39 100644 (file)
--- a/sim/testsuite/sim/cris/asm/halt.ms
+++ b/sim/testsuite/sim/cris/asm/halt.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: HALT isn't implemented\nprogram stopped with signal 5.\n
+# output: HALT isn't implemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/io6.ms b/sim/testsuite/sim/cris/asm/io6.ms
index 6f3c25d04b836c1537686f4614f1ccde35905365..3af3536265e03482e3e23db6410e003a036509a4 100644 (file)
--- a/sim/testsuite/sim/cris/asm/io6.ms
+++ b/sim/testsuite/sim/cris/asm/io6.ms
@@ -4,7 +4,7 @@
 # xerror:
 # output: b1e\n
 # output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
-# output: program stopped with signal 11.\n
+# output: program stopped with signal 11 (*).\n
 
 ; Check that invalid access to the simulator area is recognized.
 ; "FAIL" area.

diff --git a/sim/testsuite/sim/cris/asm/io7.ms b/sim/testsuite/sim/cris/asm/io7.ms
index 8c8b46122d02a5627e9fefdaa5e0a3b49a35ff28..84488e9452ed5e997415485d3dd47700ff7c0cc5 100644 (file)
--- a/sim/testsuite/sim/cris/asm/io7.ms
+++ b/sim/testsuite/sim/cris/asm/io7.ms
@@ -4,7 +4,7 @@
 # xerror:
 # output: ce11d0c\n
 # output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n
-# output: program stopped with signal 11.\n
+# output: program stopped with signal 11 (*).\n
 
 ; Check that invalid access to the simulator area is recognized.
 ; "PASS" area.

diff --git a/sim/testsuite/sim/cris/asm/io8.ms b/sim/testsuite/sim/cris/asm/io8.ms
index 0ba9287b8818270e284ac4d43a75b28982004693..49163fd04238cc291421a231b2adf74294c86158 100644 (file)
--- a/sim/testsuite/sim/cris/asm/io8.ms
+++ b/sim/testsuite/sim/cris/asm/io8.ms
@@ -3,7 +3,7 @@
 # xerror:
 # output: b1e\n
 # output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
-# output: program stopped with signal 11.\n
+# output: program stopped with signal 11 (*).\n
 
 ; Check invalid access valid with --cris-900000xx.
 ; "FAIL" area.

diff --git a/sim/testsuite/sim/cris/asm/io9.ms b/sim/testsuite/sim/cris/asm/io9.ms
index afcb5913ac6f85ee3e73477babcd3b0fca63db7d..3b929a3c8a09f1a8fe2a370e0ade34c00c94be70 100644 (file)
--- a/sim/testsuite/sim/cris/asm/io9.ms
+++ b/sim/testsuite/sim/cris/asm/io9.ms
@@ -3,7 +3,7 @@
 # xerror:
 # output: ce11d0c\n
 # output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n
-# output: program stopped with signal 11.\n
+# output: program stopped with signal 11 (*).\n
 
 ; Check invalid access valid with --cris-900000xx.
 ; "PASS" area.

diff --git a/sim/testsuite/sim/cris/asm/movecpc.ms b/sim/testsuite/sim/cris/asm/movecpc.ms
index cba1c2123058181e69440e4ace8ff072ef1a0de7..880a0f8f3db260b6d2a606242a8ecf51b6bfb1e1 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movecpc.ms
+++ b/sim/testsuite/sim/cris/asm/movecpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
 # We deliberately match both "read from" and "write to" above.
 

diff --git a/sim/testsuite/sim/cris/asm/movempc.ms b/sim/testsuite/sim/cris/asm/movempc.ms
index 1fd141674692cc7e8807b2c8bf68b16947e8283d..cbbfcc1725f9ae044d2b08bca2a59091a1d1f050 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movempc.ms
+++ b/sim/testsuite/sim/cris/asm/movempc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movepcb.ms b/sim/testsuite/sim/cris/asm/movepcb.ms
index 0dcc396d3b0295b3e2b30c105a16aa7f11d57419..b06932e5793a3f943987bbf4b94b39cb0d4020b9 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movepcb.ms
+++ b/sim/testsuite/sim/cris/asm/movepcb.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  startnostack

diff --git a/sim/testsuite/sim/cris/asm/movepcd.ms b/sim/testsuite/sim/cris/asm/movepcd.ms
index 240db55d3ba92dcc4ff8df6e802b2e3fc36c8012..2ed0060c257ab9355c28a96c702439a2754851dd 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movepcd.ms
+++ b/sim/testsuite/sim/cris/asm/movepcd.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
 # Both source and dest contain PC for "test.d r" (move.d r,r).  Ideally,
 # the output message should say "read" of PC, but we allow PC as source in

diff --git a/sim/testsuite/sim/cris/asm/movepcw.ms b/sim/testsuite/sim/cris/asm/movepcw.ms
index d51b0d9c0c71f5262dd28ceb6fc6536b89d045a6..0f3b6a2e3b70d339a05ff4561dd7f622f9756c3f 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movepcw.ms
+++ b/sim/testsuite/sim/cris/asm/movepcw.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  startnostack

diff --git a/sim/testsuite/sim/cris/asm/moveqpc.ms b/sim/testsuite/sim/cris/asm/moveqpc.ms
index dea5106ab056926dec7a5b874da5ab9b42afcb1b..d5e856b3024d84ee93e6c306e24f9414a4b45ace 100644 (file)
--- a/sim/testsuite/sim/cris/asm/moveqpc.ms
+++ b/sim/testsuite/sim/cris/asm/moveqpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  startnostack

diff --git a/sim/testsuite/sim/cris/asm/moverbpc.ms b/sim/testsuite/sim/cris/asm/moverbpc.ms
index 34a1f3c0188ab53f5273f675f08753af17d454f4..b5ea388e842b09539b7c6ef4daef04ce468ebbcf 100644 (file)
--- a/sim/testsuite/sim/cris/asm/moverbpc.ms
+++ b/sim/testsuite/sim/cris/asm/moverbpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  startnostack

diff --git a/sim/testsuite/sim/cris/asm/moverdpc.ms b/sim/testsuite/sim/cris/asm/moverdpc.ms
index 34a1f3c0188ab53f5273f675f08753af17d454f4..b5ea388e842b09539b7c6ef4daef04ce468ebbcf 100644 (file)
--- a/sim/testsuite/sim/cris/asm/moverdpc.ms
+++ b/sim/testsuite/sim/cris/asm/moverdpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  startnostack

diff --git a/sim/testsuite/sim/cris/asm/moverpcb.ms b/sim/testsuite/sim/cris/asm/moverpcb.ms
index d95d9dafcb13f3d3ede4835872d4ad2aee83e8db..13e04b160115cb120bb21254ca38aaf1408592f0 100644 (file)
--- a/sim/testsuite/sim/cris/asm/moverpcb.ms
+++ b/sim/testsuite/sim/cris/asm/moverpcb.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  startnostack

diff --git a/sim/testsuite/sim/cris/asm/moverpcw.ms b/sim/testsuite/sim/cris/asm/moverpcw.ms
index 88681fb505a0c283ffb8b79a6e21aadacce55132..9b8f92984e14928187eef99245717eb89de80794 100644 (file)
--- a/sim/testsuite/sim/cris/asm/moverpcw.ms
+++ b/sim/testsuite/sim/cris/asm/moverpcw.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  startnostack

diff --git a/sim/testsuite/sim/cris/asm/moverwpc.ms b/sim/testsuite/sim/cris/asm/moverwpc.ms
index 34a1f3c0188ab53f5273f675f08753af17d454f4..b5ea388e842b09539b7c6ef4daef04ce468ebbcf 100644 (file)
--- a/sim/testsuite/sim/cris/asm/moverwpc.ms
+++ b/sim/testsuite/sim/cris/asm/moverwpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  startnostack

diff --git a/sim/testsuite/sim/cris/asm/movppc.ms b/sim/testsuite/sim/cris/asm/movppc.ms
index e100e25dd75df2ef1fd6a680eab4ba19f13db2af..ee7e8d140ad65506662148c0a8dc39db39dfcadc 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movppc.ms
+++ b/sim/testsuite/sim/cris/asm/movppc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movrss.ms b/sim/testsuite/sim/cris/asm/movrss.ms
index 964c1611483f74c2cfa77a464c97578748cb3a0e..42305f9d6a7e08c7d2e3efbc2bd2404ada0b49c4 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movrss.ms
+++ b/sim/testsuite/sim/cris/asm/movrss.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: Write to support register is unimplemented\nprogram stopped with signal 5.\n
+# output: Write to support register is unimplemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movscpc.ms b/sim/testsuite/sim/cris/asm/movscpc.ms
index a753e236347fc1bf921c2ca8050199e68463d2ae..98618966f0f86429d41b22bd8f1e7b9fbbee3ea8 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movscpc.ms
+++ b/sim/testsuite/sim/cris/asm/movscpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movsmpc.ms b/sim/testsuite/sim/cris/asm/movsmpc.ms
index 16d818b8d303ead00fc3835eef45727efbe33ae8..95f40ad0ac3ca0b7e322f945939524844008a7a1 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movsmpc.ms
+++ b/sim/testsuite/sim/cris/asm/movsmpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movsrpc.ms b/sim/testsuite/sim/cris/asm/movsrpc.ms
index fccf31a1ce84f90049685bee455c101ea115866d..6971e378338f469eb082496c6324a5b58e63fa49 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movsrpc.ms
+++ b/sim/testsuite/sim/cris/asm/movsrpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movssr.ms b/sim/testsuite/sim/cris/asm/movssr.ms
index 62663c1c04a744acbedcc24ad57567f3dff4ea84..79e4fbd6f6c3facec94c3eb0cb3bbd9241350739 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movssr.ms
+++ b/sim/testsuite/sim/cris/asm/movssr.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: Read of support register is unimplemented\nprogram stopped with signal 5.\n
+# output: Read of support register is unimplemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movucpc.ms b/sim/testsuite/sim/cris/asm/movucpc.ms
index 91fe4de8767f562e749738bbb4d6098f12fbe2a9..aec82d1ade1ccb7d25d7ef5a494fd8f2029648a3 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movucpc.ms
+++ b/sim/testsuite/sim/cris/asm/movucpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movumpc.ms b/sim/testsuite/sim/cris/asm/movumpc.ms
index eecddf2b744c1cd7b2bdebb734346e485f6200c3..9bfc492d3f066066632f1cb293eb03d8b60fb749 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movumpc.ms
+++ b/sim/testsuite/sim/cris/asm/movumpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/movurpc.ms b/sim/testsuite/sim/cris/asm/movurpc.ms
index a90c49282ab8992f55bdc4228e27e67d3b8060fc..3d7511076c63641aa05731df72c6a702fba748b5 100644 (file)
--- a/sim/testsuite/sim/cris/asm/movurpc.ms
+++ b/sim/testsuite/sim/cris/asm/movurpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror: 
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/msteppc1.ms b/sim/testsuite/sim/cris/asm/msteppc1.ms
index 5c78e0b34ac4401860e58d743c1b6f737eac8b23..d21ffd77e1daa015481ac99e45db0c94a4711dfb 100644 (file)
--- a/sim/testsuite/sim/cris/asm/msteppc1.ms
+++ b/sim/testsuite/sim/cris/asm/msteppc1.ms
@@ -1,7 +1,7 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
 # output: General register read of PC is not implemented.\n
-# output: program stopped with signal 5.\n
+# output: program stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/msteppc2.ms b/sim/testsuite/sim/cris/asm/msteppc2.ms
index e78be45c0a53b0bf69bdd0ac8f56c4ccf03ed346..69bfbaf0e71db842b7c3e504946df3b661e1e9c3 100644 (file)
--- a/sim/testsuite/sim/cris/asm/msteppc2.ms
+++ b/sim/testsuite/sim/cris/asm/msteppc2.ms
@@ -1,7 +1,7 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
 # output: General register read of PC is not implemented.\n
-# output: program stopped with signal 5.\n
+# output: program stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/msteppc3.ms b/sim/testsuite/sim/cris/asm/msteppc3.ms
index 9e6d30124b88113dd14fd622c579b21c46e35301..09e87a324943f155486f814f4f5266346d43d6c2 100644 (file)
--- a/sim/testsuite/sim/cris/asm/msteppc3.ms
+++ b/sim/testsuite/sim/cris/asm/msteppc3.ms
@@ -1,7 +1,7 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
 # output: General register read of PC is not implemented.\n
-# output: program stopped with signal 5.\n
+# output: program stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/rfg.ms b/sim/testsuite/sim/cris/asm/rfg.ms
index f5439edd446523260e442cde3dc226632fcdab1b..aa664b28e5b01c198cff602c9bd41a92c7dd5eb2 100644 (file)
--- a/sim/testsuite/sim/cris/asm/rfg.ms
+++ b/sim/testsuite/sim/cris/asm/rfg.ms
@@ -1,6 +1,6 @@
 # mach: crisv32
 # xerror:
-# output: RFG isn't implemented\nprogram stopped with signal 5.\n
+# output: RFG isn't implemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/sbfs.ms b/sim/testsuite/sim/cris/asm/sbfs.ms
index 1138e69249abc4cdf67ecbf222ef14be61e5aba1..5714b5237c624fadec3b94d1d5d7143c5b7881fb 100644 (file)
--- a/sim/testsuite/sim/cris/asm/sbfs.ms
+++ b/sim/testsuite/sim/cris/asm/sbfs.ms
@@ -1,6 +1,6 @@
 # mach: crisv10
 # xerror:
-# output: SBFS isn't implemented\nprogram stopped with signal 5.\n
+# output: SBFS isn't implemented\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start

diff --git a/sim/testsuite/sim/cris/asm/subqpc.ms b/sim/testsuite/sim/cris/asm/subqpc.ms
index dd4d2bfd94fd005c2a7a8cb3a26e0f7e96728354..e2679a3e421e8dc0168c41e59ea6d4a10c9728a5 100644 (file)
--- a/sim/testsuite/sim/cris/asm/subqpc.ms
+++ b/sim/testsuite/sim/cris/asm/subqpc.ms
@@ -1,6 +1,6 @@
 # mach: crisv3 crisv8 crisv10
 # xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
 
  .include "testutils.inc"
  start