+2003-04-02 Chris Demetriou <cgd@broadcom.com>
+
+ * config/tc-mips.c (macro2): Adjust implementation of
+ M_ULH, M_ULHU, M_ULW, and M_ULD so that they work properly
+ in the case where the source and destination registers
+ are the same.
+
2003-04-01 Bob Wilson <bob.wilson@acm.org>
* Makefile.am (CPU_TYPES): Add xtensa.
ulh:
if (offset_expr.X_add_number >= 0x7fff)
as_bad (_("operand overflow"));
- /* avoid load delay */
if (! target_big_endian)
++offset_expr.X_add_number;
- macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
+ macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
(int) BFD_RELOC_LO16, breg);
if (! target_big_endian)
--offset_expr.X_add_number;
else
++offset_expr.X_add_number;
- macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", AT,
+ macro_build ((char *) NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
(int) BFD_RELOC_LO16, breg);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<",
- treg, treg, 8);
+ AT, AT, 8);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,v,t",
treg, treg, AT);
break;
ulw:
if (offset_expr.X_add_number >= 0x8000 - off)
as_bad (_("operand overflow"));
+ if (treg != breg)
+ tempreg = treg;
+ else
+ tempreg = AT;
if (! target_big_endian)
offset_expr.X_add_number += off;
- macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
+ macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
(int) BFD_RELOC_LO16, breg);
if (! target_big_endian)
offset_expr.X_add_number -= off;
else
offset_expr.X_add_number += off;
- macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
+ macro_build ((char *) NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
(int) BFD_RELOC_LO16, breg);
- return;
+
+ /* If necessary, move the result in tempreg the final destination. */
+ if (treg == tempreg)
+ return;
+ /* Protect second load's delay slot. */
+ if (!gpr_interlocks)
+ macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
+ move_register (&icnt, treg, tempreg);
+ break;
case M_ULD_A:
s = "ldl";
+2003-04-02 Chris Demetriou <cgd@broadcom.com>
+
+ * gas/mips/ulh.d: Adjust for ulh and ulhu macro assembly changes.
+
+ * gas/mips/mips.exp: Define new "gpr_ilocks" architecture
+ property, and add it to mips2 (and later) chips and r3900.
+ * gas/mips/uld2.s: New test source file.
+ * gas/mips/ulh2.s: Likewise.
+ * gas/mips/ulw2.s: Likewise.
+ * gas/mips/uld2.l: New test stderr listing.
+ * gas/mips/ulh2.l: Likewise.
+ * gas/mips/ulw2.l: Likewise.
+ * gas/mips/uld2-eb.d: New test.
+ * gas/mips/uld2-el.d: Likewise.
+ * gas/mips/ulh2-eb.d: Likewise.
+ * gas/mips/ulh2-el.d: Likewise.
+ * gas/mips/ulw2-eb-ilocks.d: Likewise.
+ * gas/mips/ulw2-eb.d: Likewise.
+ * gas/mips/ulw2-el-ilocks.d: Likewise.
+ * gas/mips/ulw2-el.d: Likewise.
+ * gas/mips/mips.exp: Run new tests for appropriate architectures.
+
2003-04-01 Bob Wilson <bob.wilson@acm.org>
* gas/xtensa/all.exp: New file.
# The architecture includes the instructions defined
# by that MIPS ISA.
#
+# gpr_ilocks
+# The architecture interlocks GPRs accesses. (That is,
+# there are no load delay slots.)
+#
# mips3d The architecture includes the MIPS-3D ASE.
#
# ror The architecture includes hardware rotate instructions.
# to any architecture.
mips_arch_create mips1 32 {} {} \
{ -march=mips1 -mtune=mips1 } { -mmips:3000 }
-mips_arch_create mips2 32 mips1 {} \
+mips_arch_create mips2 32 mips1 { gpr_ilocks } \
{ -march=mips2 -mtune=mips2 } { -mmips:6000 }
mips_arch_create mips3 64 mips2 {} \
{ -march=mips3 -mtune=mips3 } { -mmips:4000 }
{ mipsisa64-*-* mipsisa64el-*-* }
mips_arch_create r3000 32 mips1 {} \
{ -march=r3000 -mtune=r3000 } { -mmips:3000 }
-mips_arch_create r3900 32 mips1 {} \
+mips_arch_create r3900 32 mips1 { gpr_ilocks } \
{ -march=r3900 -mtune=r3900 } { -mmips:3900 } \
{ mipstx39-*-* mipstx39el-*-* }
mips_arch_create r4000 64 mips3 {} \
if !$aout { run_dump_test "sb" }
run_dump_test "trunc"
if !$aout { run_dump_test "ulh" }
+ run_dump_test_arches "ulh2-eb" [mips_arch_list_matching mips1]
+ run_dump_test_arches "ulh2-el" [mips_arch_list_matching mips1]
if $elf { run_dump_test "ulh-svr4pic" }
if $elf { run_dump_test "ulh-xgot" }
if $ecoff { run_dump_test "ulh-empic" }
run_dump_test "usw"
run_dump_test "usd"
}
+ run_dump_test_arches "ulw2-eb" [mips_arch_list_matching !gpr_ilocks]
+ run_dump_test_arches "ulw2-eb-ilocks" [mips_arch_list_matching gpr_ilocks]
+ run_dump_test_arches "ulw2-el" [mips_arch_list_matching !gpr_ilocks]
+ run_dump_test_arches "ulw2-el-ilocks" [mips_arch_list_matching gpr_ilocks]
+
+ run_dump_test_arches "uld2-eb" [mips_arch_list_matching mips3]
+ run_dump_test_arches "uld2-el" [mips_arch_list_matching mips3]
+
# The mips16 test can only be run on ELF, because only ELF
# supports the necessary mips16 reloc.
if { $elf && !$no_mips16 } {
--- /dev/null
+#as: -EB
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: uld2 -EB
+#source: uld2.s
+#stderr: uld2.l
+
+# Further checks of uld macro.
+# XXX: note: when 'move' is changed to use 'or' rather than daddu, the
+# XXX: 'move' opcodes shown here (whose raw instruction fields are daddu)
+# XXX: should be changed to be 'or' instructions and this comment should be
+# XXX: removed.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 68a40000 ldl \$4,0\(\$5\)
+0+0004 <[^>]*> 6ca40007 ldr \$4,7\(\$5\)
+0+0008 <[^>]*> 68a40001 ldl \$4,1\(\$5\)
+0+000c <[^>]*> 6ca40008 ldr \$4,8\(\$5\)
+0+0010 <[^>]*> 68a10000 ldl \$1,0\(\$5\)
+0+0014 <[^>]*> 6ca10007 ldr \$1,7\(\$5\)
+0+0018 <[^>]*> 0020282d move \$5,\$1
+0+001c <[^>]*> 68a10001 ldl \$1,1\(\$5\)
+0+0020 <[^>]*> 6ca10008 ldr \$1,8\(\$5\)
+0+0024 <[^>]*> 0020282d move \$5,\$1
+ \.\.\.
--- /dev/null
+#as: -EL
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: uld2 -EL
+#source: uld2.s
+#stderr: uld2.l
+
+# Further checks of uld macro.
+# XXX: note: when 'move' is changed to use 'or' rather than daddu, the
+# XXX: 'move' opcodes shown here (whose raw instruction fields are daddu)
+# XXX: should be changed to be 'or' instructions and this comment should be
+# XXX: removed.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 68a40007 ldl \$4,7\(\$5\)
+0+0004 <[^>]*> 6ca40000 ldr \$4,0\(\$5\)
+0+0008 <[^>]*> 68a40008 ldl \$4,8\(\$5\)
+0+000c <[^>]*> 6ca40001 ldr \$4,1\(\$5\)
+0+0010 <[^>]*> 68a10007 ldl \$1,7\(\$5\)
+0+0014 <[^>]*> 6ca10000 ldr \$1,0\(\$5\)
+0+0018 <[^>]*> 0020282d move \$5,\$1
+0+001c <[^>]*> 68a10008 ldl \$1,8\(\$5\)
+0+0020 <[^>]*> 6ca10001 ldr \$1,1\(\$5\)
+0+0024 <[^>]*> 0020282d move \$5,\$1
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:11: Warning: Macro used \$at after "\.set noat"
+.*:12: Warning: Macro used \$at after "\.set noat"
--- /dev/null
+# Source file used to test the uld macro (harder).
+
+ .set noat
+
+ .text
+text_label:
+
+ uld $4,0($5)
+ uld $4,1($5)
+
+ uld $5,0($5) # warns
+ uld $5,1($5) # warns
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
.*: +file format .*mips.*
Disassembly of section .text:
-0+0000 <[^>]*> lb a0,[01]\(zero\)
-0+0004 <[^>]*> lbu at,[01]\(zero\)
-0+0008 <[^>]*> sll a0,a0,0x8
+0+0000 <[^>]*> lb at,[01]\(zero\)
+0+0004 <[^>]*> lbu a0,[01]\(zero\)
+0+0008 <[^>]*> sll at,at,0x8
0+000c <[^>]*> or a0,a0,at
-0+0010 <[^>]*> lb a0,[12]\(zero\)
-0+0014 <[^>]*> lbu at,[12]\(zero\)
-0+0018 <[^>]*> sll a0,a0,0x8
+0+0010 <[^>]*> lb at,[12]\(zero\)
+0+0014 <[^>]*> lbu a0,[12]\(zero\)
+0+0018 <[^>]*> sll at,at,0x8
0+001c <[^>]*> or a0,a0,at
0+0020 <[^>]*> li at,0x8000
0+0024 <[^>]*> lb a0,[01]\(at\)
0+0028 <[^>]*> lbu at,[01]\(at\)
0+002c <[^>]*> sll a0,a0,0x8
0+0030 <[^>]*> or a0,a0,at
-0+0034 <[^>]*> lb a0,-3276[78]\(zero\)
-0+0038 <[^>]*> lbu at,-3276[78]\(zero\)
-0+003c <[^>]*> sll a0,a0,0x8
+0+0034 <[^>]*> lb at,-3276[78]\(zero\)
+0+0038 <[^>]*> lbu a0,-3276[78]\(zero\)
+0+003c <[^>]*> sll at,at,0x8
0+0040 <[^>]*> or a0,a0,at
0+0044 <[^>]*> lui at,0x1
0+0048 <[^>]*> lb a0,[01]\(at\)
0+0064 <[^>]*> lbu at,[01]\(at\)
0+0068 <[^>]*> sll a0,a0,0x8
0+006c <[^>]*> or a0,a0,at
-0+0070 <[^>]*> lb a0,[01]\(a1\)
-0+0074 <[^>]*> lbu at,[01]\(a1\)
-0+0078 <[^>]*> sll a0,a0,0x8
+0+0070 <[^>]*> lb at,[01]\(a1\)
+0+0074 <[^>]*> lbu a0,[01]\(a1\)
+0+0078 <[^>]*> sll at,at,0x8
0+007c <[^>]*> or a0,a0,at
-0+0080 <[^>]*> lb a0,[12]\(a1\)
-0+0084 <[^>]*> lbu at,[12]\(a1\)
-0+0088 <[^>]*> sll a0,a0,0x8
+0+0080 <[^>]*> lb at,[12]\(a1\)
+0+0084 <[^>]*> lbu a0,[12]\(a1\)
+0+0088 <[^>]*> sll at,at,0x8
0+008c <[^>]*> or a0,a0,at
0+0090 <[^>]*> lui at,[-0-9x]+
[ ]*90: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
0+045c <[^>]*> lbu at,[01]\(at\)
0+0460 <[^>]*> sll a0,a0,0x8
0+0464 <[^>]*> or a0,a0,at
-0+0468 <[^>]*> lbu a0,[01]\(zero\)
-0+046c <[^>]*> lbu at,[01]\(zero\)
-0+0470 <[^>]*> sll a0,a0,0x8
+0+0468 <[^>]*> lbu at,[01]\(zero\)
+0+046c <[^>]*> lbu a0,[01]\(zero\)
+0+0470 <[^>]*> sll at,at,0x8
0+0474 <[^>]*> or a0,a0,at
...
--- /dev/null
+#as: -EB
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulh2 -EB
+#source: ulh2.s
+#stderr: ulh2.l
+
+# Further checks of ulh/ulhu macros.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 80a10000 lb \$1,0\(\$5\)
+0+0004 <[^>]*> 90a40001 lbu \$4,1\(\$5\)
+0+0008 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+000c <[^>]*> 00812025 or \$4,\$4,\$1
+0+0010 <[^>]*> 80a10001 lb \$1,1\(\$5\)
+0+0014 <[^>]*> 90a40002 lbu \$4,2\(\$5\)
+0+0018 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+001c <[^>]*> 00812025 or \$4,\$4,\$1
+0+0020 <[^>]*> 80a10000 lb \$1,0\(\$5\)
+0+0024 <[^>]*> 90a50001 lbu \$5,1\(\$5\)
+0+0028 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+002c <[^>]*> 00a12825 or \$5,\$5,\$1
+0+0030 <[^>]*> 80a10001 lb \$1,1\(\$5\)
+0+0034 <[^>]*> 90a50002 lbu \$5,2\(\$5\)
+0+0038 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+003c <[^>]*> 00a12825 or \$5,\$5,\$1
+0+0040 <[^>]*> 90a10000 lbu \$1,0\(\$5\)
+0+0044 <[^>]*> 90a40001 lbu \$4,1\(\$5\)
+0+0048 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+004c <[^>]*> 00812025 or \$4,\$4,\$1
+0+0050 <[^>]*> 90a10001 lbu \$1,1\(\$5\)
+0+0054 <[^>]*> 90a40002 lbu \$4,2\(\$5\)
+0+0058 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+005c <[^>]*> 00812025 or \$4,\$4,\$1
+0+0060 <[^>]*> 90a10000 lbu \$1,0\(\$5\)
+0+0064 <[^>]*> 90a50001 lbu \$5,1\(\$5\)
+0+0068 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+006c <[^>]*> 00a12825 or \$5,\$5,\$1
+0+0070 <[^>]*> 90a10001 lbu \$1,1\(\$5\)
+0+0074 <[^>]*> 90a50002 lbu \$5,2\(\$5\)
+0+0078 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+007c <[^>]*> 00a12825 or \$5,\$5,\$1
+ \.\.\.
--- /dev/null
+#as: -EL
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulh2 -EL
+#source: ulh2.s
+#stderr: ulh2.l
+
+# Further checks of ulh/ulhu macros.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 80a10001 lb \$1,1\(\$5\)
+0+0004 <[^>]*> 90a40000 lbu \$4,0\(\$5\)
+0+0008 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+000c <[^>]*> 00812025 or \$4,\$4,\$1
+0+0010 <[^>]*> 80a10002 lb \$1,2\(\$5\)
+0+0014 <[^>]*> 90a40001 lbu \$4,1\(\$5\)
+0+0018 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+001c <[^>]*> 00812025 or \$4,\$4,\$1
+0+0020 <[^>]*> 80a10001 lb \$1,1\(\$5\)
+0+0024 <[^>]*> 90a50000 lbu \$5,0\(\$5\)
+0+0028 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+002c <[^>]*> 00a12825 or \$5,\$5,\$1
+0+0030 <[^>]*> 80a10002 lb \$1,2\(\$5\)
+0+0034 <[^>]*> 90a50001 lbu \$5,1\(\$5\)
+0+0038 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+003c <[^>]*> 00a12825 or \$5,\$5,\$1
+0+0040 <[^>]*> 90a10001 lbu \$1,1\(\$5\)
+0+0044 <[^>]*> 90a40000 lbu \$4,0\(\$5\)
+0+0048 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+004c <[^>]*> 00812025 or \$4,\$4,\$1
+0+0050 <[^>]*> 90a10002 lbu \$1,2\(\$5\)
+0+0054 <[^>]*> 90a40001 lbu \$4,1\(\$5\)
+0+0058 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+005c <[^>]*> 00812025 or \$4,\$4,\$1
+0+0060 <[^>]*> 90a10001 lbu \$1,1\(\$5\)
+0+0064 <[^>]*> 90a50000 lbu \$5,0\(\$5\)
+0+0068 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+006c <[^>]*> 00a12825 or \$5,\$5,\$1
+0+0070 <[^>]*> 90a10002 lbu \$1,2\(\$5\)
+0+0074 <[^>]*> 90a50001 lbu \$5,1\(\$5\)
+0+0078 <[^>]*> 00010a00 sll \$1,\$1,0x8
+0+007c <[^>]*> 00a12825 or \$5,\$5,\$1
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:8: Warning: Macro used \$at after "\.set noat"
+.*:9: Warning: Macro used \$at after "\.set noat"
+.*:11: Warning: Macro used \$at after "\.set noat"
+.*:12: Warning: Macro used \$at after "\.set noat"
+.*:14: Warning: Macro used \$at after "\.set noat"
+.*:15: Warning: Macro used \$at after "\.set noat"
+.*:17: Warning: Macro used \$at after "\.set noat"
+.*:18: Warning: Macro used \$at after "\.set noat"
--- /dev/null
+# Source file used to test the ulh and ulhu macros (harder).
+
+ .set noat
+
+ .text
+text_label:
+
+ ulh $4,0($5) # warns
+ ulh $4,1($5) # warns
+
+ ulh $5,0($5) # warns
+ ulh $5,1($5) # warns
+
+ ulhu $4,0($5) # warns
+ ulhu $4,1($5) # warns
+
+ ulhu $5,0($5) # warns
+ ulhu $5,1($5) # warns
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
--- /dev/null
+#as: -EB
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulw2 -EB interlocked
+#source: ulw2.s
+#stderr: ulw2.l
+
+# Further checks of ulw macro.
+# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
+# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
+# XXX: should be changed to be 'or' instructions and this comment should be
+# XXX: removed.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 88a40000 lwl \$4,0\(\$5\)
+0+0004 <[^>]*> 98a40003 lwr \$4,3\(\$5\)
+0+0008 <[^>]*> 88a40001 lwl \$4,1\(\$5\)
+0+000c <[^>]*> 98a40004 lwr \$4,4\(\$5\)
+0+0010 <[^>]*> 88a10000 lwl \$1,0\(\$5\)
+0+0014 <[^>]*> 98a10003 lwr \$1,3\(\$5\)
+0+0018 <[^>]*> 0020282[1d] move \$5,\$1
+0+001c <[^>]*> 88a10001 lwl \$1,1\(\$5\)
+0+0020 <[^>]*> 98a10004 lwr \$1,4\(\$5\)
+0+0024 <[^>]*> 0020282[1d] move \$5,\$1
+ \.\.\.
--- /dev/null
+#as: -EB
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulw2 -EB non-interlocked
+#source: ulw2.s
+#stderr: ulw2.l
+
+# Further checks of ulw macro.
+# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
+# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
+# XXX: should be changed to be 'or' instructions and this comment should be
+# XXX: removed.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 88a40000 lwl \$4,0\(\$5\)
+0+0004 <[^>]*> 98a40003 lwr \$4,3\(\$5\)
+0+0008 <[^>]*> 88a40001 lwl \$4,1\(\$5\)
+0+000c <[^>]*> 98a40004 lwr \$4,4\(\$5\)
+0+0010 <[^>]*> 88a10000 lwl \$1,0\(\$5\)
+0+0014 <[^>]*> 98a10003 lwr \$1,3\(\$5\)
+0+0018 <[^>]*> 00000000 nop
+0+001c <[^>]*> 0020282[1d] move \$5,\$1
+0+0020 <[^>]*> 88a10001 lwl \$1,1\(\$5\)
+0+0024 <[^>]*> 98a10004 lwr \$1,4\(\$5\)
+0+0028 <[^>]*> 00000000 nop
+0+002c <[^>]*> 0020282[1d] move \$5,\$1
+ \.\.\.
--- /dev/null
+#as: -EL
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulw2 -EL interlocked
+#source: ulw2.s
+#stderr: ulw2.l
+
+# Further checks of ulw macro.
+# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
+# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
+# XXX: should be changed to be 'or' instructions and this comment should be
+# XXX: removed.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 88a40003 lwl \$4,3\(\$5\)
+0+0004 <[^>]*> 98a40000 lwr \$4,0\(\$5\)
+0+0008 <[^>]*> 88a40004 lwl \$4,4\(\$5\)
+0+000c <[^>]*> 98a40001 lwr \$4,1\(\$5\)
+0+0010 <[^>]*> 88a10003 lwl \$1,3\(\$5\)
+0+0014 <[^>]*> 98a10000 lwr \$1,0\(\$5\)
+0+0018 <[^>]*> 0020282[1d] move \$5,\$1
+0+001c <[^>]*> 88a10004 lwl \$1,4\(\$5\)
+0+0020 <[^>]*> 98a10001 lwr \$1,1\(\$5\)
+0+0024 <[^>]*> 0020282[1d] move \$5,\$1
+ \.\.\.
--- /dev/null
+#as: -EL
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: ulw2 -EL non-interlocked
+#source: ulw2.s
+#stderr: ulw2.l
+
+# Further checks of ulw macro.
+# XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
+# XXX: 'move' opcodes shown here (whose raw instruction fields are addu/daddu)
+# XXX: should be changed to be 'or' instructions and this comment should be
+# XXX: removed.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 88a40003 lwl \$4,3\(\$5\)
+0+0004 <[^>]*> 98a40000 lwr \$4,0\(\$5\)
+0+0008 <[^>]*> 88a40004 lwl \$4,4\(\$5\)
+0+000c <[^>]*> 98a40001 lwr \$4,1\(\$5\)
+0+0010 <[^>]*> 88a10003 lwl \$1,3\(\$5\)
+0+0014 <[^>]*> 98a10000 lwr \$1,0\(\$5\)
+0+0018 <[^>]*> 00000000 nop
+0+001c <[^>]*> 0020282[1d] move \$5,\$1
+0+0020 <[^>]*> 88a10004 lwl \$1,4\(\$5\)
+0+0024 <[^>]*> 98a10001 lwr \$1,1\(\$5\)
+0+0028 <[^>]*> 00000000 nop
+0+002c <[^>]*> 0020282[1d] move \$5,\$1
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:11: Warning: Macro used \$at after "\.set noat"
+.*:12: Warning: Macro used \$at after "\.set noat"
--- /dev/null
+# Source file used to test the ulw macro (harder).
+
+ .set noat
+
+ .text
+text_label:
+
+ ulw $4,0($5)
+ ulw $4,1($5)
+
+ ulw $5,0($5) # warns
+ ulw $5,1($5) # warns
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
projects / binutils-gdb.git / commitdiff