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i965/vec4: Fix off-by-one register class overallocation.
authorFrancisco Jerez <currojerez@riseup.net>
Sat, 23 Nov 2013 03:21:13 +0000 (19:21 -0800)
committerFrancisco Jerez <currojerez@riseup.net>
Wed, 19 Feb 2014 15:27:25 +0000 (16:27 +0100)
Reviewed-by: Paul Berry <stereotype441@gmail.com>
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp patch | blob | history

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 4ecc4a288e2aaa0a88ecc78deda37f5341a796b0..e7aab9d039365c70a9edb6764b007647ff823e81 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -121,7 +121,7 @@ brw_vec4_alloc_reg_set(struct brw_context *brw)
    if (brw->gen >= 6)
       ra_set_allocate_round_robin(brw->vec4.regs);
    ralloc_free(brw->vec4.classes);
-   brw->vec4.classes = ralloc_array(brw, int, class_count + 1);
+   brw->vec4.classes = ralloc_array(brw, int, class_count);
 
    /* Now, add the registers to their classes, and add the conflicts
     * between them and the base GRF registers (and also each other).