x86, regressions: updates stats
authorNilay Vaish <nilay@cs.wisc.edu>
Tue, 21 May 2013 16:41:27 +0000 (11:41 -0500)
committerNilay Vaish <nilay@cs.wisc.edu>
Tue, 21 May 2013 16:41:27 +0000 (11:41 -0500)
This is due to op class, function call, walker patches.

23 files changed:
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt

index 77940f18e2cfed1008709ee570f60e18350831f4..8f4e7d03cc6a72b71e134d21569398aa65c13542 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.132953                       # Number of seconds simulated
-sim_ticks                                5132953103000                       # Number of ticks simulated
-final_tick                               5132953103000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.140938                       # Number of seconds simulated
+sim_ticks                                5140937585000                       # Number of ticks simulated
+final_tick                               5140937585000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 118788                       # Simulator instruction rate (inst/s)
-host_op_rate                                   234812                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1494512187                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 768808                       # Number of bytes of host memory used
-host_seconds                                  3434.53                       # Real time elapsed on the host
-sim_insts                                   407981680                       # Number of instructions simulated
-sim_ops                                     806469686                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide      2427072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1080064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10859584                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             14370176                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1080064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1080064                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9570112                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9570112                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        37923                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           49                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16876                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             169681                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                224534                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          149533                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               149533                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       472841                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               210418                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2115660                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2799592                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          210418                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             210418                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1864446                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1864446                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1864446                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       472841                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           611                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              210418                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2115660                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4664038                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        224534                       # Total number of read requests seen
-system.physmem.writeReqs                       149533                       # Total number of write requests seen
-system.physmem.cpureqs                         378540                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                     14370176                       # Total number of bytes read from memory
-system.physmem.bytesWritten                   9570112                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd               14370176                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                9570112                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                      118                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite               4466                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                 14182                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                 13235                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                 13224                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                 16247                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                 13672                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                 13108                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                 13087                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                 16327                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                 13931                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                 13220                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                13507                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                15686                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                13366                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                12693                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                13279                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                15652                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                  9160                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                  8678                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                  8635                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                 11642                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                  8788                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                  8537                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                  8431                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                 11660                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                  9003                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                  8633                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                 8850                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                11092                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                 8524                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                 8172                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                 8641                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                11087                       # Track writes on a per bank basis
+host_inst_rate                                 121697                       # Simulator instruction rate (inst/s)
+host_op_rate                                   240559                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1534230705                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 773616                       # Number of bytes of host memory used
+host_seconds                                  3350.82                       # Real time elapsed on the host
+sim_insts                                   407786881                       # Number of instructions simulated
+sim_ops                                     806071515                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide      2479872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1026240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10765120                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             14275328                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1026240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1026240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9536256                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9536256                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38748                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           58                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16035                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             168205                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                223052                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          149004                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               149004                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       482377                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            722                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             75                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               199621                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2093999                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2776795                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          199621                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             199621                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1854964                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1854964                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1854964                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       482377                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            75                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              199621                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2093999                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4631759                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        223052                       # Total number of read requests seen
+system.physmem.writeReqs                       149004                       # Total number of write requests seen
+system.physmem.cpureqs                         373790                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                     14275328                       # Total number of bytes read from memory
+system.physmem.bytesWritten                   9536256                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd               14275328                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                9536256                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                       71                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite               1726                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                 13636                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                 12914                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                 13124                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                 16345                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                 13470                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                 13111                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                 13382                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                 16266                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                 13519                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                 13235                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                13394                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11                15885                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12                13088                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13                12601                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                13202                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                15809                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                  8837                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                  8387                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                  8583                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                 11810                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                  8818                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                  8522                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                  8723                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                 11661                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                  8790                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                  8601                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                 8761                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                11230                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                 8431                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                 8093                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                 8583                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                11174                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                    5132953050000                       # Total gap between requests
+system.physmem.numWrRetry                           8                       # Number of times wr buffer was full causing retry
+system.physmem.totGap                    5140937531500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                  224534                       # Categorize read packet sizes
+system.physmem.readPktSize::6                  223052                       # Categorize read packet sizes
 system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                 149533                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                    174096                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     19313                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      7127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      3462                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2988                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2367                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1869                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1810                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1754                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1686                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1155                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1047                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      960                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      876                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      799                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      788                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      827                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      370                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      214                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 149004                       # Categorize write packet sizes
+system.physmem.rdQLenPdf::0                    172997                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     18175                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      7573                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      3487                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      3011                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      2422                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      1913                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1861                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1763                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1672                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1114                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1019                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      962                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      902                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      823                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      817                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      907                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      865                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      412                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      253                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -136,92 +136,92 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      5394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5748                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      6326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      6402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      6441                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      6484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      6492                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      6494                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      6494                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      6502                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     1108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                      754                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                      100                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                      5326                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      5675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      6279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      6374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                      6421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      6454                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      6466                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      6470                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      6471                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                      6479                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     1153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                      804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                      200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        8                       # What write queue length does an incoming req see
-system.physmem.totQLat                     4726159249                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                9244557999                       # Sum of mem lat for all requests
-system.physmem.totBusLat                   1122080000                       # Total cycles spent in databus access
-system.physmem.totBankLat                  3396318750                       # Total cycles spent in bank access
-system.physmem.avgQLat                       21059.81                       # Average queueing delay per request
-system.physmem.avgBankLat                    15134.03                       # Average bank access latency per request
+system.physmem.totQLat                     4794975750                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat                9301923250                       # Sum of mem lat for all requests
+system.physmem.totBusLat                   1114905000                       # Total cycles spent in databus access
+system.physmem.totBankLat                  3392042500                       # Total cycles spent in bank access
+system.physmem.avgQLat                       21503.97                       # Average queueing delay per request
+system.physmem.avgBankLat                    15212.25                       # Average bank access latency per request
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  41193.85                       # Average memory access latency
-system.physmem.avgRdBW                           2.80                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                           1.86                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   2.80                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                   1.86                       # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat                  41716.21                       # Average memory access latency
+system.physmem.avgRdBW                           2.78                       # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW                   2.78                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW                   1.85                       # Average consumed write bandwidth in MB/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
-system.physmem.avgWrQLen                        11.69                       # Average write queue length over time
-system.physmem.readRowHits                     193610                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    105925                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   86.27                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  70.84                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13722015.17                       # Average gap between requests
-system.iocache.replacements                     47570                       # number of replacements
-system.iocache.tagsinuse                     0.103974                       # Cycle average of tags in use
+system.physmem.avgWrQLen                        15.58                       # Average write queue length over time
+system.physmem.readRowHits                     191257                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    105612                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   85.77                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  70.88                       # Row buffer hit rate for writes
+system.physmem.avgGap                     13817644.47                       # Average gap between requests
+system.iocache.replacements                     47576                       # number of replacements
+system.iocache.tagsinuse                     0.128763                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47586                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47592                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4991995541000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.103974                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.006498                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.006498                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide          905                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              905                       # number of ReadReq misses
+system.iocache.warmup_cycle              4991974997000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide     0.128763                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.008048                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.008048                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          911                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              911                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47625                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47625                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47625                       # number of overall misses
-system.iocache.overall_misses::total            47625                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    145555660                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    145555660                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10008674105                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  10008674105                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide  10154229765                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  10154229765                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide  10154229765                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  10154229765                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          905                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            905                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47631                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47631                       # number of overall misses
+system.iocache.overall_misses::total            47631                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    147497397                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    147497397                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  10072244306                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  10072244306                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide  10219741703                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  10219741703                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide  10219741703                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  10219741703                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          911                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            911                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47625                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47625                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47625                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47625                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47631                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47631                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47631                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47631                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -230,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160834.983425                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 160834.983425                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214226.757384                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 214226.757384                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213212.173543                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 213212.173543                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213212.173543                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 213212.173543                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        133059                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 161907.131723                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 215587.420933                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 214560.721022                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 214560.721022                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        139153                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                12235                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                12645                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.875276                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    11.004587                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          905                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          905                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          911                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          911                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47625                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47625                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47625                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47625                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     98473941                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     98473941                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7577901783                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   7577901783                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7676375724                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   7676375724                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7676375724                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   7676375724                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47631                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47631                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47631                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    100104427                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    100104427                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   7641446543                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   7641446543                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   7741550970                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   7741550970                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   7741550970                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   7741550970                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -272,18 +272,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108810.984530                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 108810.984530                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162198.240218                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 162198.240218                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 161183.742236                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161183.742236                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 161183.742236                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 162531.774895                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 162531.774895                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -293,410 +293,410 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                86237029                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          86237029                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1109949                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             81299216                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                79239397                       # Number of BTB hits
+system.cpu.branchPred.lookups                85620726                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          85620726                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            882198                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             79268619                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                77534559                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.466373                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
-system.cpu.numCycles                        448469531                       # number of cpu cycles simulated
+system.cpu.branchPred.BTBHitPct             97.812426                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1442315                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             180251                       # Number of incorrect RAS predictions.
+system.cpu.numCycles                        447791761                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27529474                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      426122909                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    86237029                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           79239397                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     163627324                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4728707                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     117219                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               63156445                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                36498                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         53889                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          420                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9038392                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                487130                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    2791                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          258101520                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.259173                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.417982                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           25559948                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      422856490                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85620726                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           78976874                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     162677741                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4000997                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                      98298                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               65919320                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                43594                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         86507                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          459                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8492083                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                383635                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    2345                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          257461374                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.243647                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.415529                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 94901402     36.77%     36.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1566001      0.61%     37.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 71924847     27.87%     65.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   935145      0.36%     65.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1600289      0.62%     66.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2428838      0.94%     67.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1075499      0.42%     67.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1377865      0.53%     68.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 82291634     31.88%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 95198026     36.98%     36.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1534816      0.60%     37.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 71825104     27.90%     65.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   895357      0.35%     65.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1570607      0.61%     66.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2391332      0.93%     67.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1020158      0.40%     67.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1325162      0.51%     68.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81700812     31.73%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            258101520                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.192292                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.950171                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 31223769                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              60616281                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 159439032                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3242187                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3580251                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              838065302                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   921                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3580251                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 33968457                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                37481730                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       11034324                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 159610574                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              12426184                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              834407058                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 18980                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                5821881                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4760224                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents             8257                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           995986207                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1811362671                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1811361735                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               936                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             964469787                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 31516413                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             458013                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         465231                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  28772388                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             17093245                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10135018                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1252851                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1005934                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  828306143                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1250828                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 823325440                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            150511                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        22168488                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     33636711                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         196648                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     258101520                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         3.189929                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.384557                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            257461374                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.191207                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.944315                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 29461192                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              63064302                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 158550724                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3309649                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3075507                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              832761340                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   863                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3075507                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 32153278                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38465118                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       12079112                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 158824437                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              12863922                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              829829025                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 19879                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                6055166                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4924546                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            11525                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           991492877                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1800847756                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1800847292                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               464                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             963999366                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 27493506                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             456551                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         462682                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  29304477                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             16752339                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             9837983                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1099709                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           928773                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  825036488                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1186686                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 821069910                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            146070                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        19309743                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     29357166                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         131932                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     257461374                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         3.189099                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.383585                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            71580535     27.73%     27.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            15499802      6.01%     33.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10327986      4.00%     37.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7455254      2.89%     40.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            75927506     29.42%     70.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3856019      1.49%     71.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72517162     28.10%     99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              787235      0.31%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              150021      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            71259249     27.68%     27.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            15575755      6.05%     33.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10479111      4.07%     37.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7383615      2.87%     40.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            75752504     29.42%     70.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3772068      1.47%     71.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72307575     28.08%     99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              782694      0.30%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              148803      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       258101520                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       257461374                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  366750     34.22%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     34.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 553108     51.61%     85.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                151931     14.18%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  356313     33.63%     33.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    241      0.02%     33.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                    2452      0.23%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 547502     51.68%     85.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                152922     14.43%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            309801      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             795758940     96.65%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             17866354      2.17%     98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9390345      1.14%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            308526      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             793557907     96.65%     96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150412      0.02%     96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                124298      0.02%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             17694567      2.16%     98.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9234200      1.12%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              823325440                       # Type of FU issued
-system.cpu.iq.rate                           1.835856                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1071789                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001302                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1906104602                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         851735215                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    818848735                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 378                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                450                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           94                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              824087257                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     171                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1645357                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              821069910                       # Type of FU issued
+system.cpu.iq.rate                           1.833598                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1059430                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001290                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1900915279                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         845543458                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    817157785                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 194                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                212                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           52                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              821820724                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      90                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1686147                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3104742                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        23669                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11440                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1716567                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2748440                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        17101                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11930                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1411969                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      1932461                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         11842                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1931504                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         11624                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3580251                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                26245227                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2113533                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           829556971                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            304073                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              17093245                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10135018                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             718533                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1617499                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 11192                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11440                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         653820                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       594083                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1247903                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             821445654                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17451760                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1879785                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3075507                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                26873503                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2150322                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           826223174                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            241070                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              16752339                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              9837983                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             692103                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1621529                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12267                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11930                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         498132                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       506603                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1004735                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             819660888                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17391685                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1409021                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     26608752                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83225006                       # Number of branches executed
-system.cpu.iew.exec_stores                    9156992                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.831664                       # Inst execution rate
-system.cpu.iew.wb_sent                      820984205                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     818848829                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 639993786                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1045886534                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     26440023                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83107253                       # Number of branches executed
+system.cpu.iew.exec_stores                    9048338                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.830451                       # Inst execution rate
+system.cpu.iew.wb_sent                      819258374                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     817157837                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 638799704                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1044337102                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.825874                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.611915                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.824861                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.611680                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        22977930                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1054178                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1115022                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    254521269                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     3.168575                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.855004                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        20042352                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1054753                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            891546                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    254385866                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     3.168696                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.858566                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     82765060     32.52%     32.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11818595      4.64%     37.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3860584      1.52%     38.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74956276     29.45%     68.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2441275      0.96%     69.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1480165      0.58%     69.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       888603      0.35%     70.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70922136     27.86%     97.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5388575      2.12%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     82972146     32.62%     32.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11724447      4.61%     37.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3813249      1.50%     38.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74747378     29.38%     68.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2384925      0.94%     69.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1476326      0.58%     69.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       865615      0.34%     69.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     70850824     27.85%     97.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5550956      2.18%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    254521269                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407981680                       # Number of instructions committed
-system.cpu.commit.committedOps              806469686                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    254385866                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407786881                       # Number of instructions committed
+system.cpu.commit.committedOps              806071515                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22406951                       # Number of memory references committed
-system.cpu.commit.loads                      13988500                       # Number of loads committed
-system.cpu.commit.membars                      474453                       # Number of memory barriers committed
-system.cpu.commit.branches                   82201236                       # Number of branches committed
+system.cpu.commit.refs                       22429911                       # Number of memory references committed
+system.cpu.commit.loads                      14003897                       # Number of loads committed
+system.cpu.commit.membars                      474463                       # Number of memory barriers committed
+system.cpu.commit.branches                   82163817                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 735408262                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5388575                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                 735061477                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1156045                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               5550956                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1078502153                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1662494402                       # The number of ROB writes
-system.cpu.timesIdled                         1221401                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       190368011                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9817434094                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407981680                       # Number of Instructions Simulated
-system.cpu.committedOps                     806469686                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             407981680                       # Number of Instructions Simulated
-system.cpu.cpi                               1.099239                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.099239                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.909720                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.909720                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1507130605                       # number of integer regfile reads
-system.cpu.int_regfile_writes               977067823                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        94                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               264732336                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 402254                       # number of misc regfile writes
-system.cpu.icache.replacements                1049385                       # number of replacements
-system.cpu.icache.tagsinuse                509.447090                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  7923264                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1049897                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   7.546706                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            56158934000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     509.447090                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.995014                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.995014                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst      7923264                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7923264                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7923264                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7923264                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7923264                       # number of overall hits
-system.cpu.icache.overall_hits::total         7923264                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1115125                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1115125                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1115125                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1115125                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1115125                       # number of overall misses
-system.cpu.icache.overall_misses::total       1115125                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  15322207492                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  15322207492                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  15322207492                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  15322207492                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  15322207492                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  15322207492                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9038389                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9038389                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9038389                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9038389                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9038389                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9038389                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.123377                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.123377                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.123377                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.123377                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.123377                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.123377                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13740.349729                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13740.349729                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13740.349729                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13740.349729                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13740.349729                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13740.349729                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        10877                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                   1074870508                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1655318425                       # The number of ROB writes
+system.cpu.timesIdled                         1256763                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       190330387                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9834088814                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407786881                       # Number of Instructions Simulated
+system.cpu.committedOps                     806071515                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             407786881                       # Number of Instructions Simulated
+system.cpu.cpi                               1.098102                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.098102                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.910662                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.910662                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1504614065                       # number of integer regfile reads
+system.cpu.int_regfile_writes               975429838                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        52                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               264130300                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 403010                       # number of misc regfile writes
+system.cpu.icache.replacements                 955437                       # number of replacements
+system.cpu.icache.tagsinuse                509.903328                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7482159                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 955949                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.826944                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle           146514700000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     509.903328                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.995905                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.995905                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      7482159                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7482159                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7482159                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7482159                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7482159                       # number of overall hits
+system.cpu.icache.overall_hits::total         7482159                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1009922                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1009922                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1009922                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1009922                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1009922                       # number of overall misses
+system.cpu.icache.overall_misses::total       1009922                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13938284992                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13938284992                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13938284992                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13938284992                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13938284992                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13938284992                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8492081                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8492081                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8492081                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8492081                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8492081                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8492081                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.118925                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.118925                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.118925                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.118925                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.118925                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.118925                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.348017                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13801.348017                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.348017                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13801.348017                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.348017                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13801.348017                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         8199                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               301                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               203                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    36.136213                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    40.389163                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        62547                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        62547                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        62547                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        62547                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        62547                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        62547                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1052578                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1052578                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1052578                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1052578                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1052578                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1052578                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12612158993                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12612158993                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12612158993                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12612158993                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12612158993                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12612158993                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116456                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116456                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116456                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.116456                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116456                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.116456                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.160935                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.160935                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.160935                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.160935                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.160935                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.160935                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53908                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        53908                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        53908                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        53908                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        53908                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        53908                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       956014                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       956014                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       956014                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       956014                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       956014                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       956014                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11502740492                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11502740492                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11502740492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11502740492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11502740492                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11502740492                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112577                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112577                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112577                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.112577                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112577                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.112577                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.979126                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.979126                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.979126                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.979126                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.979126                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.979126                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements         8504                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        6.007408                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs          27369                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs         8519                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         3.212701                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5106816403500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.007408                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375463                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total     0.375463                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        27369                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        27369                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements         7960                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        6.326712                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs          20386                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs         7973                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.556879                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5107329698000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.326712                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.395420                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.395420                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        20403                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        20403                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        27371                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        27371                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        27371                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        27371                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9373                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         9373                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9373                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         9373                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9373                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         9373                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    104966500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    104966500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    104966500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    104966500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    104966500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    104966500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        36742                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        36742                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        20405                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        20405                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        20405                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        20405                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         8843                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         8843                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         8843                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         8843                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         8843                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         8843                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     96821500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     96821500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     96821500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     96821500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     96821500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     96821500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        29246                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        29246                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        36744                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        36744                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        36744                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        36744                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.255103                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.255103                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.255089                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.255089                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.255089                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.255089                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11198.815747                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11198.815747                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11198.815747                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11198.815747                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11198.815747                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11198.815747                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        29248                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        29248                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        29248                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        29248                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.302366                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.302366                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.302345                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.302345                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.302345                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.302345                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10948.942667                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10948.942667                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10948.942667                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10948.942667                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10948.942667                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10948.942667                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -705,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1896                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1896                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9373                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9373                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9373                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         9373                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9373                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         9373                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     86220500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     86220500                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     86220500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     86220500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     86220500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     86220500                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.255103                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.255103                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.255089                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.255089                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.255089                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.255089                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9198.815747                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9198.815747                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9198.815747                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9198.815747                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9198.815747                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9198.815747                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         1394                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1394                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         8843                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         8843                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         8843                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         8843                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         8843                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         8843                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     79135500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     79135500                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     79135500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     79135500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     79135500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     79135500                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.302366                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.302366                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.302345                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.302345                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.302345                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.302345                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8948.942667                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8948.942667                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8948.942667                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8948.942667                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8948.942667                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8948.942667                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements       107843                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse       12.947477                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs         134583                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs       107858                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.247779                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5099863447000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.947477                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.809217                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total     0.809217                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       134601                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       134601                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       134601                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       134601                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       134601                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       134601                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       108812                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total       108812                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       108812                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total       108812                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       108812                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total       108812                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1371802000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1371802000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1371802000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total   1371802000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1371802000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total   1371802000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       243413                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       243413                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       243413                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       243413                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       243413                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       243413                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.447026                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.447026                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.447026                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.447026                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.447026                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.447026                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12607.083778                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12607.083778                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12607.083778                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12607.083778                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12607.083778                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12607.083778                       # average overall miss latency
+system.cpu.dtb_walker_cache.replacements        67560                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse       14.837353                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs          92239                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs        67575                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.364987                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5100574572500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    14.837353                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.927335                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.927335                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92240                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        92240                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92240                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        92240                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92240                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        92240                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        68644                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        68644                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        68644                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        68644                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        68644                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        68644                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    852599000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    852599000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    852599000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    852599000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    852599000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    852599000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       160884                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       160884                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       160884                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       160884                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       160884                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       160884                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.426668                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.426668                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.426668                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.426668                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.426668                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.426668                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12420.590292                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12420.590292                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12420.590292                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12420.590292                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12420.590292                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12420.590292                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -785,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        34946                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        34946                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       108812                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       108812                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       108812                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total       108812                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       108812                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total       108812                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1154178000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1154178000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1154178000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1154178000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1154178000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1154178000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.447026                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.447026                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.447026                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.447026                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.447026                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.447026                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10607.083778                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10607.083778                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10607.083778                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10607.083778                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        19876                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        19876                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        68644                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        68644                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        68644                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        68644                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        68644                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        68644                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    715311000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    715311000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    715311000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    715311000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    715311000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    715311000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.426668                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.426668                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.426668                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.426668                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.426668                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.426668                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10420.590292                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10420.590292                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10420.590292                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10420.590292                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1657617                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997737                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 19103102                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1658129                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  11.520878                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               27986000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.997737                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     11006955                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11006955                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8090467                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8090467                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      19097422                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19097422                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19097422                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19097422                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2237002                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2237002                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       318492                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       318492                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2555494                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2555494                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2555494                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2555494                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32016735000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32016735000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9683080495                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9683080495                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  41699815495                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  41699815495                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  41699815495                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  41699815495                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13243957                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13243957                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8408959                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8408959                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21652916                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21652916                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21652916                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21652916                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.168907                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.168907                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037875                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037875                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.118021                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.118021                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118021                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118021                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14312.340803                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14312.340803                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30402.900214                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30402.900214                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16317.712151                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16317.712151                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16317.712151                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16317.712151                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       383482                       # number of cycles access was blocked
+system.cpu.dcache.replacements                1655094                       # number of replacements
+system.cpu.dcache.tagsinuse                511.995445                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 19021390                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1655606                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  11.489080                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               27980000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.995445                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999991                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999991                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     10917270                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10917270                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8101435                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8101435                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      19018705                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19018705                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19018705                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19018705                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2239579                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2239579                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       315092                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       315092                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2554671                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2554671                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2554671                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2554671                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31946998000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31946998000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9622210995                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9622210995                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  41569208995                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  41569208995                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  41569208995                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  41569208995                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13156849                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13156849                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8416527                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8416527                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21573376                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21573376                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21573376                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21573376                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170222                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.170222                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037437                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037437                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.118418                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.118418                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118418                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118418                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14264.733684                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14264.733684                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30537.782600                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30537.782600                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16271.844396                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16271.844396                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16271.844396                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16271.844396                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       387071                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             42249                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             42390                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.076712                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.131187                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1559520                       # number of writebacks
-system.cpu.dcache.writebacks::total           1559520                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       866015                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       866015                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        26449                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        26449                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       892464                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       892464                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       892464                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       892464                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1370987                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1370987                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       292043                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       292043                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1663030                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1663030                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1663030                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1663030                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17418217500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17418217500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8839751495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8839751495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26257968995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26257968995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26257968995                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26257968995                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97350275500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97350275500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2525993500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2525993500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99876269000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  99876269000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103518                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103518                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034730                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034730                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076804                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.076804                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076804                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.076804                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12704.874299                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12704.874299                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30268.664186                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30268.664186                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15789.233505                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15789.233505                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15789.233505                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15789.233505                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1557214                       # number of writebacks
+system.cpu.dcache.writebacks::total           1557214                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       870911                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       870911                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25892                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        25892                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       896803                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       896803                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       896803                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       896803                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1368668                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1368668                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       289200                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       289200                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1657868                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1657868                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1657868                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1657868                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17401159000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17401159000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8794383495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8794383495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26195542495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26195542495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26195542495                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26195542495                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97349101500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97349101500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2522345500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2522345500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99871447000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  99871447000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104027                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104027                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034361                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034361                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076848                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.076848                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076848                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.076848                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12713.937200                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12713.937200                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30409.348185                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30409.348185                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.740768                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.740768                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.740768                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.740768                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -932,141 +932,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                113549                       # number of replacements
-system.cpu.l2cache.tagsinuse             64828.327724                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3928640                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                177472                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 22.136675                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                111963                       # number of replacements
+system.cpu.l2cache.tagsinuse             64818.241357                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3779325                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                176193                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 21.449916                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 50064.846561                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker     9.159250                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.124586                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   3285.119507                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  11469.077820                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.763929                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000140                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.050127                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.175004                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.989202                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       102263                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7285                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      1032873                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1333038                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2475459                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1596362                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1596362                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          310                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          310                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       153914                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       153914                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker       102263                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         7285                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      1032873                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1486952                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2629373                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker       102263                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         7285                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      1032873                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1486952                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2629373                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           49                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        16879                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        36894                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        53827                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         4124                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         4124                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133799                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133799                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           49                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16879                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       170693                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        187626                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           49                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16879                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       170693                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       187626                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4543000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       320500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1178779000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2492461998                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3676104498                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17587000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     17587000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6908700500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   6908700500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4543000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       320500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1178779000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   9401162498                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10584804998                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4543000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       320500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1178779000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   9401162498                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10584804998                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       102312                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7290                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1049752                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1369932                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2529286                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1596362                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1596362                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4434                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         4434                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       287713                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       287713                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker       102312                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         7290                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      1049752                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1657645                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2816999                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker       102312                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         7290                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1049752                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1657645                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2816999                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000479                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000686                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016079                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026931                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021281                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.930086                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.930086                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.465043                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.465043                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000479                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000686                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016079                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.102973                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.066605                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000479                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000686                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016079                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.102973                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.066605                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92714.285714                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        64100                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69837.016411                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67557.380550                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68294.805544                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  4264.548982                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  4264.548982                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51634.918796                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51634.918796                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92714.285714                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        64100                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69837.016411                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55076.438389                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 56414.382857                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92714.285714                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        64100                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69837.016411                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55076.438389                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 56414.382857                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 50535.271880                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker    14.689116                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.441967                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   3088.733265                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  11179.105128                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.771107                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000224                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000007                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.047130                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.170580                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.989048                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        63019                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         6673                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       939861                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1331810                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2341363                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1578484                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1578484                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          313                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          313                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       154035                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       154035                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        63019                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         6673                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       939861                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1485845                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2495398                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        63019                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         6673                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       939861                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1485845                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2495398                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           58                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            6                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        16036                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        36136                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        52236                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1469                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1469                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133013                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133013                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           58                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            6                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        16036                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       169149                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        185249                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           58                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            6                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        16036                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       169149                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       185249                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4739500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       386000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1102660000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2500024999                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   3607810499                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     18004500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     18004500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6917223500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   6917223500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4739500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       386000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1102660000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   9417248499                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10525033999                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4739500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       386000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1102660000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   9417248499                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10525033999                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        63077                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         6679                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       955897                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1367946                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2393599                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1578484                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1578484                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1782                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1782                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       287048                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       287048                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        63077                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         6679                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       955897                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1654994                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2680647                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        63077                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         6679                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       955897                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1654994                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2680647                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000898                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016776                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026416                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.021823                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.824355                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.824355                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.463382                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.463382                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000898                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016776                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.102205                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.069106                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000920                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000898                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016776                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.102205                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.069106                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81715.517241                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64333.333333                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68761.536543                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69183.777922                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69067.510893                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12256.296801                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12256.296801                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.116139                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.116139                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81715.517241                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64333.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68761.536543                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55674.278293                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 56815.604937                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81715.517241                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64333.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68761.536543                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55674.278293                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 56815.604937                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1075,99 +1075,96 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       102866                       # number of writebacks
-system.cpu.l2cache.writebacks::total           102866                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           49                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16876                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36893                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        53823                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4124                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         4124                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133799                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133799                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           49                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16876                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       170692                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       187622                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           49                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16876                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       170692                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       187622                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3930045                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       257504                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    968789302                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2034070067                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3007046918                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     42432097                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     42432097                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5258255507                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5258255507                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3930045                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       257504                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    968789302                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7292325574                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   8265302425                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3930045                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       257504                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    968789302                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7292325574                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   8265302425                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89237875000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89237875000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2360777500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2360777500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91598652500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91598652500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000479                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000686                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016076                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026931                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021280                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.930086                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.930086                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.465043                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.465043                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000479                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000686                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016076                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102973                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.066604                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000479                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000686                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016076                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102973                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.066604                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        80205                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51500.800000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57406.334558                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55134.309137                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55869.180796                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10289.063288                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10289.063288                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39299.662232                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39299.662232                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        80205                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51500.800000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57406.334558                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42722.128594                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44052.949148                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        80205                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51500.800000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57406.334558                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42722.128594                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44052.949148                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       102337                       # number of writebacks
+system.cpu.l2cache.writebacks::total           102337                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           58                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            6                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16035                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        36136                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        52235                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1469                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1469                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133013                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133013                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           58                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            6                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16035                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       169149                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       185248                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           58                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            6                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16035                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       169149                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       185248                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      4016555                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       310006                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    903103756                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2050826327                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2958256644                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15725947                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15725947                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5276958842                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5276958842                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      4016555                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       310006                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    903103756                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7327785169                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8235215486                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      4016555                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       310006                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    903103756                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7327785169                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8235215486                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89236811500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89236811500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2357396500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2357396500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91594208000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91594208000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000920                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000898                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016775                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026416                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021823                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.824355                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.824355                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.463382                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.463382                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000920                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000898                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016775                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.102205                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.069106                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000920                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000898                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016775                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.102205                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.069106                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 51667.666667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56320.783037                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56752.997758                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56633.610491                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10705.205582                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10705.205582                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39672.504507                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39672.504507                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 51667.666667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56320.783037                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43321.480878                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44455.084460                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69250.948276                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 51667.666667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56320.783037                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43321.480878                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44455.084460                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
index e29eb22f798786c5e4db54765d7e18b92853344e..f3136422c137530e06672b45fc303f3f8397545c 100644 (file)
@@ -4,13 +4,13 @@ sim_seconds                                  5.205149                       # Nu
 sim_ticks                                5205148879000                       # Number of ticks simulated
 final_tick                               5205148879000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 134092                       # Simulator instruction rate (inst/s)
-host_op_rate                                   257066                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6543163557                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 131600                       # Simulator instruction rate (inst/s)
+host_op_rate                                   252290                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6421585329                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 872300                       # Number of bytes of host memory used
-host_seconds                                   795.51                       # Real time elapsed on the host
+host_seconds                                   810.57                       # Real time elapsed on the host
 sim_insts                                   106671342                       # Number of instructions simulated
-sim_ops                                     204498755                       # Number of ops (including micro ops) simulated
+sim_ops                                     204498751                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide        35240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker       160344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker        75328                       # Number of bytes read from this memory
@@ -264,10 +264,10 @@ system.cpu0.numCycles                     10410297758                       # nu
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu0.committedInsts                   60288276                       # Number of instructions committed
-system.cpu0.committedOps                    115773081                       # Number of ops (including micro ops) committed
+system.cpu0.committedOps                    115773079                       # Number of ops (including micro ops) committed
 system.cpu0.num_int_alu_accesses            108731496                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu0.num_func_calls                    1065656                       # number of times a function call or return occured
 system.cpu0.num_conditional_control_insts     10277696                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                   108731496                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
@@ -288,10 +288,10 @@ system.cpu1.numCycles                     10407399002                       # nu
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.committedInsts                   46383066                       # Number of instructions committed
-system.cpu1.committedOps                     88725674                       # Number of ops (including micro ops) committed
+system.cpu1.committedOps                     88725672                       # Number of ops (including micro ops) committed
 system.cpu1.num_int_alu_accesses             85218419                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
+system.cpu1.num_func_calls                    1670749                       # number of times a function call or return occured
 system.cpu1.num_conditional_control_insts      7955161                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    85218419                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
index 09ee5a401534143ef4f98cb8f5715fc440f39255..a3f0789f487eb4330b004766e15837f2e0f53aa2 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.133111                       # Number of seconds simulated
-sim_ticks                                5133110815000                       # Number of ticks simulated
-final_tick                               5133110815000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.139557                       # Number of seconds simulated
+sim_ticks                                5139557121500                       # Number of ticks simulated
+final_tick                               5139557121500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 272926                       # Simulator instruction rate (inst/s)
-host_op_rate                                   542191                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5733082021                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 964520                       # Number of bytes of host memory used
-host_seconds                                   895.35                       # Real time elapsed on the host
-sim_insts                                   244363664                       # Number of instructions simulated
-sim_ops                                     485450482                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide      2484864                       # Number of bytes read from this memory
+host_inst_rate                                 183644                       # Simulator instruction rate (inst/s)
+host_op_rate                                   364835                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3871369364                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 967408                       # Number of bytes of host memory used
+host_seconds                                  1327.58                       # Real time elapsed on the host
+sim_insts                                   243802016                       # Number of instructions simulated
+sim_ops                                     484348047                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide      2455296                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           399872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5730880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           105152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1659200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         1216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           489280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          3010880                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13881664                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       399872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       105152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       489280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          994304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9191104                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9191104                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        38826                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu0.inst           466944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5828928                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           127616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1842944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           356032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2734144                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13813760                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       466944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       127616                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       356032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          950592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9154048                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9154048                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38364                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6248                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             89545                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1643                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             25925                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           19                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              7645                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             47045                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                216901                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          143611                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143611                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       484085                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst              7296                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             91077                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1994                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             28796                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           24                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              5563                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             42721                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                215840                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          143032                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143032                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       477725                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               77901                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1116454                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               20485                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              323235                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           237                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               95318                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              586560                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2704337                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          77901                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          20485                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          95318                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             193704                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1790552                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1790552                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1790552                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       484085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               90853                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1134130                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               24830                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              358580                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           299                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               69273                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              531980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2687734                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          90853                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          24830                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          69273                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             184956                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1781097                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1781097                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1781097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       477725                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              77901                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1116454                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              20485                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             323235                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          237                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              95318                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             586560                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4494890                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        101193                       # Total number of read requests seen
-system.physmem.writeReqs                        78846                       # Total number of write requests seen
-system.physmem.cpureqs                         181047                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                      6476352                       # Total number of bytes read from memory
-system.physmem.bytesWritten                   5046144                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                6476352                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                5046144                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                       41                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite               1005                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                  6749                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                  6143                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                  6157                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                  7514                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                  6089                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                  5671                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                  5777                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                  7080                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                  6052                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                  5601                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                 5675                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                 7038                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                 5939                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                 5837                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                 6375                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                 7455                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                  5123                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                  4689                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                  4672                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                  6199                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                  4650                       # Track writes on a per bank basis
+system.physmem.bw_total::cpu0.inst              90853                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1134130                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              24830                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             358580                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          299                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              69273                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             531980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4468830                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         99105                       # Total number of read requests seen
+system.physmem.writeReqs                        78746                       # Total number of write requests seen
+system.physmem.cpureqs                         178569                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                      6342720                       # Total number of bytes read from memory
+system.physmem.bytesWritten                   5039744                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd                6342720                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                5039744                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                       11                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite                712                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                  6100                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                  5671                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                  5539                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                  6946                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                  5876                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                  5654                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                  5883                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                  7012                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                  6334                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                  6064                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                 5868                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11                 7100                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12                 5762                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13                 5656                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                 6255                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                 7374                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                  4754                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                  4366                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                  4230                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                  5859                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                  4494                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::5                  4387                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                  4512                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                  5830                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                  4686                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                  4421                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                 4349                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                 5631                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                 4491                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                 4380                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                 4808                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                 6018                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                  4605                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                  5921                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                  5001                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                  4809                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                 4668                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                 5984                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                 4422                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                 4352                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                 4757                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                 6137                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                    5132091305000                       # Total gap between requests
+system.physmem.numWrRetry                           6                       # Number of times wr buffer was full causing retry
+system.physmem.totGap                    5135869541000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                  101193                       # Categorize read packet sizes
+system.physmem.readPktSize::6                   99105                       # Categorize read packet sizes
 system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                  78846                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                     77214                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      8676                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      3512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1689                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1504                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      1170                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       912                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       829                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      556                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      506                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      474                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      434                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      387                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      390                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      434                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      193                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  78746                       # Categorize write packet sizes
+system.physmem.rdQLenPdf::0                     75637                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      7751                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      3409                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1725                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1554                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      1226                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       983                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       957                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       916                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                       876                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      581                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      527                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      479                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      448                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      405                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      409                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      448                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      189                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                       97                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -156,304 +156,304 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      2905                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      3064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      3362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      3405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      3421                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      3435                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      3434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      3432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      3433                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      3428                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                      2865                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      3038                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      3360                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      3392                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                      3411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      3426                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      3425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      3425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      3422                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                      3426                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                     3424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     3423                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     3422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     3422                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     3419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3416                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3414                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3410                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3407                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3403                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      558                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                      395                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        3                       # What write queue length does an incoming req see
-system.physmem.totQLat                     2336250250                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                4424855250                       # Sum of mem lat for all requests
-system.physmem.totBusLat                    505760000                       # Total cycles spent in databus access
-system.physmem.totBankLat                  1582845000                       # Total cycles spent in bank access
-system.physmem.avgQLat                       23096.43                       # Average queueing delay per request
-system.physmem.avgBankLat                    15648.18                       # Average bank access latency per request
+system.physmem.wrQLenPdf::11                     3421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                     3419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                     3417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                     3415                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     3414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3412                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3407                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3404                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3403                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     3400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                      594                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                      412                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       88                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       30                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        7                       # What write queue length does an incoming req see
+system.physmem.totQLat                     2229520000                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat                4250910000                       # Sum of mem lat for all requests
+system.physmem.totBusLat                    495470000                       # Total cycles spent in databus access
+system.physmem.totBankLat                  1525920000                       # Total cycles spent in bank access
+system.physmem.avgQLat                       22499.04                       # Average queueing delay per request
+system.physmem.avgBankLat                    15398.71                       # Average bank access latency per request
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  43744.61                       # Average memory access latency
-system.physmem.avgRdBW                           1.26                       # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat                  42897.75                       # Average memory access latency
+system.physmem.avgRdBW                           1.23                       # Average achieved read bandwidth in MB/s
 system.physmem.avgWrBW                           0.98                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   1.26                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW                   1.23                       # Average consumed read bandwidth in MB/s
 system.physmem.avgConsumedWrBW                   0.98                       # Average consumed write bandwidth in MB/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
 system.physmem.avgWrQLen                         0.10                       # Average write queue length over time
-system.physmem.readRowHits                      84789                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     54894                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.82                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  69.62                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28505442.18                       # Average gap between requests
-system.l2c.replacements                        105754                       # number of replacements
-system.l2c.tagsinuse                     64827.685609                       # Cycle average of tags in use
-system.l2c.total_refs                         3731730                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        169931                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         21.960266                       # Average number of references to valid blocks.
+system.physmem.readRowHits                      83478                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     56534                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.24                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.79                       # Row buffer hit rate for writes
+system.physmem.avgGap                     28877372.30                       # Average gap between requests
+system.l2c.replacements                        104936                       # number of replacements
+system.l2c.tagsinuse                     64827.217537                       # Cycle average of tags in use
+system.l2c.total_refs                         3630977                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        168979                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         21.487741                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        50562.021644                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker       0.124352                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          1105.122085                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          4366.997770                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst           211.458182                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data          1301.465927                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.dtb.walker       3.202289                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst          1974.838993                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data          5302.454365                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.771515                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        50639.454481                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.125451                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          1092.997242                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          4517.674660                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           223.356063                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          1300.523613                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.dtb.walker       6.306120                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst          1891.819622                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data          5154.960284                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.772697                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.itb.walker      0.000002                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.016863                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.066635                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.003227                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.019859                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.dtb.walker      0.000049                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst            0.030134                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.data            0.080909                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.989192                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker        19783                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        10976                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             335265                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             516181                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         3330                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1120                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             152740                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             231467                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        92579                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        13716                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             391764                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             554488                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2323409                       # number of ReadReq hits
+system.l2c.occ_percent::cpu0.inst            0.016678                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.068934                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.003408                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.019844                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.dtb.walker      0.000096                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst            0.028867                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data            0.078658                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.989185                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker        20688                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        11397                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             368018                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             524840                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         3790                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1830                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             151783                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             229669                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        45217                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker         8673                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             312711                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             544544                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2223160                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1547018                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1547018                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             133                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              46                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              75                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 254                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            67056                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            49870                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            55865                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               172791                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         19783                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         10978                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              335265                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              583237                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          3330                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1120                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              152740                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              281337                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         92579                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         13716                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              391764                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              610353                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2496202                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        19783                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        10978                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             335265                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             583237                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         3330                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1120                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             152740                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             281337                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        92579                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        13716                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             391764                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             610353                       # number of overall hits
-system.l2c.overall_hits::total                2496202                       # number of overall hits
+system.l2c.Writeback_hits::writebacks         1544951                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1544951                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             152                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              41                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              67                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 260                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            71407                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            43953                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            57565                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               172925                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         20688                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker         11399                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              368018                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              596247                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          3790                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1830                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              151783                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              273622                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         45217                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker          8673                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              312711                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              602109                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2396087                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        20688                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker        11399                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             368018                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             596247                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         3790                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1830                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             151783                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             273622                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        45217                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker         8673                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             312711                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             602109                       # number of overall hits
+system.l2c.overall_hits::total                2396087                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.itb.walker            5                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             6248                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data            12943                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1643                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4995                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           19                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             7645                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data            15366                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                48864                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           572                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           316                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           468                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1356                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          76924                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          21191                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          32048                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             130163                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu0.inst             7296                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data            14431                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             1994                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             4052                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker           24                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             5567                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data            14790                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                48159                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data           746                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           231                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data           361                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1338                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          77254                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          24966                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          28044                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             130264                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.itb.walker            5                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              6248                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             89867                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1643                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             26186                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker           19                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              7645                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             47414                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                179027                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7296                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             91685                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1994                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             29018                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker           24                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              5567                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             42834                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                178423                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.itb.walker            5                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             6248                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            89867                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1643                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            26186                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker           19                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             7645                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            47414                       # number of overall misses
-system.l2c.overall_misses::total               179027                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst    103398500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    296551000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      1601000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    553329000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data   1041727494                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1996606994                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      3261500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data      5737499                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      8998999                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1096336500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   1799486495                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   2895822995                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    103398500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1392887500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker      1601000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    553329000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   2841213989                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      4892429989                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    103398500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1392887500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker      1601000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    553329000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   2841213989                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     4892429989                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        19783                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        10981                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         341513                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         529124                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         3330                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1120                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         154383                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         236462                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker        92598                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        13716                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         399409                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         569854                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2372273                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_misses::cpu0.inst             7296                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            91685                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1994                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            29018                       # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker           24                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             5567                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            42834                       # number of overall misses
+system.l2c.overall_misses::total               178423                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst    122911000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    250826000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      1797000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    390878500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data    976895991                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1743308491                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      1987000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data      4443500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      6430500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1303821500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   1552905500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2856727000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    122911000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1554647500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker      1797000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    390878500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   2529801491                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      4600035491                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    122911000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1554647500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker      1797000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    390878500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   2529801491                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     4600035491                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        20688                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker        11402                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         375314                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         539271                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         3790                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1830                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         153777                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         233721                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        45241                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker         8673                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst         318278                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data         559334                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2271319                       # number of ReadReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1547018                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1547018                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data          705                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          362                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data          543                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1610                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       143980                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        71061                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        87913                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           302954                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        19783                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        10983                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          341513                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          673104                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         3330                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1120                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          154383                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          307523                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker        92598                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        13716                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          399409                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          657767                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2675229                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        19783                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        10983                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         341513                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         673104                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         3330                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1120                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         154383                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         307523                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        92598                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        13716                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         399409                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         657767                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2675229                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000455                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.018295                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.024461                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010642                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.021124                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000205                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.019141                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.026965                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.020598                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.811348                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.872928                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.861878                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.842236                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.534269                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.298209                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.364542                       # miss rate for ReadExReq accesses
+system.l2c.Writeback_accesses::writebacks      1544951                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1544951                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data          898                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          272                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data          428                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1598                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       148661                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        68919                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        85609                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           303189                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        20688                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker        11404                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          375314                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          687932                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         3790                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1830                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          153777                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          302640                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        45241                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker         8673                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          318278                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          644943                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2574510                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        20688                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker        11404                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         375314                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         687932                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         3790                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1830                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         153777                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         302640                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        45241                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker         8673                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         318278                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         644943                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2574510                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000439                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.019440                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.026760                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.012967                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.017337                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000530                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.017491                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.026442                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.021203                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.830735                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.849265                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.843458                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.837297                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.519666                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.362251                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.327582                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total        0.429646                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000455                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.018295                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.133511                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010642                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.085151                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000205                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.019141                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.072083                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.066920                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000455                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.018295                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.133511                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010642                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.085151                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000205                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.019141                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.072083                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.066920                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 62932.744979                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 59369.569570                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84263.157895                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 72377.894048                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 67794.318235                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 40860.490218                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 10321.202532                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12259.613248                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6636.429941                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 51735.949224                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 56149.728376                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 22247.666349                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 62932.744979                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 53192.068281                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84263.157895                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 72377.894048                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 59923.524465                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 27327.889028                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 62932.744979                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 53192.068281                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84263.157895                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 72377.894048                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 59923.524465                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 27327.889028                       # average overall miss latency
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000438                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.019440                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.133276                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.012967                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.095883                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000530                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.017491                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.066415                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.069304                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000438                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.019440                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.133276                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.012967                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.095883                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000530                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.017491                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.066415                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.069304                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 61640.421264                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 61901.776900                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker        74875                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70213.490210                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 66051.115010                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 36199.017650                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  8601.731602                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12308.864266                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4806.053812                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52223.884483                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 55373.894594                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 21930.287723                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 61640.421264                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 53575.280860                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker        74875                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 70213.490210                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 59060.594178                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 25781.628439                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 61640.421264                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 53575.280860                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker        74875                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 70213.490210                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 59060.594178                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 25781.628439                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -462,119 +462,119 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               96944                       # number of writebacks
-system.l2c.writebacks::total                    96944                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1643                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4995                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           19                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         7645                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data        15365                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           29667                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          316                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          468                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          784                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        21191                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        32048                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         53239                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1643                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        26186                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           19                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         7645                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        47413                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            82906                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1643                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        26186                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           19                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         7645                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        47413                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           82906                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     82735143                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    234275272                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      1365263                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    458273787                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data    850361157                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1627010622                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      3210315                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      4800964                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      8011279                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    829338934                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1395043627                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   2224382561                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     82735143                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1063614206                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      1365263                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    458273787                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   2245404784                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   3851393183                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     82735143                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1063614206                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      1365263                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    458273787                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   2245404784                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   3851393183                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28696022500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30542112500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  59238135000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    349705500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    850322500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1200028000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  29045728000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31392435000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  60438163000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010642                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.021124                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000205                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.019141                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.026963                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.012506                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.872928                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.861878                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.486957                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.298209                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.364542                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.175733                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010642                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.085151                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000205                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.019141                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.072082                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.030990                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010642                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.085151                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000205                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.019141                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.072082                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.030990                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 50356.143031                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46901.956356                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 71855.947368                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59944.249444                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55344.038855                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 54842.438467                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10159.224684                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10258.470085                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10218.468112                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 39136.375537                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43529.818616                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41781.073292                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50356.143031                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40617.666157                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71855.947368                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59944.249444                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 47358.420349                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 46454.939124                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50356.143031                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40617.666157                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71855.947368                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59944.249444                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 47358.420349                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 46454.939124                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks               96365                       # number of writebacks
+system.l2c.writebacks::total                    96365                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu2.inst             4                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 4                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  4                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 4                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu1.inst         1994                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         4052                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           24                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         5563                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data        14790                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           26423                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          231                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          361                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          592                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        24966                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        28044                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         53010                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1994                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        29018                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           24                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         5563                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        42834                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            79433                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1994                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        29018                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           24                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         5563                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        42834                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           79433                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     97847743                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    200215627                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      1495274                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    321284586                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    792603807                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1413447037                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2410729                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      3666859                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      6077588                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    988776449                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1199056726                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   2187833175                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     97847743                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1188992076                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      1495274                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    321284586                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   1991660533                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   3601280212                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     97847743                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1188992076                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      1495274                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    321284586                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   1991660533                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   3601280212                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28659296500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30447811500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  59107108000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    345721500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    690071500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1035793000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  29005018000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31137883000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60142901000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.012967                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017337                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000530                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.017478                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.026442                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.011633                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.849265                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.843458                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.370463                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.362251                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.327582                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.174841                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.012967                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.095883                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000530                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.017478                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.066415                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.030854                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.012967                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.095883                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000530                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.017478                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.066415                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.030854                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 49071.084754                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49411.556515                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57753.835341                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 53590.521095                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 53493.056693                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10436.056277                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10157.504155                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10266.195946                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 39604.920652                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 42756.266082                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41272.084041                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49071.084754                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40974.294438                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57753.835341                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46497.187585                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 45337.330983                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49071.084754                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40974.294438                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62303.083333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57753.835341                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46497.187585                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 45337.330983                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -585,39 +585,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47574                       # number of replacements
-system.iocache.tagsinuse                     0.080510                       # Cycle average of tags in use
+system.iocache.replacements                     47571                       # number of replacements
+system.iocache.tagsinuse                     0.100524                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47590                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47587                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4999662298059                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.080510                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.005032                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.005032                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
+system.iocache.warmup_cycle              4999700789059                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide     0.100524                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.006283                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.006283                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          906                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              906                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47629                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47629                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47629                       # number of overall misses
-system.iocache.overall_misses::total            47629                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    129741871                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    129741871                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   4861732608                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   4861732608                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   4991474479                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   4991474479                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   4991474479                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   4991474479                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47626                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47626                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47626                       # number of overall misses
+system.iocache.overall_misses::total            47626                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide     21701996                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21701996                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   5260229904                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5260229904                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   5281931900                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5281931900                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   5281931900                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5281931900                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          906                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            906                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47629                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47629                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47629                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47626                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47626                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47626                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47626                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -626,60 +626,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142730.331133                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 142730.331133                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 104061.057534                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 104061.057534                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 104799.061055                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 104799.061055                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 104799.061055                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 104799.061055                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         68462                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23953.637969                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 23953.637969                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 112590.537329                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 112590.537329                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 110904.377861                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 110904.377861                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 110904.377861                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 110904.377861                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         67344                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 6315                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 6552                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.841172                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    10.278388                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          764                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          764                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        22592                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        22592                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        23356                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        23356                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        23356                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        23356                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     89992399                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     89992399                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3686306893                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   3686306893                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   3776299292                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3776299292                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   3776299292                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3776299292                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.840484                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.840484                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.483562                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total     0.483562                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.490374                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.490374                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.490374                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.490374                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117791.098168                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 117791.098168                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163168.683295                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 163168.683295                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161684.333448                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 161684.333448                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161684.333448                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 161684.333448                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          169                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          169                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        24864                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        24864                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        25033                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        25033                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        25033                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        25033                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     12912498                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12912498                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3966572850                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3966572850                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   3979485348                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3979485348                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   3979485348                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3979485348                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.186534                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.186534                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.532192                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total     0.532192                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.525616                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.525616                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.525616                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.525616                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 76405.313609                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76405.313609                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 159530.761342                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 159530.761342                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 158969.574082                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 158969.574082                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           29                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -689,336 +689,336 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu0.numCycles                      1742412594                       # number of cpu cycles simulated
+system.cpu0.numCycles                      1838156995                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   72300698                       # Number of instructions committed
-system.cpu0.committedOps                    146721419                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            135119362                       # Number of integer alu accesses
+system.cpu0.committedInsts                   73261263                       # Number of instructions committed
+system.cpu0.committedOps                    148566469                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            136919559                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14129272                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   135119362                       # number of integer instructions
+system.cpu0.num_func_calls                    1069041                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14289344                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   136919559                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          332380651                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         171799243                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          336929611                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         173945922                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     14355035                       # number of memory refs
-system.cpu0.num_load_insts                   10404244                       # Number of load instructions
-system.cpu0.num_store_insts                   3950791                       # Number of store instructions
-system.cpu0.num_idle_cycles              1032160899328.073853                       # Number of idle cycles
-system.cpu0.num_busy_cycles              -1030418486734.073853                       # Number of busy cycles
-system.cpu0.not_idle_fraction             -591.374563                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                  592.374563                       # Percentage of idle cycles
+system.cpu0.num_mem_refs                     14717824                       # number of memory refs
+system.cpu0.num_load_insts                   10660250                       # Number of load instructions
+system.cpu0.num_store_insts                   4057574                       # Number of store instructions
+system.cpu0.num_idle_cycles              1090327710419.609375                       # Number of idle cycles
+system.cpu0.num_busy_cycles              -1088489553424.609375                       # Number of busy cycles
+system.cpu0.not_idle_fraction             -592.163540                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                  593.163540                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.icache.replacements                894848                       # number of replacements
-system.cpu0.icache.tagsinuse               510.913561                       # Cycle average of tags in use
-system.cpu0.icache.total_refs               128448966                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                895360                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                143.460693                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle          147286851000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   366.522543                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst    28.161806                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu2.inst   116.229212                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.715864                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu1.inst     0.055004                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu2.inst     0.227010                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.997878                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     88078408                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     37386418                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2984140                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      128448966                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     88078408                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     37386418                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2984140                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       128448966                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     88078408                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     37386418                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2984140                       # number of overall hits
-system.cpu0.icache.overall_hits::total      128448966                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       341513                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       154383                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       422579                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       918475                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       341513                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       154383                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       422579                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        918475                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       341513                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       154383                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       422579                       # number of overall misses
-system.cpu0.icache.overall_misses::total       918475                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2101458500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6067832979                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8169291479                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2101458500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   6067832979                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8169291479                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2101458500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   6067832979                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8169291479                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     88419921                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     37540801                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3406719                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    129367441                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     88419921                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     37540801                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3406719                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    129367441                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     88419921                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     37540801                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3406719                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    129367441                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003862                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004112                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.124043                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.007100                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003862                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004112                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.124043                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.007100                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003862                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004112                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.124043                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.007100                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13611.981241                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14359.049974                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8894.408099                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13611.981241                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14359.049974                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8894.408099                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13611.981241                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14359.049974                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8894.408099                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        12687                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets          590                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              356                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    35.637640                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          590                       # average number of cycles each access was blocked
+system.cpu0.icache.replacements                846873                       # number of replacements
+system.cpu0.icache.tagsinuse               510.809979                       # Cycle average of tags in use
+system.cpu0.icache.total_refs               129726169                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                847385                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                153.089999                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle          147287067000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   322.415881                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst    27.501112                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu2.inst   160.892986                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.629719                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst     0.053713                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu2.inst     0.314244                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.997676                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     89310227                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     37866681                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2549261                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      129726169                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     89310227                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     37866681                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2549261                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       129726169                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     89310227                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     37866681                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2549261                       # number of overall hits
+system.cpu0.icache.overall_hits::total      129726169                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       375314                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       153777                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       335702                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       864793                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       375314                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       153777                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       335702                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        864793                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       375314                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       153777                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       335702                       # number of overall misses
+system.cpu0.icache.overall_misses::total       864793                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2109411000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4767990981                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6877401981                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   2109411000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4767990981                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6877401981                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   2109411000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4767990981                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6877401981                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     89685541                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     38020458                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2884963                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    130590962                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     89685541                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     38020458                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      2884963                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    130590962                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     89685541                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     38020458                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      2884963                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    130590962                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.004185                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004045                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.116363                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.006622                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.004185                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004045                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.116363                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.006622                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.004185                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004045                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.116363                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.006622                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13717.337443                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14203.046097                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  7952.656857                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13717.337443                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14203.046097                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  7952.656857                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13717.337443                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14203.046097                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  7952.656857                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         6416                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              225                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    28.515556                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23101                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        23101                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        23101                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        23101                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        23101                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        23101                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       154383                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       399478                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       553861                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       154383                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       399478                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       553861                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       154383                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       399478                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       553861                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1792692500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5012362480                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6805054980                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1792692500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5012362480                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6805054980                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1792692500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5012362480                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6805054980                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004112                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.117262                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004281                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004112                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.117262                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004281                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004112                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.117262                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004281                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11611.981241                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12547.280401                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12286.575477                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11611.981241                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12547.280401                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12286.575477                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11611.981241                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12547.280401                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12286.575477                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        17396                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        17396                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        17396                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        17396                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        17396                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        17396                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       153777                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       318306                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       472083                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       153777                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       318306                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       472083                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       153777                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       318306                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       472083                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1801857000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3960171483                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5762028483                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1801857000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3960171483                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5762028483                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1801857000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3960171483                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5762028483                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004045                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.110333                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.003615                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004045                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.110333                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.003615                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004045                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.110333                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.003615                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11717.337443                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12441.397533                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12205.541151                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11717.337443                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12441.397533                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12205.541151                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11717.337443                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12441.397533                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12205.541151                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements               1637829                       # number of replacements
-system.cpu0.dcache.tagsinuse               511.999325                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                19719847                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs               1638341                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 12.036473                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle               7550500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   486.525664                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu1.data    16.669360                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu2.data     8.804301                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.950245                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu1.data     0.032557                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu2.data     0.017196                       # Average percentage of cache occupancy
+system.cpu0.dcache.replacements               1634958                       # number of replacements
+system.cpu0.dcache.tagsinuse               511.999366                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                19655982                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1635470                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 12.018552                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle               7549500                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   482.608033                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data    17.353549                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu2.data    12.037784                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.942594                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data     0.033894                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu2.data     0.023511                       # Average percentage of cache occupancy
 system.cpu0.dcache.occ_percent::total        0.999999                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5387330                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2122125                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4119415                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11628870                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3803545                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1464488                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2821209                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8089242                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9190875                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      3586613                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6940624                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19718112                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9190875                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      3586613                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6940624                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19718112                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       529124                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       236462                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       932462                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1698048                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       144685                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        71423                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data        99870                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       315978                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       673809                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       307885                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1032332                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2014026                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       673809                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       307885                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1032332                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2014026                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3328476000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  15456118000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  18784594000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1822382500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   2810623495                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   4633005995                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   5150858500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  18266741495                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  23417599995                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   5150858500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  18266741495                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  23417599995                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5916454                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2358587                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      5051877                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13326918                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3948230                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1535911                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2921079                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8405220                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      9864684                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      3894498                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7972956                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21732138                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9864684                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      3894498                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7972956                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21732138                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.089433                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.100256                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.184577                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.127415                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036646                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.046502                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.034189                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.037593                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.068305                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.079056                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.129479                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.092675                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.068305                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.079056                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.129479                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.092675                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14076.156000                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16575.600936                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 11062.463487                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25515.345197                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 28142.820617                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 14662.432179                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 16729.813080                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17694.638445                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 11627.258037                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16729.813080                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17694.638445                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11627.258037                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       176638                       # number of cycles access was blocked
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5624800                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2207994                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      3726568                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       11559362                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3904284                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1548034                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      2642598                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       8094916                       # number of WriteReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9529084                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      3756028                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      6369166                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        19654278                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9529084                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      3756028                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      6369166                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       19654278                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       539271                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       233721                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       917659                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1690651                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       149559                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        69191                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data        97336                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       316086                       # number of WriteReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       688830                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       302912                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1014995                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2006737                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       688830                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       302912                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1014995                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2006737                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3256389500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  15046703000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  18303092500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1959155500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   2564161499                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   4523316999                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   5215545000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  17610864499                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  22826409499                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   5215545000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  17610864499                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  22826409499                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6164071                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      2441715                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4644227                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13250013                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4053843                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1617225                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2739934                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      8411002                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     10217914                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      4058940                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7384161                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     21661015                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     10217914                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      4058940                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7384161                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21661015                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.087486                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.095720                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.197591                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.127596                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036893                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.042784                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.035525                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.037580                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.067414                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.074628                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.137456                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.092643                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.067414                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.074628                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.137456                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.092643                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13932.806637                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16396.834772                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10826.061973                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28315.178275                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26343.403253                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 14310.399698                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17218.020415                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17350.690889                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 11374.888438                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17218.020415                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17350.690889                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 11374.888438                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       180086                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            12002                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            11859                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.717380                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.185597                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1547018                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1547018                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       362388                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       362388                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        11634                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        11634                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       374022                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       374022                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       374022                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       374022                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       236462                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       570074                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       806536                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        71423                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        88236                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       159659                       # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       307885                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       658310                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       966195                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       307885                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       658310                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       966195                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2855552000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8374924000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  11230476000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1679536500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2505829996                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4185366496                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4535088500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10880753996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  15415842496                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4535088500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  10880753996                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  15415842496                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  31206994500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33315270500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  64522265000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    372935500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    904884500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1277820000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31579930000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34220155000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65800085000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.100256                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.112844                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.060519                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.046502                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.030207                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018995                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.079056                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.082568                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.044459                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.079056                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.082568                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.044459                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12076.156000                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14690.941878                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13924.333198                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23515.345197                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 28399.179428                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26214.410061                       # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 14729.813080                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16528.313403                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15955.208313                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 14729.813080                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16528.313403                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15955.208313                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      1544951                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1544951                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       358302                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       358302                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        11322                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        11322                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       369624                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       369624                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       369624                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       369624                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       233721                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       559357                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       793078                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        69191                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        86014                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       155205                       # number of WriteReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       302912                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       645371                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       948283                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       302912                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       645371                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       948283                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2788947500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8180959500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  10969907000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1820773500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2270883499                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4091656999                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4609721000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  10451842999                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  15061563999                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4609721000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  10451842999                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  15061563999                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  31167993500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33212773000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  64380766500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    368756500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    730986500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1099743000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31536750000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33943759500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65480509500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.095720                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.120441                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.059855                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.042784                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031393                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018453                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.074628                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.087399                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.043778                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.074628                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.087399                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.043778                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11932.806637                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14625.649630                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13832.065698                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26315.178275                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26401.324191                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26362.920003                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15218.020415                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16195.092434                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15882.984298                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15218.020415                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16195.092434                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15882.984298                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1029,303 +1029,303 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2604004638                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2606004355                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   34050358                       # Number of instructions committed
-system.cpu1.committedOps                     66241025                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             61396531                       # Number of integer alu accesses
+system.cpu1.committedInsts                   34463532                       # Number of instructions committed
+system.cpu1.committedOps                     67005357                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             62150402                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6330827                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    61396531                       # number of integer instructions
+system.cpu1.num_func_calls                     411236                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6382216                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    62150402                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          147773528                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          79124330                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          149729485                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          79937808                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4089746                       # number of memory refs
-system.cpu1.num_load_insts                    2551885                       # Number of load instructions
-system.cpu1.num_store_insts                   1537861                       # Number of store instructions
-system.cpu1.num_idle_cycles              7651672288.559311                       # Number of idle cycles
-system.cpu1.num_busy_cycles              -5047667650.559310                       # Number of busy cycles
-system.cpu1.not_idle_fraction               -1.938425                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    2.938425                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                      4253944                       # number of memory refs
+system.cpu1.num_load_insts                    2634755                       # Number of load instructions
+system.cpu1.num_store_insts                   1619189                       # Number of store instructions
+system.cpu1.num_idle_cycles              7677367348.593150                       # Number of idle cycles
+system.cpu1.num_busy_cycles              -5071362993.593150                       # Number of busy cycles
+system.cpu1.not_idle_fraction               -1.946030                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    2.946030                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               29453623                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         29453623                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           415098                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            27524978                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               26775027                       # Number of BTB hits
+system.cpu2.branchPred.lookups               28657213                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         28657213                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           282528                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26332341                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               25809696                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.275380                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                      0                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect                 0                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       155984085                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            98.015197                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 509678                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             56598                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       152138342                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          10604817                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     145070644                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   29453623                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26775027                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     55443665                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                1825085                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                    101909                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles              22639923                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                2951                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             5864                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles         5243                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles         1584                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3406726                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               188434                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   3455                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          90201759                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             3.168652                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.414059                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           8765036                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     141230370                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   28657213                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26319374                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     54195726                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                1350224                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     59186                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles              22546148                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles                3184                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             6465                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        18223                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.IcacheWaitRetryStallCycles          777                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2884967                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               126552                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   1685                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          86648155                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             3.214672                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.414816                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                34888289     38.68%     38.68% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  600988      0.67%     39.34% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                24050058     26.66%     66.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  353959      0.39%     66.40% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  625644      0.69%     67.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  870018      0.96%     68.06% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  382969      0.42%     68.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  534158      0.59%     69.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27895676     30.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                32565830     37.58%     37.58% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  546380      0.63%     38.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23846422     27.52%     65.74% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  287955      0.33%     66.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  558507      0.64%     66.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  803239      0.93%     67.64% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  320738      0.37%     68.01% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  484990      0.56%     68.57% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27234094     31.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            90201759                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.188825                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.930035                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                12002495                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             21681187                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 45325562                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              1251433                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               1399062                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             284656362                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                    4                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               1399062                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                13027629                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               13040843                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       3781171                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 45395781                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              5015320                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             283355773                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 7223                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               2405393                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents              1942678                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents            3127                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands          338147018                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            617097261                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       617097023                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups              238                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            325868282                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                12278736                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            148774                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        149957                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 11224608                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6517761                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3579821                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           461835                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          357597                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 281093420                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             441880                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                278958104                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            66093                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        8698902                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     13192307                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         82110                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     90201759                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        3.092602                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.393390                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            86648155                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.188363                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.928302                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                10203383                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             21434341                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 42926723                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              1270829                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               1056674                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             277800524                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                   10                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles               1056674                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                11171095                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               12732005                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       3756843                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 43068844                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              5106557                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             276894625                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 6426                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               2483944                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents              1961652                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents            2548                       # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands          331033770                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            601753258                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       601753178                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups               80                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            321557178                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 9476592                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            136008                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        137084                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 11206153                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             5917951                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3223233                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           365517                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          302609                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 275352384                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             397965                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                273886109                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            53996                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        6700477                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     10323870                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         50144                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     86648155                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        3.160899                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.377923                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           26012470     28.84%     28.84% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            6039286      6.70%     35.53% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3951880      4.38%     39.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            2755931      3.06%     42.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           25450269     28.21%     71.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            1402946      1.56%     72.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           24246567     26.88%     99.62% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             287223      0.32%     99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              55187      0.06%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           23779115     27.44%     27.44% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            5842995      6.74%     34.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3792974      4.38%     38.56% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            2596888      3.00%     41.56% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           25119641     28.99%     70.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            1266341      1.46%     72.01% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           23944050     27.63%     99.65% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             257275      0.30%     99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              48876      0.06%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       90201759                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       86648155                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                 134556     34.98%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     34.98% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                196649     51.12%     86.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                53504     13.91%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                 118795     33.06%     33.06% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                   241      0.07%     33.13% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                     86      0.02%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     33.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                188736     52.53%     85.68% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                51440     14.32%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            83173      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            268863326     96.38%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6715737      2.41%     98.82% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3295868      1.18%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            68063      0.02%      0.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            264478225     96.57%     96.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               51078      0.02%     96.61% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                47173      0.02%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.63% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6223177      2.27%     98.90% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3018393      1.10%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             278958104                       # Type of FU issued
-system.cpu2.iq.rate                          1.788375                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     384709                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001379                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         648620730                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        290237963                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    277347431                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                 99                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes               114                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           26                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             279259593                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     47                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          629589                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             273886109                       # Type of FU issued
+system.cpu2.iq.rate                          1.800244                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     359298                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001312                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         634870698                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        282454128                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    272600027                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                 31                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes                36                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses            8                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             274177330                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                     14                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          614321                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1208294                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         7639                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         4324                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       653312                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       929558                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         6267                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         3704                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       478908                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       656809                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        10508                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       656133                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        10377                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               1399062                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                8628497                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               800211                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          281535300                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts           104725                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6517761                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3579821                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            245066                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                628910                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                 4050                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          4324                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        245790                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       219209                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              464999                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            278243266                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6548770                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           714838                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles               1056674                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                8226180                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               803204                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          275750349                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            63685                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              5917951                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3223233                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            220549                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                623968                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 3956                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          3704                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        161931                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       157888                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              319819                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            273437676                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6124763                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           448433                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     9760405                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                28303676                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3211635                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.783793                       # Inst execution rate
-system.cpu2.iew.wb_sent                     278068144                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    277347457                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                216266417                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                353604041                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                     9083662                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27821550                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2958899                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.797296                       # Inst execution rate
+system.cpu2.iew.wb_sent                     273301697                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    272600035                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                212879972                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                348297595                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.778050                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.611606                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.791790                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.611201                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        9045420                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         359770                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           415805                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     88802697                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     3.068466                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.866565                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        6973062                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         347821                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           284653                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     85591481                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     3.140222                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.867307                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     30564443     34.42%     34.42% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4416110      4.97%     39.39% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1290481      1.45%     40.84% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     25052940     28.21%     69.06% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       877654      0.99%     70.04% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       569019      0.64%     70.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       327531      0.37%     71.05% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23624903     26.60%     97.66% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2079616      2.34%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     28429929     33.22%     33.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4148762      4.85%     38.06% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1193631      1.39%     39.46% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24678313     28.83%     68.29% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       797871      0.93%     69.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       541346      0.63%     69.85% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       330295      0.39%     70.24% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23445398     27.39%     97.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2025936      2.37%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     88802697                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           138012608                       # Number of instructions committed
-system.cpu2.commit.committedOps             272488038                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     85591481                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           136077221                       # Number of instructions committed
+system.cpu2.commit.committedOps             268776221                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8235976                       # Number of memory references committed
-system.cpu2.commit.loads                      5309467                       # Number of loads committed
-system.cpu2.commit.membars                     167075                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27913254                       # Number of branches committed
+system.cpu2.commit.refs                       7732718                       # Number of memory references committed
+system.cpu2.commit.loads                      4988393                       # Number of loads committed
+system.cpu2.commit.membars                     163760                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27507890                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                248812400                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls                   0                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events              2079616                       # number cycles where commit BW limit reached
+system.cpu2.commit.int_insts                245262632                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              414873                       # Number of function calls committed.
+system.cpu2.commit.bw_lim_events              2025936                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   368229083                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  564472103                       # The number of ROB writes
-system.cpu2.timesIdled                         458685                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       65782326                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4902194189                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  138012608                       # Number of Instructions Simulated
-system.cpu2.committedOps                    272488038                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total            138012608                       # Number of Instructions Simulated
-system.cpu2.cpi                              1.130216                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.130216                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.884786                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.884786                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               511223313                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              330894999                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    62522                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   62496                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads               90285732                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                129561                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                   359289994                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  552558663                       # The number of ROB writes
+system.cpu2.timesIdled                         454161                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       65490187                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4914041775                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  136077221                       # Number of Instructions Simulated
+system.cpu2.committedOps                    268776221                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total            136077221                       # Number of Instructions Simulated
+system.cpu2.cpi                              1.118029                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.118029                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.894431                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.894431                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               502349004                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              325553024                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    62552                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   62544                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads               88383748                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                121022                       # number of misc regfile writes
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
index a7b0854c313dd6f2f8c46f6c8d00618b30a329ff..b2e32248a22cce3e4a96518047953788313855af 100644 (file)
@@ -1,72 +1,72 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.607388                       # Number of seconds simulated
-sim_ticks                                607388314000                       # Number of ticks simulated
-final_tick                               607388314000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.602332                       # Number of seconds simulated
+sim_ticks                                602332345500                       # Number of ticks simulated
+final_tick                               602332345500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39851                       # Simulator instruction rate (inst/s)
-host_op_rate                                    73427                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               27504625                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294932                       # Number of bytes of host memory used
-host_seconds                                 22083.13                       # Real time elapsed on the host
+host_inst_rate                                  59375                       # Simulator instruction rate (inst/s)
+host_op_rate                                   109402                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               40639301                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298404                       # Number of bytes of host memory used
+host_seconds                                 14821.42                       # Real time elapsed on the host
 sim_insts                                   880025277                       # Number of instructions simulated
 sim_ops                                    1621493927                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             57920                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1693120                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1751040                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        57920                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           57920                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks       162112                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            162112                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                905                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              26455                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 27360                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            2533                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                 2533                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                95359                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2787541                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2882900                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           95359                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              95359                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            266900                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 266900                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            266900                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               95359                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2787541                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3149800                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         27361                       # Total number of read requests seen
-system.physmem.writeReqs                         2533                       # Total number of write requests seen
-system.physmem.cpureqs                          29894                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                      1751040                       # Total number of bytes read from memory
-system.physmem.bytesWritten                    162112                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                1751040                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                 162112                       # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst             57280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1693184                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1750464                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        57280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           57280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks       162240                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            162240                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                895                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              26456                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 27351                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            2535                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                 2535                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                95097                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2811046                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2906143                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           95097                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              95097                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            269353                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 269353                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            269353                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               95097                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2811046                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3175496                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         27351                       # Total number of read requests seen
+system.physmem.writeReqs                         2535                       # Total number of write requests seen
+system.physmem.cpureqs                          29886                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                      1750464                       # Total number of bytes read from memory
+system.physmem.bytesWritten                    162240                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd                1750464                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                 162240                       # bytesWritten derated as per pkt->getSize()
 system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                  1742                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                  1718                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                  1710                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0                  1741                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                  1716                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                  1707                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::3                  1642                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                  1656                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                  1655                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                  1657                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                  1659                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::6                  1713                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                  1701                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                  1714                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                  1710                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                 1717                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                 1730                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                 1739                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                 1728                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                 1751                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                 1735                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                   160                       # Track writes on a per bank basis
+system.physmem.perBankRdReqs::7                  1703                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                  1711                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                  1703                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                 1718                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11                 1725                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12                 1737                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13                 1725                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                 1752                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                 1742                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                   159                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::1                   161                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::2                   160                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::3                   155                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::4                   155                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                   154                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                   155                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::6                   158                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                   157                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                   158                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::8                   156                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::9                   160                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::10                  158                       # Track writes on a per bank basis
@@ -74,28 +74,28 @@ system.physmem.perBankWrReqs::11                  159                       # Tr
 system.physmem.perBankWrReqs::12                  159                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::13                  158                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::14                  164                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                  159                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                  160                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                    607388300000                       # Total gap between requests
+system.physmem.totGap                    602332206500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                   27361                       # Categorize read packet sizes
+system.physmem.readPktSize::6                   27351                       # Categorize read packet sizes
 system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                   2533                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                     26894                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       344                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        98                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        22                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                   2535                       # Categorize write packet sizes
+system.physmem.rdQLenPdf::0                     26932                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       329                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        72                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -127,8 +127,8 @@ system.physmem.rdQLenPdf::31                        0                       # Wh
 system.physmem.wrQLenPdf::0                       111                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                       111                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                       111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       111                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::5                       110                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::6                       110                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::7                       110                       # What write queue length does an incoming req see
@@ -156,265 +156,265 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.totQLat                       89920500                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                 894824250                       # Sum of mem lat for all requests
-system.physmem.totBusLat                    136805000                       # Total cycles spent in databus access
-system.physmem.totBankLat                   668098750                       # Total cycles spent in bank access
-system.physmem.avgQLat                        3286.45                       # Average queueing delay per request
-system.physmem.avgBankLat                    24417.92                       # Average bank access latency per request
+system.physmem.totQLat                       88037750                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat                 893262750                       # Sum of mem lat for all requests
+system.physmem.totBusLat                    136755000                       # Total cycles spent in databus access
+system.physmem.totBankLat                   668470000                       # Total cycles spent in bank access
+system.physmem.avgQLat                        3218.81                       # Average queueing delay per request
+system.physmem.avgBankLat                    24440.42                       # Average bank access latency per request
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  32704.37                       # Average memory access latency
-system.physmem.avgRdBW                           2.88                       # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat                  32659.24                       # Average memory access latency
+system.physmem.avgRdBW                           2.91                       # Average achieved read bandwidth in MB/s
 system.physmem.avgWrBW                           0.27                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   2.88                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW                   2.91                       # Average consumed read bandwidth in MB/s
 system.physmem.avgConsumedWrBW                   0.27                       # Average consumed write bandwidth in MB/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
-system.physmem.avgWrQLen                        12.62                       # Average write queue length over time
-system.physmem.readRowHits                      16432                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                      1027                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   60.06                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  40.54                       # Row buffer hit rate for writes
-system.physmem.avgGap                     20318067.17                       # Average gap between requests
-system.cpu.branchPred.lookups               158363276                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         158363276                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          26388177                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             84556073                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                84327975                       # Number of BTB hits
+system.physmem.avgWrQLen                         8.01                       # Average write queue length over time
+system.physmem.readRowHits                      16404                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                      1020                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   59.98                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  40.24                       # Row buffer hit rate for writes
+system.physmem.avgGap                     20154326.66                       # Average gap between requests
+system.cpu.branchPred.lookups               155894666                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         155894666                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          25699129                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             80742532                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                80542859                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.730241                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.752704                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 2586842                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               5513                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       1214776629                       # number of cpu cycles simulated
+system.cpu.numCycles                       1204664695                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          179085869                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1458535582                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   158363276                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           84327975                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     399051382                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                88177914                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              574644515                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   45                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           339                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 188128638                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes              12060508                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1214415274                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.059853                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.253551                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          175314236                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1434822441                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   155894666                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           83129701                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     393116244                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                83893731                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              577823849                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  123                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           791                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 184597714                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11658023                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1204295068                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.043367                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.243240                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                822580385     67.73%     67.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 26905566      2.22%     69.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 13181581      1.09%     71.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 20540967      1.69%     72.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 26638083      2.19%     74.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 18230799      1.50%     76.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 31362370      2.58%     79.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 39059510      3.22%     82.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                215916013     17.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                818096949     67.93%     67.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 26918487      2.24%     70.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 12895052      1.07%     71.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 20223867      1.68%     72.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 26382325      2.19%     75.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 18061341      1.50%     76.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 31920988      2.65%     79.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 38294164      3.18%     82.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                211501895     17.56%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1214415274                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.130364                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.200662                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                288243803                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             497890873                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 274138871                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              92508603                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               61633124                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2344113948                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               61633124                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                336916939                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               124193279                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           2662                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 304031533                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             387637737                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2248223321                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   352                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              242707605                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             120173474                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2618640021                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5724414358                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       5724407502                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              6856                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1204295068                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.129409                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.191055                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                284492311                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             500325603                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 268669661                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              92767668                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               58039825                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2310318754                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               58039825                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                333414311                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               124348906                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           3625                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 298566996                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             389921405                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2218156227                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   521                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              243059098                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             121762189                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2583430749                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5648758417                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       5648752173                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              6244                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1886895260                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                731744761                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 86                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             86                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 731270344                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            531930252                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           219281722                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         342004102                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        144706308                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1994081706                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 268                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1783937479                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            271890                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       372188972                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    760599366                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            219                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1214415274                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.468968                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.421626                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                696535489                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                103                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            103                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 737453259                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            525280959                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           216617119                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         339037703                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        144743699                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1968663502                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 332                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1774132594                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            144752                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       346851970                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    707722705                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            283                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1204295068                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.473171                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.418728                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           360308657     29.67%     29.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           364274837     30.00%     59.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           234367873     19.30%     78.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           141282709     11.63%     90.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            60755557      5.00%     95.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            39735013      3.27%     98.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            11052402      0.91%     99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             2038744      0.17%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              599482      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           354010440     29.40%     29.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           362491598     30.10%     59.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           234089313     19.44%     78.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           140647652     11.68%     90.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            60236623      5.00%     95.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            39446291      3.28%     98.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            10873538      0.90%     99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1896665      0.16%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              602948      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1214415274                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1204295068                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  457362     15.66%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     15.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2260297     77.38%     93.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                203472      6.97%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  400252     14.21%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     14.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2198563     78.06%     92.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                217598      7.73%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass          46812177      2.62%      2.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1065743062     59.74%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            478833230     26.84%     89.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           192549010     10.79%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass          46812295      2.64%      2.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1058825283     59.68%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                18980      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   398      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            476287231     26.85%     89.17% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192188407     10.83%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1783937479                       # Type of FU issued
-system.cpu.iq.rate                           1.468531                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2921131                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001637                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4785482838                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2366447244                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1724674774                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 415                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               2104                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          108                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1740046229                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     204                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        210002024                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1774132594                       # Type of FU issued
+system.cpu.iq.rate                           1.472719                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2816413                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001587                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4755521042                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2315690389                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1716753140                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 379                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1840                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           92                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1730136533                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     179                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        210301951                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    112888130                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        39196                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       182689                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     31095664                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    106238837                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        40588                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       180694                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     28431061                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2343                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            45                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2329                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            64                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               61633124                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1215598                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                109803                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1994081974                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts          63261504                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             531930252                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            219281722                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 80                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  53150                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  2875                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         182689                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        2045744                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect     24472235                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             26517979                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1766179614                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             474605200                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          17757865                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               58039825                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1222123                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                102210                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1968663834                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          63066910                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             525280959                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            216617119                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 88                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  49147                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  2813                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         180694                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1387767                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     24439207                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             25826974                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1757694663                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             472697091                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          16437931                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    666327456                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                110355440                       # Number of branches executed
-system.cpu.iew.exec_stores                  191722256                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.453913                       # Inst execution rate
-system.cpu.iew.wb_sent                     1725787981                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1724674882                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1267085899                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1828860280                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    664152329                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                110147604                       # Number of branches executed
+system.cpu.iew.exec_stores                  191455238                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.459074                       # Inst execution rate
+system.cpu.iew.wb_sent                     1717478326                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1716753232                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1259860051                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1819503625                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.419747                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.692828                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.425088                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.692420                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       372589426                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       347171319                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              49                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          26388224                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1152782150                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.406592                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.830218                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          25699242                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1146255243                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.414601                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.834752                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    418160632     36.27%     36.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    415035897     36.00%     72.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     86967576      7.54%     79.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    122159323     10.60%     90.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     24161943      2.10%     92.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     25351733      2.20%     94.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     16436685      1.43%     96.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     12048526      1.05%     97.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     32459835      2.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    413178457     36.05%     36.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    412793718     36.01%     72.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     87651437      7.65%     79.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    122127525     10.65%     90.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     23936453      2.09%     92.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     25493357      2.22%     94.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     16343741      1.43%     96.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     12104723      1.06%     97.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     32625832      2.85%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1152782150                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1146255243                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            880025277                       # Number of instructions committed
 system.cpu.commit.committedOps             1621493927                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -424,196 +424,196 @@ system.cpu.commit.membars                           0                       # Nu
 system.cpu.commit.branches                  107161574                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1621354439                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              32459835                       # number cycles where commit BW limit reached
+system.cpu.commit.function_calls              1061692                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              32625832                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3114405668                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4049835519                       # The number of ROB writes
-system.cpu.timesIdled                           58880                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          361355                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3082294657                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3995391584                       # The number of ROB writes
+system.cpu.timesIdled                           60284                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          369627                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   880025277                       # Number of Instructions Simulated
 system.cpu.committedOps                    1621493927                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             880025277                       # Number of Instructions Simulated
-system.cpu.cpi                               1.380388                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.380388                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.724434                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.724434                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3542838094                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1974489722                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       108                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               910800153                       # number of misc regfile reads
+system.cpu.cpi                               1.368898                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.368898                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.730515                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.730515                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3534938952                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1966276795                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        92                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               906122047                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                     25                       # number of replacements
-system.cpu.icache.tagsinuse                816.521748                       # Cycle average of tags in use
-system.cpu.icache.total_refs                188127242                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    922                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               204042.561822                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                     34                       # number of replacements
+system.cpu.icache.tagsinuse                799.517991                       # Cycle average of tags in use
+system.cpu.icache.total_refs                184596362                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    919                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               200866.552775                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     816.521748                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.398692                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.398692                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    188127247                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       188127247                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     188127247                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        188127247                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    188127247                       # number of overall hits
-system.cpu.icache.overall_hits::total       188127247                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1391                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1391                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1391                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1391                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1391                       # number of overall misses
-system.cpu.icache.overall_misses::total          1391                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     66285000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     66285000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     66285000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     66285000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     66285000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     66285000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    188128638                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    188128638                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    188128638                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    188128638                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    188128638                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    188128638                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     799.517991                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.390390                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.390390                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    184596362                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       184596362                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     184596362                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        184596362                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    184596362                       # number of overall hits
+system.cpu.icache.overall_hits::total       184596362                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1352                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1352                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1352                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1352                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1352                       # number of overall misses
+system.cpu.icache.overall_misses::total          1352                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     65001000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     65001000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     65001000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     65001000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     65001000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     65001000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    184597714                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    184597714                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    184597714                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    184597714                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    184597714                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    184597714                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000007                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000007                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000007                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000007                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000007                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000007                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47652.767793                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 47652.767793                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 47652.767793                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 47652.767793                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 47652.767793                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 47652.767793                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          175                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48077.662722                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 48077.662722                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48077.662722                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 48077.662722                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48077.662722                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 48077.662722                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          237                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           35                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    59.250000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          463                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          463                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          463                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          463                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          463                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          463                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          928                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          928                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          928                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          928                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          928                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          928                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     48200500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     48200500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     48200500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     48200500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     48200500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     48200500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          430                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          430                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          430                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          430                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          430                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          430                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          922                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          922                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          922                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          922                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          922                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          922                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     47826000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     47826000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     47826000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     47826000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     47826000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     47826000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51940.193966                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51940.193966                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51940.193966                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51940.193966                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51940.193966                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51940.193966                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51872.017354                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51872.017354                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51872.017354                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51872.017354                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51872.017354                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51872.017354                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                  2555                       # number of replacements
-system.cpu.l2cache.tagsinuse             22257.251564                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  531421                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 24192                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 21.966807                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                  2557                       # number of replacements
+system.cpu.l2cache.tagsinuse             22244.474628                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  531898                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 24190                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 21.988342                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20781.354031                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    799.332721                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    676.564812                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.634197                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.024394                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.020647                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.679237                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       199286                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         199303                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       429059                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       429059                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            6                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            6                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       224456                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       224456                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       423742                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          423759                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       423742                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         423759                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          905                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         4557                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         5462                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        21899                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        21899                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          905                       # number of demand (read+write) misses
+system.cpu.l2cache.occ_blocks::writebacks 20784.853808                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    785.459531                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    674.161290                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.634303                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.023970                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.020574                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.678847                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           24                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       199349                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         199373                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       429005                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       429005                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       224425                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       224425                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           24                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       423774                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          423798                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           24                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       423774                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         423798                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          895                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         4556                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         5451                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        21900                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        21900                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          895                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data        26456                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         27361                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          905                       # number of overall misses
+system.cpu.l2cache.demand_misses::total         27351                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          895                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        26456                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        27361                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     47084000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    330436000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    377520000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1133219500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1133219500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     47084000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1463655500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1510739500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     47084000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1463655500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1510739500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          922                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       203843                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       204765                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       429059                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       429059                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            6                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            6                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246355                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246355                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          922                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       450198                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       451120                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          922                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       450198                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       451120                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.981562                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022355                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.026674                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.088892                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.088892                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.981562                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.058765                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.060651                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.981562                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.058765                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.060651                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52026.519337                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72511.740180                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69117.539363                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51747.545550                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51747.545550                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52026.519337                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55324.141972                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 55215.068894                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52026.519337                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55324.141972                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 55215.068894                       # average overall miss latency
+system.cpu.l2cache.overall_misses::total        27351                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     46652500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    330531500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    377184000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1131448000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1131448000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     46652500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1461979500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1508632000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     46652500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1461979500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1508632000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          919                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       203905                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       204824                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       429005                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       429005                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       246325                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       246325                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          919                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       450230                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       451149                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          919                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       450230                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       451149                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.973885                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022344                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.026613                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.088907                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.088907                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.973885                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.058761                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.060625                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.973885                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.058761                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060625                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52125.698324                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72548.617208                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69195.376995                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51664.292237                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51664.292237                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52125.698324                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55260.791503                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 55158.202625                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52125.698324                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55260.791503                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 55158.202625                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -622,160 +622,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks         2533                       # number of writebacks
-system.cpu.l2cache.writebacks::total             2533                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          905                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4557                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         5462                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21899                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        21899                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          905                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.writebacks::writebacks         2535                       # number of writebacks
+system.cpu.l2cache.writebacks::total             2535                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          895                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4556                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         5451                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21900                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        21900                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          895                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        26456                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        27361                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          905                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        27351                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          895                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        26456                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        27361                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     35849736                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    273446014                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    309295750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    860917120                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    860917120                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     35849736                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1134363134                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1170212870                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     35849736                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1134363134                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1170212870                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.981562                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022355                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.026674                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.088892                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.088892                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.981562                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058765                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060651                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.981562                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058765                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060651                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39612.967956                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60005.708580                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56626.830831                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39313.079136                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39313.079136                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39612.967956                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42877.348579                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42769.375023                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39612.967956                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42877.348579                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42769.375023                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::total        27351                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     35533995                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    273547521                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    309081516                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    859327626                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    859327626                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     35533995                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1132875147                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1168409142                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     35533995                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1132875147                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1168409142                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.973885                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022344                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.026613                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.088907                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.088907                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.973885                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058761                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060625                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.973885                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058761                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060625                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39702.787709                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60041.159131                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56701.800771                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39238.704384                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39238.704384                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39702.787709                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42821.104740                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42719.064824                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39702.787709                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42821.104740                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42719.064824                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 446101                       # number of replacements
-system.cpu.dcache.tagsinuse               4092.714287                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                452328275                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 450197                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                1004.734094                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              861652000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4092.714287                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999198                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999198                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    264388646                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       264388646                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    187939623                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      187939623                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     452328269                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        452328269                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    452328269                       # number of overall hits
-system.cpu.dcache.overall_hits::total       452328269                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       211237                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        211237                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       246435                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       246435                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       457672                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         457672                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       457672                       # number of overall misses
-system.cpu.dcache.overall_misses::total        457672                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   3022054000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   3022054000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4117738500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4117738500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7139792500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7139792500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7139792500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7139792500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    264599883                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    264599883                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                 446134                       # number of replacements
+system.cpu.dcache.tagsinuse               4092.678697                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                450120039                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 450230                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 999.755767                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              862286000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4092.678697                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999189                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999189                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    262180372                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       262180372                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    187939664                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      187939664                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     450120036                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        450120036                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    450120036                       # number of overall hits
+system.cpu.dcache.overall_hits::total       450120036                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       211406                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        211406                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       246394                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       246394                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       457800                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         457800                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       457800                       # number of overall misses
+system.cpu.dcache.overall_misses::total        457800                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   3024053500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   3024053500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4115325499                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4115325499                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7139378999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7139378999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7139378999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7139378999                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    262391778                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    262391778                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    188186058                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    188186058                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    452785941                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    452785941                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    452785941                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    452785941                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000798                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000798                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001310                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001310                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.001011                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.001011                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.001011                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.001011                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.461463                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.461463                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16709.227585                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16709.227585                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15600.238817                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15600.238817                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15600.238817                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15600.238817                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          388                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    450577836                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    450577836                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    450577836                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    450577836                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000806                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000806                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001309                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001309                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.001016                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.001016                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.001016                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.001016                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14304.482843                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14304.482843                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16702.214741                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16702.214741                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15594.973785                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15594.973785                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15594.973785                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15594.973785                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          342                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                43                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.023256                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.953488                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       429059                       # number of writebacks
-system.cpu.dcache.writebacks::total            429059                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         7389                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         7389                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           79                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           79                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7468                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7468                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7468                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7468                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       203848                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       203848                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       246356                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       246356                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       450204                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       450204                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       450204                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       450204                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2529010500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2529010500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3624235500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   3624235500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6153246000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6153246000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6153246000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6153246000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000770                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000770                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       429005                       # number of writebacks
+system.cpu.dcache.writebacks::total            429005                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         7496                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         7496                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           71                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           71                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7567                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7567                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7567                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7567                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       203910                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       203910                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       246323                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       246323                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       450233                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       450233                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       450233                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       450233                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2529393000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2529393000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3622096999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3622096999                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6151489999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6151489999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6151489999                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6151489999                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000777                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000777                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001309                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.001309                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000994                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000994                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000994                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000994                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12406.354244                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12406.354244                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14711.375002                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14711.375002                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13667.683983                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13667.683983                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13667.683983                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13667.683983                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000999                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000999                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000999                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000999                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12404.457849                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12404.457849                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14704.664197                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14704.664197                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13662.903428                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13662.903428                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13662.903428                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13662.903428                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index da1003d0f26123f9f348e030b2e86fdab59914d8..8d09ee0165b895ab9a363616e45f28cc4f9a163d 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.963993                       # Nu
 sim_ticks                                963992672000                       # Number of ticks simulated
 final_tick                               963992672000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 595979                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1098124                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              652844357                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 283988                       # Number of bytes of host memory used
-host_seconds                                  1476.60                       # Real time elapsed on the host
+host_inst_rate                                 988845                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1822001                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1083195788                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 286888                       # Number of bytes of host memory used
+host_seconds                                   889.95                       # Real time elapsed on the host
 sim_insts                                   880025278                       # Number of instructions simulated
 sim_ops                                    1621493928                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst        9492133560                       # Number of bytes read from this memory
@@ -41,7 +41,7 @@ system.cpu.committedInsts                   880025278                       # Nu
 system.cpu.committedOps                    1621493928                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1621354440                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     2123381                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     99478856                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1621354440                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index 2279afb6565393192290a744dc98384a31e8bee9..441f669b6e6863b938ff5f32c8beaabe2db2a4d4 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  1.800193                       # Nu
 sim_ticks                                1800193398000                       # Number of ticks simulated
 final_tick                               1800193398000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 392596                       # Simulator instruction rate (inst/s)
-host_op_rate                                   723379                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              803099848                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292568                       # Number of bytes of host memory used
-host_seconds                                  2241.56                       # Real time elapsed on the host
+host_inst_rate                                 510604                       # Simulator instruction rate (inst/s)
+host_op_rate                                   940816                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1044499940                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295340                       # Number of bytes of host memory used
+host_seconds                                  1723.50                       # Real time elapsed on the host
 sim_insts                                   880025278                       # Number of instructions simulated
 sim_ops                                    1621493928                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             46208                       # Number of bytes read from this memory
@@ -42,7 +42,7 @@ system.cpu.committedInsts                   880025278                       # Nu
 system.cpu.committedOps                    1621493928                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1621354440                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     2123381                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     99478856                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1621354440                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index 2c4cdb31eb31a083e3e489629e4e2cc2cdc9fa64..5ca506819c8a3cbd2ca837f5d28d6d5285699700 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.066016                       # Number of seconds simulated
-sim_ticks                                 66015916000                       # Number of ticks simulated
-final_tick                                66015916000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.064955                       # Number of seconds simulated
+sim_ticks                                 64955437500                       # Number of ticks simulated
+final_tick                                64955437500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  35889                       # Simulator instruction rate (inst/s)
-host_op_rate                                    63194                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               14996247                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 431068                       # Number of bytes of host memory used
-host_seconds                                  4402.16                       # Real time elapsed on the host
+host_inst_rate                                  70718                       # Simulator instruction rate (inst/s)
+host_op_rate                                   124523                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               29075113                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 434544                       # Number of bytes of host memory used
+host_seconds                                  2234.06                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             64832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1882688                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1947520                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        64832                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           64832                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        10816                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             10816                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1013                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29417                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30430                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             169                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  169                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               982066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             28518698                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                29500765                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          982066                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             982066                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            163839                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 163839                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            163839                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              982066                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            28518698                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               29664604                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30432                       # Total number of read requests seen
-system.physmem.writeReqs                          169                       # Total number of write requests seen
-system.physmem.cpureqs                          30602                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                      1947520                       # Total number of bytes read from memory
-system.physmem.bytesWritten                     10816                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                1947520                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr                  10816                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                       57                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                  1                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                  1931                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                  1906                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                  1971                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                  1959                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                  1883                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                  1865                       # Track reads on a per bank basis
+system.physmem.bytes_read::cpu.inst             64064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1882496                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1946560                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        64064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           64064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        10432                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             10432                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1001                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29414                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30415                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             163                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  163                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               986276                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             28981346                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                29967622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          986276                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             986276                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            160602                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 160602                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            160602                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              986276                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            28981346                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               30128224                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30415                       # Total number of read requests seen
+system.physmem.writeReqs                          163                       # Total number of write requests seen
+system.physmem.cpureqs                          30578                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                      1946560                       # Total number of bytes read from memory
+system.physmem.bytesWritten                     10432                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd                1946560                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr                  10432                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                       40                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                  1928                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                  1903                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                  1919                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                  1928                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                  1935                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                  1899                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::6                  1928                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                  1952                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                  1930                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                  1938                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                 1871                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                  1949                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                  1933                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                  1946                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                 1870                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::11                 1874                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                 1844                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                 1894                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                 1830                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                 1799                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                     7                       # Track writes on a per bank basis
+system.physmem.perBankRdReqs::12                 1848                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13                 1890                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                 1827                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                 1798                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                    61                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                    46                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                    14                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                     7                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                    63                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                    50                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::6                     2                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                     7                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                     4                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::8                     3                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                     1                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                    5                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                    11                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                    6                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::11                    6                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                    3                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                   14                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                    4                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                    7                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                     66015903000                       # Total gap between requests
+system.physmem.totGap                     64955401000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                   30432                       # Categorize read packet sizes
+system.physmem.readPktSize::6                   30415                       # Categorize read packet sizes
 system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                    169                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                     29838                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       404                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        98                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        28                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    163                       # Categorize write packet sizes
+system.physmem.rdQLenPdf::0                     29875                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       392                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        17                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -126,12 +126,12 @@ system.physmem.rdQLenPdf::30                        0                       # Wh
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                         8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::8                         7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::9                         7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                        7                       # What write queue length does an incoming req see
@@ -156,266 +156,266 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.totQLat                       14883000                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                 612849250                       # Sum of mem lat for all requests
+system.physmem.totQLat                       11278750                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat                 610070000                       # Sum of mem lat for all requests
 system.physmem.totBusLat                    151875000                       # Total cycles spent in databus access
-system.physmem.totBankLat                   446091250                       # Total cycles spent in bank access
-system.physmem.avgQLat                         489.98                       # Average queueing delay per request
-system.physmem.avgBankLat                    14686.13                       # Average bank access latency per request
+system.physmem.totBankLat                   446916250                       # Total cycles spent in bank access
+system.physmem.avgQLat                         371.32                       # Average queueing delay per request
+system.physmem.avgBankLat                    14713.29                       # Average bank access latency per request
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  20176.11                       # Average memory access latency
-system.physmem.avgRdBW                          29.50                       # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat                  20084.61                       # Average memory access latency
+system.physmem.avgRdBW                          29.97                       # Average achieved read bandwidth in MB/s
 system.physmem.avgWrBW                           0.16                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                  29.50                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW                  29.97                       # Average consumed read bandwidth in MB/s
 system.physmem.avgConsumedWrBW                   0.16                       # Average consumed write bandwidth in MB/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.24                       # Data bus utilization in percentage
 system.physmem.avgRdQLen                         0.01                       # Average read queue length over time
-system.physmem.avgWrQLen                        12.99                       # Average write queue length over time
-system.physmem.readRowHits                      29112                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                        92                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   95.84                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  54.44                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2157311.95                       # Average gap between requests
-system.cpu.branchPred.lookups                34543649                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          34543649                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            911313                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24748799                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                24648647                       # Number of BTB hits
+system.physmem.avgWrQLen                         9.38                       # Average write queue length over time
+system.physmem.readRowHits                      29086                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                        90                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   95.76                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  55.21                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2124252.76                       # Average gap between requests
+system.cpu.branchPred.lookups                33861369                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          33861369                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            775033                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             19294803                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                19205281                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.595326                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.536031                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 5016068                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               5449                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        132031833                       # number of cpu cycles simulated
+system.cpu.numCycles                        129910880                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           26608466                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      185598145                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    34543649                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24648647                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      56505869                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6118180                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               43668483                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   28                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           168                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  25960165                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                191907                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          131953761                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.484443                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.326412                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           26135643                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      182272269                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    33861369                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24221349                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      55463274                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5355481                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               43685508                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   41                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           275                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  25577909                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                166501                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          129829944                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.475075                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.321063                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 77999092     59.11%     59.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1996445      1.51%     60.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2954879      2.24%     62.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3924320      2.97%     65.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7795201      5.91%     71.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4757326      3.61%     75.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2733781      2.07%     77.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1559430      1.18%     78.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 28233287     21.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 76844002     59.19%     59.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1961117      1.51%     60.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2942078      2.27%     62.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3835155      2.95%     65.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7767567      5.98%     71.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4757667      3.66%     75.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2666355      2.05%     77.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1316617      1.01%     78.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 27739386     21.37%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            131953761                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.261631                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.405708                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 37450717                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              35919295                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  44755686                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               8657316                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5170747                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              324590135                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                5170747                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 43008680                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8572089                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           9131                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  47592423                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              27600691                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              320189266                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   214                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  52468                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              25750177                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              365                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           322200191                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             849206572                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        849204881                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              1691                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            129829944                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.260651                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.403056                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 36820018                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              35912600                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  43886713                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8665410                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4545203                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              318850210                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                4545203                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42299380                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8565943                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           6540                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  46769687                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              27643191                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              315014600                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   177                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  37506                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              25780031                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              461                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           317193496                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             836529852                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        836528510                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              1342                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 42987444                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                470                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            464                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  62325140                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            102538299                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            35256894                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          39591249                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          6019659                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  315840251                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1684                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 302185420                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            114738                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        37013163                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     54220323                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1239                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     131953761                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.290086                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.700741                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 37980749                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                473                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            470                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  62475342                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            101554999                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            34779465                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          39658435                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5856370                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  311474506                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1648                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 300268759                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             90582                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        32704656                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     46105854                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1203                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     129829944                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.312785                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.693578                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            24578254     18.63%     18.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            23242336     17.61%     36.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25887812     19.62%     55.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            25783281     19.54%     75.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            18948095     14.36%     89.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             8310182      6.30%     96.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             4120126      3.12%     99.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              915829      0.69%     99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              167846      0.13%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            23157142     17.84%     17.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            23146978     17.83%     35.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25463277     19.61%     55.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            25807307     19.88%     75.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            18888431     14.55%     89.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8277018      6.38%     96.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3970528      3.06%     99.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              942780      0.73%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              176483      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       131953761                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       129829944                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   38358      1.96%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1827997     93.47%     95.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                 89360      4.57%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   31372      1.52%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1915002     93.02%     94.54% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                112311      5.46%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             31281      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             171162971     56.64%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  27      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.65% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             97754962     32.35%     89.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            33236179     11.00%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             31277      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             169830588     56.56%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11175      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   333      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             97304104     32.41%     88.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            33091251     11.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              302185420                       # Type of FU issued
-system.cpu.iq.rate                           2.288732                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1955715                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006472                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          738394566                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         352887317                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    299540345                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 488                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                781                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          144                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              304109629                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     225                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         54010503                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              300268759                       # Type of FU issued
+system.cpu.iq.rate                           2.311344                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2058685                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006856                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          732516269                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         344212556                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    298017233                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 460                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                646                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          145                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              302295951                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     216                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         54147980                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     11758914                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        26738                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        33947                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      3817142                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     10775614                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        30228                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        33222                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3339713                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3224                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          8519                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3234                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          8606                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5170747                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1767696                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                159609                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           315841935                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            195500                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             102538299                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             35256894                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                4545203                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1761176                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                160180                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           311476154                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            195955                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             101554999                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             34779465                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                465                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3164                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 73504                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          33947                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         522441                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       446022                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               968463                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             300565656                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              97285754                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1619764                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                   3219                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 73682                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          33222                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         393210                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       428039                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               821249                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             298868187                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              96891593                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1400572                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    130302195                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 30889184                       # Number of branches executed
-system.cpu.iew.exec_stores                   33016441                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.276464                       # Inst execution rate
-system.cpu.iew.wb_sent                      299955561                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     299540489                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 219513821                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 298021184                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    129818447                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 30819793                       # Number of branches executed
+system.cpu.iew.exec_stores                   32926854                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.300563                       # Inst execution rate
+system.cpu.iew.wb_sent                      298386144                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     298017378                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 218312526                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 296857185                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.268699                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.736571                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.294014                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.735413                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        37662479                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        33296720                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            911334                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    126783014                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.194241                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.965349                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            775062                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    125284741                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.220482                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.978635                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     58216104     45.92%     45.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     19275036     15.20%     61.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     11824840      9.33%     70.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9597612      7.57%     78.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1736989      1.37%     79.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2070795      1.63%     81.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1302129      1.03%     82.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       715865      0.56%     82.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22043644     17.39%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     57056182     45.54%     45.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     19092863     15.24%     60.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     11627505      9.28%     70.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9458661      7.55%     77.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1851635      1.48%     79.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2083324      1.66%     80.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1287468      1.03%     81.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       696184      0.56%     82.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22130919     17.66%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    126783014                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    125284741                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -425,199 +425,193 @@ system.cpu.commit.membars                           0                       # Nu
 system.cpu.commit.branches                   29309705                       # Number of branches committed
 system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 278186174                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              22043644                       # number cycles where commit BW limit reached
+system.cpu.commit.function_calls              4237596                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              22130919                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    420594313                       # The number of ROB reads
-system.cpu.rob.rob_writes                   636885752                       # The number of ROB writes
-system.cpu.timesIdled                           13744                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           78072                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    414643006                       # The number of ROB reads
+system.cpu.rob.rob_writes                   627527392                       # The number of ROB writes
+system.cpu.timesIdled                           13814                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           80936                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             157988547                       # Number of Instructions Simulated
-system.cpu.cpi                               0.835705                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.835705                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.196594                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.196594                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                592843050                       # number of integer regfile reads
-system.cpu.int_regfile_writes               300182545                       # number of integer regfile writes
+system.cpu.cpi                               0.822280                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.822280                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.216130                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.216130                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                590791400                       # number of integer regfile reads
+system.cpu.int_regfile_writes               298595306                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       134                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       63                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               192703630                       # number of misc regfile reads
+system.cpu.fp_regfile_writes                       70                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               191828831                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                     61                       # number of replacements
-system.cpu.icache.tagsinuse                834.489266                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 25958820                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   1031                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               25178.292919                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                820.655975                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 25576619                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1018                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               25124.380157                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     834.489266                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.407465                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.407465                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     25958820                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25958820                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25958820                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25958820                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25958820                       # number of overall hits
-system.cpu.icache.overall_hits::total        25958820                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1345                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1345                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1345                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1345                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1345                       # number of overall misses
-system.cpu.icache.overall_misses::total          1345                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     65418500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     65418500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     65418500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     65418500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     65418500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     65418500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25960165                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25960165                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25960165                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25960165                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25960165                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25960165                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48638.289963                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48638.289963                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48638.289963                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48638.289963                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48638.289963                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48638.289963                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          133                       # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst     820.655975                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.400711                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.400711                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     25576619                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25576619                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25576619                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25576619                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25576619                       # number of overall hits
+system.cpu.icache.overall_hits::total        25576619                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1290                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1290                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1290                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1290                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1290                       # number of overall misses
+system.cpu.icache.overall_misses::total          1290                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     64574500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     64574500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     64574500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     64574500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     64574500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     64574500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25577909                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25577909                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25577909                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25577909                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25577909                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25577909                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000050                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000050                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000050                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000050                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000050                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000050                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50057.751938                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 50057.751938                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 50057.751938                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 50057.751938                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 50057.751938                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 50057.751938                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs           35                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    26.600000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           35                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          313                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          313                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          313                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          313                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          313                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          313                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1032                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1032                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1032                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1032                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1032                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1032                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51534000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     51534000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51534000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     51534000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51534000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     51534000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          272                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          272                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          272                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          272                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          272                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          272                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1018                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1018                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1018                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1018                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1018                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1018                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     52495000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     52495000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     52495000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     52495000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     52495000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     52495000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49936.046512                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49936.046512                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49936.046512                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 49936.046512                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49936.046512                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 49936.046512                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51566.797642                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51566.797642                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51566.797642                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 51566.797642                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51566.797642                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 51566.797642                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                   480                       # number of replacements
-system.cpu.l2cache.tagsinuse             20799.286466                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 4028524                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 30409                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                132.478016                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                   476                       # number of replacements
+system.cpu.l2cache.tagsinuse             20892.456285                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 4029594                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 30400                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                132.552434                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 19864.428387                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    688.567964                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    246.290114                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.606214                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.021013                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.007516                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.634744                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst           18                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1993506                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1993524                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2066214                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2066214                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        53254                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        53254                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           18                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2046760                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2046778                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           18                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2046760                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2046778                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1013                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          420                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1433                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        28999                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        28999                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1013                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29419                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30432                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1013                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29419                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30432                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     50314000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     20518000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     70832000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1223231500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1223231500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     50314000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1243749500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1294063500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     50314000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1243749500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1294063500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         1031                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1993926                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1994957                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2066214                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2066214                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        82253                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        82253                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1031                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2076179                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2077210                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1031                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2076179                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2077210                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.982541                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000211                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000718                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352559                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.352559                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.982541                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014170                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014650                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982541                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014170                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014650                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49668.311945                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 48852.380952                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 49429.169574                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42181.851098                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42181.851098                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49668.311945                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42277.082838                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 42523.117114                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49668.311945                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42277.082838                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 42523.117114                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 19980.495233                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    670.175654                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    241.785398                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.609756                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.020452                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.007379                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.637587                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1993856                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1993873                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2066867                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2066867                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        53312                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        53312                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2047168                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2047185                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2047168                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2047185                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1001                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          414                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1415                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        29000                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        29000                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1001                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        29414                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         30415                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1001                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        29414                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        30415                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     51299000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21301500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     72600500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1218397500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1218397500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     51299000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1239699000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1290998000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     51299000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1239699000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1290998000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1018                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1994270                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1995288                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2066867                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2066867                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        82312                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        82312                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1018                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2076582                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2077600                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1018                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2076582                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2077600                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.983301                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000208                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000709                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352318                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.352318                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.983301                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014165                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014639                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.983301                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014165                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014639                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51247.752248                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 51452.898551                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51307.773852                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42013.706897                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42013.706897                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51247.752248                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42146.562861                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 42446.095676                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51247.752248                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42146.562861                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 42446.095676                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -626,168 +620,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          169                       # number of writebacks
-system.cpu.l2cache.writebacks::total              169                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1013                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          420                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1433                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28999                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        28999                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1013                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29419                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30432                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1013                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29419                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30432                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     37747309                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     15318354                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     53065663                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        10001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    865494962                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    865494962                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     37747309                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    880813316                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    918560625                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     37747309                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    880813316                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    918560625                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.982541                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000211                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000718                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352559                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352559                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.982541                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014170                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014650                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982541                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014170                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014650                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37262.891412                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36472.271429                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37031.167481                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29845.683024                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29845.683024                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37262.891412                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29940.287433                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30184.037362                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37262.891412                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29940.287433                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30184.037362                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks          163                       # number of writebacks
+system.cpu.l2cache.writebacks::total              163                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1001                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          414                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1415                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29000                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        29000                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1001                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29414                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30415                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1001                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29414                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30415                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38886556                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     16149852                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     55036408                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    860635717                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    860635717                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38886556                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    876785569                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    915672125                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38886556                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    876785569                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    915672125                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.983301                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000208                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000709                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352318                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352318                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.983301                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014165                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014639                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.983301                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014165                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.014639                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38847.708292                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39009.304348                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38894.987986                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 29677.093690                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 29677.093690                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38847.708292                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 29808.443904                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30105.938682                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38847.708292                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29808.443904                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30105.938682                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2072080                       # number of replacements
-system.cpu.dcache.tagsinuse               4072.471065                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 71944468                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2076176                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  34.652394                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            21165048000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4072.471065                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.994256                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.994256                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     40602724                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        40602724                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31341737                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31341737                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      71944461                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         71944461                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     71944461                       # number of overall hits
-system.cpu.dcache.overall_hits::total        71944461                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2627186                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2627186                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        98015                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        98015                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2725201                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2725201                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2725201                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2725201                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  31333887000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31333887000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2111359499                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2111359499                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  33445246499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  33445246499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  33445246499                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  33445246499                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     43229910                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     43229910                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2072485                       # number of replacements
+system.cpu.dcache.tagsinuse               4072.522671                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 71414123                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2076581                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  34.390242                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            20537505000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4072.522671                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994268                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994268                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     40072419                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        40072419                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31341704                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31341704                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      71414123                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         71414123                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     71414123                       # number of overall hits
+system.cpu.dcache.overall_hits::total        71414123                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2626925                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2626925                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        98048                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        98048                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2724973                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2724973                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2724973                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2724973                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31341587500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31341587500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2106729496                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2106729496                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  33448316996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  33448316996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  33448316996                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  33448316996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     42699344                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     42699344                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     74669662                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     74669662                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     74669662                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     74669662                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060772                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.060772                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003118                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.003118                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036497                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036497                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036497                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036497                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11926.786684                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11926.786684                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21541.187563                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21541.187563                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12272.579710                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12272.579710                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12272.579710                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12272.579710                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        32228                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     74139096                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     74139096                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     74139096                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     74139096                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061521                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.061521                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003119                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.003119                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036755                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036755                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036755                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036755                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.903052                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.903052                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21486.715649                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21486.715649                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.733363                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12274.733363                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.733363                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12274.733363                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32679                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              9462                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              9497                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     3.406045                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     3.440981                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066214                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066214                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       633159                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       633159                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        15862                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        15862                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       649021                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       649021                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       649021                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       649021                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994027                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994027                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82153                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82153                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076180                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076180                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076180                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076180                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21983040000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  21983040000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1837362499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1837362499                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23820402499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23820402499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23820402499                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  23820402499                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046126                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046126                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002613                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002613                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027805                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.027805                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027805                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027805                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.444504                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.444504                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22365.129685                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22365.129685                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11473.187536                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11473.187536                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11473.187536                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11473.187536                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2066867                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066867                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       632543                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       632543                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        15848                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        15848                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       648391                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       648391                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       648391                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       648391                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994382                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994382                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82200                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82200                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076582                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076582                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076582                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076582                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21987816500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21987816500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1833120496                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1833120496                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23820936996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23820936996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23820936996                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  23820936996                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046708                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046708                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002615                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002615                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028009                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028009                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028009                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028009                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.877130                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.877130                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22300.735961                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22300.735961                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.223865                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.223865                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.223865                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.223865                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index f4ab1803f54cc8acada4e3dcc28e50d9414f9a22..19252022ff9a23846949afc8cdd911574b527e45 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.168950                       # Nu
 sim_ticks                                168950040000                       # Number of ticks simulated
 final_tick                               168950040000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 540700                       # Simulator instruction rate (inst/s)
-host_op_rate                                   952086                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              578214744                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 420252                       # Number of bytes of host memory used
-host_seconds                                   292.19                       # Real time elapsed on the host
+host_inst_rate                                 992711                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1748005                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1061587108                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 424044                       # Number of bytes of host memory used
+host_seconds                                   159.15                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst        1741569312                       # Number of bytes read from this memory
@@ -41,7 +41,7 @@ system.cpu.committedInsts                   157988548                       # Nu
 system.cpu.committedOps                     278192465                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             278186175                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     8475189                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     18628007                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    278186175                       # number of integer instructions
 system.cpu.num_fp_insts                            40                       # number of float instructions
index ac797fce6aea39041c29ec092c6c8831dcac0a55..f8e97e7f1874ca4aa64bb309feeb617b6cffbcec 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.365989                       # Nu
 sim_ticks                                365989065000                       # Number of ticks simulated
 final_tick                               365989065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 284823                       # Simulator instruction rate (inst/s)
-host_op_rate                                   501527                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              659807143                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 428704                       # Number of bytes of host memory used
-host_seconds                                   554.69                       # Real time elapsed on the host
+host_inst_rate                                 466388                       # Simulator instruction rate (inst/s)
+host_op_rate                                   821234                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1080412484                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 431468                       # Number of bytes of host memory used
+host_seconds                                   338.75                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             51392                       # Number of bytes read from this memory
@@ -42,7 +42,7 @@ system.cpu.committedInsts                   157988548                       # Nu
 system.cpu.committedOps                     278192465                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             278186175                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     8475189                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     18628007                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    278186175                       # number of integer instructions
 system.cpu.num_fp_insts                            40                       # number of float instructions
index 97c2e1466543ee4c6247d8550b07fca60e33117b..2c49dab7402b05b4afe83b139fd4bdbdd63a8e4a 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.434544                       # Number of seconds simulated
-sim_ticks                                434543595000                       # Number of ticks simulated
-final_tick                               434543595000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.451833                       # Number of seconds simulated
+sim_ticks                                451832922000                       # Number of ticks simulated
+final_tick                               451832922000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65471                       # Simulator instruction rate (inst/s)
-host_op_rate                                   121063                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               34406418                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 403752                       # Number of bytes of host memory used
-host_seconds                                 12629.72                       # Real time elapsed on the host
+host_inst_rate                                  67045                       # Simulator instruction rate (inst/s)
+host_op_rate                                   123974                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               36635806                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390776                       # Number of bytes of host memory used
+host_seconds                                 12333.10                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            207168                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24469184                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24676352                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       207168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          207168                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18791424                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18791424                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3237                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             382331                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                385568                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293616                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293616                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               476748                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             56310079                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                56786827                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          476748                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             476748                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          43244048                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               43244048                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          43244048                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              476748                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            56310079                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              100030875                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        385570                       # Total number of read requests seen
-system.physmem.writeReqs                       293616                       # Total number of write requests seen
-system.physmem.cpureqs                         889416                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                     24676352                       # Total number of bytes read from memory
-system.physmem.bytesWritten                  18791424                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd               24676352                       # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr               18791424                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                      147                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite             210200                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                 23300                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                 24510                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                 23756                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                 22591                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                 23592                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                 24765                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                 24384                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                 24225                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                 24541                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                 24693                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                24144                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                24284                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                24592                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                23476                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                24665                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                23905                       # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0                 17803                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1                 18814                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2                 18269                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3                 17556                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4                 18028                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5                 18647                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6                 18328                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7                 18330                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8                 18773                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9                 18765                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10                18401                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11                18543                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12                18573                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13                17879                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14                18800                       # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15                18107                       # Track writes on a per bank basis
+system.physmem.bytes_read::cpu.inst            202816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24482112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24684928                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18794304                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18794304                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3169                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             382533                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                385702                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293661                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293661                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               448874                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             54183993                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                54632867                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          448874                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             448874                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          41595694                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               41595694                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          41595694                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              448874                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            54183993                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               96228561                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        385702                       # Total number of read requests seen
+system.physmem.writeReqs                       293661                       # Total number of write requests seen
+system.physmem.cpureqs                         815428                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                     24684928                       # Total number of bytes read from memory
+system.physmem.bytesWritten                  18794304                       # Total number of bytes written to memory
+system.physmem.bytesConsumedRd               24684928                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr               18794304                       # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ                      138                       # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite             136028                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                 23108                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                 24460                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                 23977                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                 22639                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                 23451                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                 24452                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                 24479                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                 24189                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                 24310                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                 25055                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                24328                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11                24340                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12                24467                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13                23420                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                24898                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                23991                       # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0                 17770                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1                 18792                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2                 18332                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3                 17557                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4                 18019                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5                 18441                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6                 18303                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7                 18298                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8                 18726                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9                 19016                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10                18442                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11                18563                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12                18552                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13                17871                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14                18864                       # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15                18115                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry                          30                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                    434543578000                       # Total gap between requests
+system.physmem.numWrRetry                          37                       # Number of times wr buffer was full causing retry
+system.physmem.totGap                    451832896000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                  385570                       # Categorize read packet sizes
+system.physmem.readPktSize::6                  385702                       # Categorize read packet sizes
 system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
-system.physmem.writePktSize::6                 293616                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                    380658                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4312                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       385                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        60                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293661                       # Categorize write packet sizes
+system.physmem.rdQLenPdf::0                    380831                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4356                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       329                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        44                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -124,300 +124,299 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     12705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     12716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     12716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     12716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     12720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     12725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     12730                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     12733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     12735                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    12766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    12765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    12765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                     12709                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                     12717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                     12719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                     12722                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                     12722                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                     12723                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                     12725                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                     12728                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                     12729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                     12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    12768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    12767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    12767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    12767                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       51                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       46                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       41                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       31                       # What write queue length does an incoming req see
-system.physmem.totQLat                     3416691250                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat               12001501250                       # Sum of mem lat for all requests
-system.physmem.totBusLat                   1927115000                       # Total cycles spent in databus access
-system.physmem.totBankLat                  6657695000                       # Total cycles spent in bank access
-system.physmem.avgQLat                        8864.78                       # Average queueing delay per request
-system.physmem.avgBankLat                    17273.74                       # Average bank access latency per request
+system.physmem.wrQLenPdf::28                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       39                       # What write queue length does an incoming req see
+system.physmem.totQLat                     3445991500                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat               12040169000                       # Sum of mem lat for all requests
+system.physmem.totBusLat                   1927820000                       # Total cycles spent in databus access
+system.physmem.totBankLat                  6666357500                       # Total cycles spent in bank access
+system.physmem.avgQLat                        8937.53                       # Average queueing delay per request
+system.physmem.avgBankLat                    17289.89                       # Average bank access latency per request
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  31138.52                       # Average memory access latency
-system.physmem.avgRdBW                          56.79                       # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW                          43.24                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                  56.79                       # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW                  43.24                       # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat                  31227.42                       # Average memory access latency
+system.physmem.avgRdBW                          54.63                       # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW                          41.60                       # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW                  54.63                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW                  41.60                       # Average consumed write bandwidth in MB/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.78                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.75                       # Data bus utilization in percentage
 system.physmem.avgRdQLen                         0.03                       # Average read queue length over time
-system.physmem.avgWrQLen                         9.11                       # Average write queue length over time
-system.physmem.readRowHits                     331804                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    191849                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   86.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  65.34                       # Row buffer hit rate for writes
-system.physmem.avgGap                       639800.55                       # Average gap between requests
-system.cpu.branchPred.lookups               214941297                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         214941297                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          13134170                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            150507127                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               147849168                       # Number of BTB hits
+system.physmem.avgWrQLen                         8.94                       # Average write queue length over time
+system.physmem.readRowHits                     331871                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    191829                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   86.07                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  65.32                       # Row buffer hit rate for writes
+system.physmem.avgGap                       665083.17                       # Average gap between requests
+system.cpu.branchPred.lookups               205621718                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         205621718                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           9907083                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            117077740                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               114695478                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.233998                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.965231                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25073647                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1800250                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        869087191                       # number of cpu cycles simulated
+system.cpu.numCycles                        903825131                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          180529479                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1193576474                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   214941297                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          147849168                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     371266839                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                83403229                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              231605654                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                31859                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        315081                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           80                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 173437780                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               3837204                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          853761597                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.595537                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.389460                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          167418043                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1132282338                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   205621718                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          139769125                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     352430400                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                71153000                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              297148174                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                48797                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        255592                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           33                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 162064992                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2572532                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          878293133                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.398381                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.331165                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                486899007     57.03%     57.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 24703220      2.89%     59.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 27351293      3.20%     63.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 28808692      3.37%     66.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 18472602      2.16%     68.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 24587756      2.88%     71.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 30665646      3.59%     75.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 28871909      3.38%     78.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                183401472     21.48%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                529920988     60.34%     60.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 23389932      2.66%     63.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 25306191      2.88%     65.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 27947555      3.18%     69.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 17765128      2.02%     71.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 22905202      2.61%     73.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 29375609      3.34%     77.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 26663527      3.04%     80.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                175019001     19.93%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            853761597                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.247318                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.373368                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                236998203                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             188180276                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 313422880                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              45147633                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               70012605                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2166855434                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                     2                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               70012605                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                270389606                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                53986414                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          16429                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 322684460                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             136672083                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2120106693                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 31519                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               21337249                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             101081597                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               78                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2216557030                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5356293513                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       5356152135                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            141378                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            878293133                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.227502                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.252767                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                222360951                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             252528998                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 295744531                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              46666559                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               60992094                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2071948592                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               60992094                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                255743691                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               109858014                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          17204                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 306968990                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             144713140                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2035757004                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 14813                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               25048489                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             104458594                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              180                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2138803025                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5151932301                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       5151817228                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            115073                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                602516176                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1382                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1352                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 330488922                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            512705517                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           204907925                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         196340700                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         55518293                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2033906543                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               22903                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1808080301                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            844129                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       499423460                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    818593930                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          22351                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     853761597                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.117781                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.887022                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                524762171                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1163                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1096                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 344343454                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            496005535                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           194479256                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         195803959                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         55147463                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1975947809                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               16072                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1772430246                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            489293                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       442088890                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    735772933                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          15520                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     878293133                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.018040                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.884895                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           233333722     27.33%     27.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           145354336     17.03%     44.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           138354387     16.21%     60.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           133038603     15.58%     76.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            96103978     11.26%     87.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            58771252      6.88%     94.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            34916322      4.09%     98.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            11980698      1.40%     99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1908299      0.22%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           263200988     29.97%     29.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           149900664     17.07%     47.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           137095286     15.61%     62.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           132054982     15.04%     77.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            91669420     10.44%     88.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            56193413      6.40%     94.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            34492530      3.93%     98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            11912661      1.36%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1773189      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       853761597                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       878293133                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 4978338     32.41%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7792932     50.73%     83.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2590948     16.87%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 4998230     32.74%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7655755     50.14%     82.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2613853     17.12%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2717915      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1190782663     65.86%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            438926011     24.28%     90.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           175653712      9.71%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2627910      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1165981895     65.78%     65.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               352516      0.02%     65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3880818      0.22%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            429341212     24.22%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170245895      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1808080301                       # Type of FU issued
-system.cpu.iq.rate                           2.080436                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    15362218                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008496                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4486103997                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2533565590                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1768588128                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               24549                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              46362                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         5401                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1820713311                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   11293                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        170590285                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1772430246                       # Type of FU issued
+system.cpu.iq.rate                           1.961032                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    15267838                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008614                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4438895750                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2418277528                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1745063548                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               15006                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              33162                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         3630                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1785062995                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    7179                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        172239839                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    128603360                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       477781                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       270908                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     55748152                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    111903378                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       383433                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       329474                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     45320259                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        12303                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           614                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        14682                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           568                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               70012605                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                16361207                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2863228                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2033929446                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2371289                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             512705517                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            204908338                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6072                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1817776                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 76759                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         270908                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        9111612                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4490464                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             13602076                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1780387317                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             431399251                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          27692984                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               60992094                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                64075051                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               7111223                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1975963881                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            801543                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             496005535                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            194480445                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               3509                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                4460880                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 83569                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         329474                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5903386                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4417104                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10320490                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1753197001                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             424204757                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          19233245                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    602062000                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                169264678                       # Number of branches executed
-system.cpu.iew.exec_stores                  170662749                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.048572                       # Inst execution rate
-system.cpu.iew.wb_sent                     1775274937                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1768593529                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1341496349                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1964252976                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    591004689                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                167488871                       # Number of branches executed
+system.cpu.iew.exec_stores                  166799932                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.939752                       # Inst execution rate
+system.cpu.iew.wb_sent                     1749947599                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1745067178                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1326505641                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1948512890                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.035001                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.682955                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.930758                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.680778                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       504973387                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       447002783                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          13165974                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    783748992                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.950865                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.458310                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9936450                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    817301039                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.870778                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.444599                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    290412107     37.05%     37.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    195557118     24.95%     62.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     62107499      7.92%     69.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     92255388     11.77%     81.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     25035287      3.19%     84.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     28388589      3.62%     88.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9410992      1.20%     89.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     10755720      1.37%     91.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     69826292      8.91%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    326881530     40.00%     40.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    191845418     23.47%     63.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     62847977      7.69%     71.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     92272413     11.29%     82.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     25036529      3.06%     85.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27653799      3.38%     88.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9274477      1.13%     90.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11343051      1.39%     91.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     70145845      8.58%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    783748992                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    817301039                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -427,205 +426,205 @@ system.cpu.commit.membars                           0                       # Nu
 system.cpu.commit.branches                  149758583                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1528317561                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              69826292                       # number cycles where commit BW limit reached
+system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events              70145845                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2747884788                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4138119354                       # The number of ROB writes
-system.cpu.timesIdled                          343577                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        15325594                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2723146678                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4013137574                       # The number of ROB writes
+system.cpu.timesIdled                         3358951                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        25531998                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
-system.cpu.cpi                               1.051048                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.051048                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.951432                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.951432                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3357192668                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1848351672                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      5396                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        7                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               980175338                       # number of misc regfile reads
+system.cpu.cpi                               1.093059                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.093059                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.914864                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.914864                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3313860690                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1826087017                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      3611                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       20                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               964797382                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.icache.replacements                   5459                       # number of replacements
-system.cpu.icache.tagsinuse               1031.272902                       # Cycle average of tags in use
-system.cpu.icache.total_refs                173201219                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   7046                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               24581.495742                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   5491                       # number of replacements
+system.cpu.icache.tagsinuse               1036.603099                       # Cycle average of tags in use
+system.cpu.icache.total_refs                161916606                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   7071                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               22898.685617                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1031.272902                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.503551                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.503551                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    173216530                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       173216530                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     173216530                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        173216530                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    173216530                       # number of overall hits
-system.cpu.icache.overall_hits::total       173216530                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       221250                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        221250                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       221250                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         221250                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       221250                       # number of overall misses
-system.cpu.icache.overall_misses::total        221250                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1405122498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1405122498                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1405122498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1405122498                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1405122498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1405122498                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    173437780                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    173437780                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    173437780                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    173437780                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    173437780                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    173437780                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001276                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001276                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001276                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001276                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001276                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001276                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6350.836149                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6350.836149                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6350.836149                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6350.836149                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6350.836149                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6350.836149                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          511                       # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst    1036.603099                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.506154                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.506154                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    161918575                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       161918575                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     161918575                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        161918575                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    161918575                       # number of overall hits
+system.cpu.icache.overall_hits::total       161918575                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       146417                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        146417                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       146417                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         146417                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       146417                       # number of overall misses
+system.cpu.icache.overall_misses::total        146417                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    875142000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    875142000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    875142000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    875142000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    875142000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    875142000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    162064992                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    162064992                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    162064992                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    162064992                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    162064992                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    162064992                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000903                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000903                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000903                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000903                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000903                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000903                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  5977.051845                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  5977.051845                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  5977.051845                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  5977.051845                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  5977.051845                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  5977.051845                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1375                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    34.066667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   229.166667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2445                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2445                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2445                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2445                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2445                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2445                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       218805                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       218805                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       218805                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       218805                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       218805                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       218805                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    886299999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    886299999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    886299999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    886299999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    886299999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    886299999                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001262                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001262                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001262                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001262                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001262                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001262                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4050.638692                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4050.638692                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4050.638692                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  4050.638692                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4050.638692                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  4050.638692                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1845                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1845                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1845                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1845                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1845                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1845                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       144572                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       144572                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       144572                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       144572                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       144572                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       144572                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    521583500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    521583500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    521583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    521583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    521583500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    521583500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000892                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000892                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000892                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000892                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000892                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000892                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3607.776748                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3607.776748                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3607.776748                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  3607.776748                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3607.776748                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  3607.776748                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                352890                       # number of replacements
-system.cpu.l2cache.tagsinuse             29622.917064                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3697451                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                385249                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  9.597562                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          202056635000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21050.647644                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    232.691985                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   8339.577435                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.642415                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.007101                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.254504                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.904020                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3783                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1586610                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1590393                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2331126                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2331126                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1528                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1528                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       564574                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       564574                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3783                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2151184                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2154967                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3783                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2151184                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2154967                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3238                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       175600                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       178838                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       210169                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       210169                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206764                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206764                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3238                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       382364                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        385602                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3238                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       382364                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       385602                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    198244000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  10115005954                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  10313249954                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      7282500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      7282500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10370858500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10370858500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    198244000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  20485864454                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  20684108454                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    198244000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  20485864454                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  20684108454                       # number of overall miss cycles
+system.cpu.l2cache.replacements                353019                       # number of replacements
+system.cpu.l2cache.tagsinuse             29665.542211                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3698954                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                385379                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  9.598224                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          196543776500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 21121.895278                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    226.041869                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   8317.605064                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.644589                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.006898                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.253833                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.905321                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3851                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1587691                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1591542                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2331818                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2331818                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1456                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1456                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       565593                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       565593                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3851                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2153284                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2157135                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3851                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2153284                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2157135                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3170                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       175625                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       178795                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       135999                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       135999                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206937                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206937                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3170                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       382562                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        385732                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3170                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       382562                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       385732                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    197656000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  10096367454                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  10294023454                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6513500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total      6513500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10430438500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10430438500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    197656000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  20526805954                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20724461954                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    197656000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  20526805954                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20724461954                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         7021                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1762210                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1769231                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2331126                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2331126                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       211697                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       211697                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       771338                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       771338                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1763316                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1770337                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2331818                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2331818                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       137455                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       137455                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       772530                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       772530                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst         7021                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2533548                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2540569                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2535846                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2542867                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst         7021                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2533548                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2540569                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.461188                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099648                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.101082                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.992782                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.992782                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268059                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.268059                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461188                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.150920                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151778                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461188                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.150920                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151778                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61224.212477                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57602.539601                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 57668.112784                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    34.650686                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    34.650686                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50157.950610                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50157.950610                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61224.212477                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53576.865118                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 53641.081877                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61224.212477                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53576.865118                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 53641.081877                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::cpu.data      2535846                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2542867                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.451503                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099599                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.100995                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989407                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989407                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.267869                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.267869                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.451503                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.150862                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151692                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.451503                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.150862                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151692                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62352.050473                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57488.213261                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 57574.448133                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    47.893735                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    47.893735                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50403.932115                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50403.932115                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62352.050473                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53656.154961                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 53727.619057                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62352.050473                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53656.154961                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 53727.619057                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -634,168 +633,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       293616                       # number of writebacks
-system.cpu.l2cache.writebacks::total           293616                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3238                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175600                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       178838                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       210169                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       210169                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206764                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206764                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3238                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       382364                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       385602                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3238                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       382364                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       385602                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    158016497                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   7941834689                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   8099851186                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2107112859                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2107112859                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7783948782                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7783948782                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    158016497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15725783471                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  15883799968                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    158016497                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15725783471                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  15883799968                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.461188                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099648                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101082                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.992782                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.992782                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268059                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268059                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461188                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150920                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151778                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461188                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150920                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151778                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48800.647622                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45226.849026                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45291.555408                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.802373                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.802373                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.537995                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.537995                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48800.647622                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.782613                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41192.213650                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48800.647622                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.782613                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41192.213650                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       293661                       # number of writebacks
+system.cpu.l2cache.writebacks::total           293661                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3170                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175625                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       178795                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       135999                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       135999                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206937                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206937                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3170                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       382562                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       385732                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3170                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       382562                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       385732                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    158250747                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   7922707780                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   8080958527                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1364143324                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1364143324                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7842004636                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7842004636                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    158250747                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15764712416                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  15922963163                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    158250747                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15764712416                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  15922963163                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.451503                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099599                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.100995                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989407                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989407                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.267869                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.267869                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.451503                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150862                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151692                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.451503                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150862                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151692                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49921.371293                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45111.503374                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45196.781381                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.539372                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.539372                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37895.613815                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37895.613815                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49921.371293                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41208.254913                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41279.860533                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49921.371293                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41208.254913                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41279.860533                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2529450                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.791832                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                405306727                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2533546                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 159.976068                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             1794502000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.791832                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997996                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997996                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    256575503                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       256575503                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148160629                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148160629                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     404736132                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        404736132                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    404736132                       # number of overall hits
-system.cpu.dcache.overall_hits::total       404736132                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2890458                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2890458                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       999573                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       999573                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3890031                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3890031                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3890031                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3890031                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  51324442500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  51324442500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  23758155000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  23758155000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  75082597500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  75082597500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  75082597500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  75082597500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    259465961                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    259465961                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2531750                       # number of replacements
+system.cpu.dcache.tagsinuse               4088.641557                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                396440107                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2535846                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 156.334457                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             1679431000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4088.641557                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.998204                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.998204                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    247707841                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       247707841                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148233543                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148233543                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     395941384                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        395941384                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    395941384                       # number of overall hits
+system.cpu.dcache.overall_hits::total       395941384                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2871315                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2871315                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       926659                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       926659                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3797974                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3797974                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3797974                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3797974                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  51373394500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  51373394500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21994238500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21994238500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  73367633000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  73367633000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  73367633000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  73367633000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250579156                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250579156                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    408626163                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    408626163                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    408626163                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    408626163                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011140                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011140                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006701                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006701                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009520                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009520                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009520                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009520                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17756.508657                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17756.508657                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23768.304066                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 23768.304066                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19301.285131                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19301.285131                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19301.285131                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19301.285131                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         6798                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    399739358                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    399739358                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    399739358                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    399739358                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011459                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011459                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006213                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006213                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009501                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009501                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009501                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009501                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.939582                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.939582                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23734.986117                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 23734.986117                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19317.571158                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19317.571158                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19317.571158                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19317.571158                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         6008                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               655                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               680                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.378626                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.835294                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2331126                       # number of writebacks
-system.cpu.dcache.writebacks::total           2331126                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1127945                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1127945                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16844                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16844                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1144789                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1144789                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1144789                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1144789                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762513                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1762513                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       982729                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       982729                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2745242                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2745242                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2745242                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2745242                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27781259000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27781259000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  21592303500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  21592303500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  49373562500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  49373562500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  49373562500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  49373562500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006793                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006793                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006588                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006588                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006718                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006718                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006718                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006718                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15762.300193                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15762.300193                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21971.778079                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21971.778079                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17985.140290                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17985.140290                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17985.140290                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17985.140290                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2331818                       # number of writebacks
+system.cpu.dcache.writebacks::total           2331818                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1107712                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1107712                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16962                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16962                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1124674                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1124674                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1124674                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1124674                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1763603                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1763603                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       909697                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       909697                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2673300                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2673300                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2673300                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2673300                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27774523500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27774523500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19972622500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19972622500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47747146000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  47747146000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47747146000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  47747146000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007038                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007038                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006099                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006099                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006688                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006688                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006688                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006688                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15748.739087                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15748.739087                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21955.247187                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21955.247187                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17860.751132                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17860.751132                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17860.751132                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17860.751132                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index cadafb39e273850308b82dc110965ead8c0f1d4f..6867203d830f9fd806507a9f7ad91eb3f7765851 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.885229                       # Nu
 sim_ticks                                885229328000                       # Number of ticks simulated
 final_tick                               885229328000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 607816                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1123920                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              650709398                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293412                       # Number of bytes of host memory used
-host_seconds                                  1360.41                       # Real time elapsed on the host
+host_inst_rate                                1006678                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1861461                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1077718973                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296180                       # Number of bytes of host memory used
+host_seconds                                   821.39                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst        8546776520                       # Number of bytes read from this memory
@@ -41,7 +41,7 @@ system.cpu.committedInsts                   826877110                       # Nu
 system.cpu.committedOps                    1528988702                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1528317562                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    35346287                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     92658795                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1528317562                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index c3c3c690946af8ad9d21bd7cdfa97a29e74bf765..7c0f3a039526c8baab6ee7c271c27d748c26f074 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  1.647873                       # Nu
 sim_ticks                                1647872849000                       # Number of ticks simulated
 final_tick                               1647872849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 379189                       # Simulator instruction rate (inst/s)
-host_op_rate                                   701163                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              755680972                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300836                       # Number of bytes of host memory used
-host_seconds                                  2180.65                       # Real time elapsed on the host
+host_inst_rate                                 533286                       # Simulator instruction rate (inst/s)
+host_op_rate                                   986105                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1062778196                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304632                       # Number of bytes of host memory used
+host_seconds                                  1550.53                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            120704                       # Number of bytes read from this memory
@@ -42,7 +42,7 @@ system.cpu.committedInsts                   826877110                       # Nu
 system.cpu.committedOps                    1528988702                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1528317562                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    35346287                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     92658795                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   1528317562                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index 7cb3ea1a2e6efd1bac56fc289a1cb05e29c62b7f..545751e4106565569de5c26fde282d0007fd8a53 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  2.846007                       # Nu
 sim_ticks                                2846007227500                       # Number of ticks simulated
 final_tick                               2846007227500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 922936                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1438019                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              873209138                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 283960                       # Number of bytes of host memory used
-host_seconds                                  3259.25                       # Real time elapsed on the host
+host_inst_rate                                1114602                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1736651                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1054547884                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 286860                       # Number of bytes of host memory used
+host_seconds                                  2698.79                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst       32105863056                       # Number of bytes read from this memory
@@ -41,7 +41,7 @@ system.cpu.committedInsts                  3008081022                       # Nu
 system.cpu.committedOps                    4686862596                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            4686862527                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    33534539                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts    182173300                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   4686862527                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index 914311460551bf409495e6ed0b2b0f31478d8df1..225f011f68314d8b9c9170a0ef9dc0345d1c6499 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  5.882581                       # Nu
 sim_ticks                                5882580526000                       # Number of ticks simulated
 final_tick                               5882580526000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 579739                       # Simulator instruction rate (inst/s)
-host_op_rate                                   903286                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1133733281                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 291512                       # Number of bytes of host memory used
-host_seconds                                  5188.68                       # Real time elapsed on the host
+host_inst_rate                                 548624                       # Simulator instruction rate (inst/s)
+host_op_rate                                   854806                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1072884756                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295308                       # Number of bytes of host memory used
+host_seconds                                  5482.96                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
@@ -42,7 +42,7 @@ system.cpu.committedInsts                  3008081022                       # Nu
 system.cpu.committedOps                    4686862596                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            4686862527                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                    33534539                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts    182173300                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                   4686862527                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index fbc39fbabc7781ee118bbd62da75757a8db3ad96..682644ea738a516de6276e6ae4bd6954b3dbe855 100644 (file)
@@ -1,57 +1,57 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.082784                       # Number of seconds simulated
-sim_ticks                                 82784332500                       # Number of ticks simulated
-final_tick                                82784332500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.144599                       # Number of seconds simulated
+sim_ticks                                144599413000                       # Number of ticks simulated
+final_tick                               144599413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  28862                       # Simulator instruction rate (inst/s)
-host_op_rate                                    48376                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               18091276                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 321848                       # Number of bytes of host memory used
-host_seconds                                  4575.93                       # Real time elapsed on the host
+host_inst_rate                                  53694                       # Simulator instruction rate (inst/s)
+host_op_rate                                    89995                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               58787129                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 325332                       # Number of bytes of host memory used
+host_seconds                                  2459.71                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221362962                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            217728                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            124352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               342080                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       217728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          217728                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3402                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1943                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5345                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2630063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1502120                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4132183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2630063                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2630063                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2630063                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1502120                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4132183                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5347                       # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst            217792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            125312                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               343104                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       217792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          217792                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3403                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1958                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5361                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1506175                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               866615                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2372790                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1506175                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1506175                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1506175                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              866615                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2372790                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5365                       # Total number of read requests seen
 system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                           5510                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                       342080                       # Total number of bytes read from memory
+system.physmem.cpureqs                           5519                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                       343104                       # Total number of bytes read from memory
 system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                 342080                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd                 343104                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
 system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite                163                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                   274                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1                   289                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                   321                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                   273                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                   309                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                   370                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                   377                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                   378                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                   366                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9                   376                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                  367                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                  353                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                  356                       # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite                154                       # Reqs where no action is needed
+system.physmem.perBankRdReqs::0                   279                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1                   290                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                   322                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                   281                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                   310                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                   374                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                   370                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                   382                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                   374                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9                   377                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                  361                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11                  349                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12                  366                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::13                  337                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                  353                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                  248                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                  344                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                  249                       # Track reads on a per bank basis
 system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14                    0                       # Tr
 system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                     82784303000                       # Total gap between requests
+system.physmem.totGap                    144599380000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                    5347                       # Categorize read packet sizes
+system.physmem.readPktSize::6                    5365                       # Categorize read packet sizes
 system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
@@ -85,12 +85,12 @@ system.physmem.writePktSize::3                      0                       # Ca
 system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                      4168                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       927                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       202                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        42                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4242                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       901                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       182                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        35                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -149,267 +149,267 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.totQLat                       15985000                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                 132177500                       # Sum of mem lat for all requests
-system.physmem.totBusLat                     26735000                       # Total cycles spent in databus access
-system.physmem.totBankLat                    89457500                       # Total cycles spent in bank access
-system.physmem.avgQLat                        2989.53                       # Average queueing delay per request
-system.physmem.avgBankLat                    16730.41                       # Average bank access latency per request
+system.physmem.totQLat                       15365500                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat                 134288000                       # Sum of mem lat for all requests
+system.physmem.totBusLat                     26825000                       # Total cycles spent in databus access
+system.physmem.totBankLat                    92097500                       # Total cycles spent in bank access
+system.physmem.avgQLat                        2864.03                       # Average queueing delay per request
+system.physmem.avgBankLat                    17166.36                       # Average bank access latency per request
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  24719.94                       # Average memory access latency
-system.physmem.avgRdBW                           4.13                       # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat                  25030.38                       # Average memory access latency
+system.physmem.avgRdBW                           2.37                       # Average achieved read bandwidth in MB/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                   4.13                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW                   2.37                       # Average consumed read bandwidth in MB/s
 system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
+system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
 system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                       4531                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4467                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.74                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.26                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15482383.21                       # Average gap between requests
-system.cpu.branchPred.lookups                19946660                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          19946660                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           2010176                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             13817098                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                13100139                       # Number of BTB hits
+system.physmem.avgGap                     26952354.15                       # Average gap between requests
+system.cpu.branchPred.lookups                18673504                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          18673504                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1493262                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11432454                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                10793701                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.811074                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.412809                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1324082                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              23521                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        165568666                       # number of cpu cycles simulated
+system.cpu.numCycles                        289482612                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           25865179                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      219003921                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    19946660                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           13100139                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      57576020                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                17616732                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               66658067                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  301                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2079                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          100                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  24478210                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                431162                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          165440333                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.186068                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.325239                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           23502455                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      207109778                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    18673504                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           12117783                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      54283022                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                15594841                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              178283916                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 1444                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          8051                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           37                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22396392                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                221801                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          269918552                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.268498                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.756525                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                109457492     66.16%     66.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3058910      1.85%     68.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2395088      1.45%     69.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2913515      1.76%     71.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3447820      2.08%     73.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3570209      2.16%     75.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4310601      2.61%     78.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2725404      1.65%     79.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 33561294     20.29%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                217073469     80.42%     80.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2850604      1.06%     81.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2315423      0.86%     82.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2639736      0.98%     83.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3229574      1.20%     84.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3384900      1.25%     85.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3844403      1.42%     87.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2562175      0.95%     88.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 32018268     11.86%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            165440333                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.120474                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.322738                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 38757375                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              56681760                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  44701919                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9960692                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               15338587                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              353512832                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               15338587                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 46220216                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                14972536                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          23135                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  46536732                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              42349127                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              345185267                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    94                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               18050300                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              22188357                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              104                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           398793355                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             959907307                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        950110032                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           9797275                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            269918552                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.064506                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.715448                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 36985977                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             167209662                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  41646466                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              10236820                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               13839627                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              336463810                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               13839627                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 45047343                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               116751427                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          32413                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  42745141                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              51502601                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              330086802                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 10951                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               26152362                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              22736681                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              256                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           382815435                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             919037508                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        910796649                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           8240859                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259428606                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                139364749                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1689                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1679                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  90442233                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             86625401                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            31763472                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          57799485                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         18862046                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  333525036                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                3363                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 267505666                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            256796                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       111713410                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    229404022                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2118                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     165440333                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.616931                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.504344                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                123386829                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2258                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2296                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 105258591                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             84679198                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            30165066                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          58703856                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         19098571                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  323202869                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4566                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 260671940                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            116724                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       101460757                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    211331898                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3321                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     269918552                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.965743                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.342643                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            45064653     27.24%     27.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            46696636     28.23%     55.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            32890293     19.88%     75.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            19781835     11.96%     87.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            13196196      7.98%     95.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4792802      2.90%     98.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2338024      1.41%     99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              533151      0.32%     99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              146743      0.09%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           143572602     53.19%     53.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            55645964     20.62%     73.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34208859     12.67%     86.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            19077068      7.07%     93.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            10849323      4.02%     97.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4139320      1.53%     99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1825268      0.68%     99.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              469630      0.17%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              130518      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       165440333                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       269918552                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  135867      5.09%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2266939     84.88%     89.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                267901     10.03%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  131441      4.84%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2279294     83.91%     88.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                305503     11.25%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1212144      0.45%      0.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             174223829     65.13%     65.58% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.58% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1597035      0.60%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             67207754     25.12%     91.30% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            23264904      8.70%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1210514      0.46%      0.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             162160673     62.21%     62.67% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               788045      0.30%     62.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7035797      2.70%     65.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1444934      0.55%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             65461399     25.11%     91.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            22570578      8.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              267505666                       # Type of FU issued
-system.cpu.iq.rate                           1.615678                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2670707                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009984                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          698027148                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         440935220                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    260272326                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             5352020                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            4598390                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2575188                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266272654                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2691575                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         19010388                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              260671940                       # Type of FU issued
+system.cpu.iq.rate                           0.900475                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2716238                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010420                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          789209442                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         421320217                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    255304788                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             4885952                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            3632838                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2349442                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              259718878                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2458786                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18858463                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     29975814                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        29182                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       297064                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     11247755                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     28029611                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        25725                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       290431                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      9649349                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        49364                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked             7                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        49573                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            13                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               15338587                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  586618                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                254753                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           333528399                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            189186                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              86625401                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             31763472                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1668                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 142182                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 30086                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         297064                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1176748                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       915608                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              2092356                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             264614762                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              66222036                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2890904                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               13839627                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                84981347                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               5427028                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           323207435                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            136147                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              84679198                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             30165066                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               2231                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                2677235                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 14355                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         290431                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         637937                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       905599                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1543536                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             258899576                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              64693791                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1772364                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     89093330                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14607419                       # Number of branches executed
-system.cpu.iew.exec_stores                   22871294                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.598218                       # Inst execution rate
-system.cpu.iew.wb_sent                      263675320                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     262847514                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 212089133                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 375086159                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     87060323                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14273836                       # Number of branches executed
+system.cpu.iew.exec_stores                   22366532                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.894353                       # Inst execution rate
+system.cpu.iew.wb_sent                      258261406                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     257654230                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 206076672                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 369295783                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.587544                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.565441                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.890051                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.558026                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       112202846                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       101920014                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           2010398                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    150101746                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.474753                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.942108                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1494473                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    256078925                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.864433                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.651734                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     50823152     33.86%     33.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57296396     38.17%     72.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13814368      9.20%     81.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12061169      8.04%     89.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4147019      2.76%     92.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2963443      1.97%     94.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1057939      0.70%     94.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1004682      0.67%     95.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6933578      4.62%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    156603135     61.15%     61.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     57289650     22.37%     83.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     14093127      5.50%     89.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12068952      4.71%     93.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4185763      1.63%     95.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2969218      1.16%     96.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       905577      0.35%     96.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1050426      0.41%     97.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6913077      2.70%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    150101746                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    256078925                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221362962                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -419,201 +419,199 @@ system.cpu.commit.membars                           0                       # Nu
 system.cpu.commit.branches                   12326938                       # Number of branches committed
 system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 220339553                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6933578                       # number cycles where commit BW limit reached
+system.cpu.commit.function_calls               797818                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               6913077                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    476733976                       # The number of ROB reads
-system.cpu.rob.rob_writes                   682504424                       # The number of ROB writes
-system.cpu.timesIdled                            2963                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          128333                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    572448824                       # The number of ROB reads
+system.cpu.rob.rob_writes                   660431667                       # The number of ROB writes
+system.cpu.timesIdled                         5928357                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        19564060                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221362962                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             132071192                       # Number of Instructions Simulated
-system.cpu.cpi                               1.253632                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.253632                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.797682                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.797682                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                562551000                       # number of integer regfile reads
-system.cpu.int_regfile_writes               298759078                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3525668                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2235326                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               137020971                       # number of misc regfile reads
+system.cpu.cpi                               2.191868                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.191868                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.456232                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.456232                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                554310914                       # number of integer regfile reads
+system.cpu.int_regfile_writes               293915019                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3215317                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2009393                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               133439176                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    845                       # number of misc regfile writes
-system.cpu.icache.replacements                   4809                       # number of replacements
-system.cpu.icache.tagsinuse               1620.816173                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 24469178                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   6775                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                3611.686790                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   4633                       # number of replacements
+system.cpu.icache.tagsinuse               1627.424900                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 22387705                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   6601                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                3391.562642                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1620.816173                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.791414                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.791414                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     24469178                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24469178                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      24469178                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         24469178                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     24469178                       # number of overall hits
-system.cpu.icache.overall_hits::total        24469178                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         9032                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          9032                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         9032                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           9032                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         9032                       # number of overall misses
-system.cpu.icache.overall_misses::total          9032                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    270256997                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    270256997                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    270256997                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    270256997                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    270256997                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    270256997                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     24478210                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     24478210                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     24478210                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     24478210                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     24478210                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     24478210                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000369                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000369                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000369                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000369                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000369                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000369                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29922.165301                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29922.165301                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29922.165301                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29922.165301                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29922.165301                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29922.165301                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          940                       # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst    1627.424900                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.794641                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.794641                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     22387705                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22387705                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22387705                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22387705                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22387705                       # number of overall hits
+system.cpu.icache.overall_hits::total        22387705                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8687                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8687                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8687                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8687                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8687                       # number of overall misses
+system.cpu.icache.overall_misses::total          8687                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    264464000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    264464000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    264464000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    264464000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    264464000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    264464000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22396392                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22396392                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22396392                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22396392                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22396392                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22396392                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000388                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000388                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000388                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000388                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000388                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000388                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30443.651433                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 30443.651433                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 30443.651433                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 30443.651433                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 30443.651433                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 30443.651433                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          666                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                27                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                16                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    34.814815                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    41.625000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2092                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2092                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2092                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2092                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2092                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2092                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6940                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         6940                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         6940                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         6940                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         6940                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         6940                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    204869497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    204869497                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    204869497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    204869497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    204869497                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    204869497                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000284                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000284                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000284                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000284                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000284                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000284                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29520.100432                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29520.100432                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29520.100432                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 29520.100432                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29520.100432                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 29520.100432                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1931                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1931                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1931                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1931                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1931                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1931                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6756                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         6756                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         6756                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         6756                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         6756                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         6756                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    203573500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    203573500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    203573500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    203573500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    203573500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    203573500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000302                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000302                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000302                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000302                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000302                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000302                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30132.252812                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30132.252812                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30132.252812                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 30132.252812                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30132.252812                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 30132.252812                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2523.720712                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    3406                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  3795                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.897497                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2558.702101                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    3231                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3835                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.842503                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks     1.566236                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2241.747095                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    280.407381                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.000048                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.068413                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.008557                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.077018                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3374                       # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::writebacks     1.875617                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2246.028041                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    310.798443                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000057                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.068543                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.009485                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.078085                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3198                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           28                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           3402                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           14                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           14                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadReq_hits::total           3226                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            7                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            7                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3374                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         3198                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           35                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            3409                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3374                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            3233                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3198                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           35                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           3409                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3402                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          390                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3792                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          163                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          163                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1555                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1555                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3402                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1945                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5347                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3402                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1945                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5347                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    164029000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     23357500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    187386500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     68438500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     68438500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    164029000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     91796000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    255825000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    164029000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     91796000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    255825000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6776                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          418                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         7194                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           14                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           14                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          164                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          164                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1562                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1562                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6776                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1980                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8756                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6776                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1980                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8756                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.502066                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.933014                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.527106                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.993902                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.993902                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.995519                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.995519                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.502066                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.982323                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.610667                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.502066                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.982323                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.610667                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48215.461493                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59891.025641                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 49416.271097                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44011.897106                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44011.897106                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48215.461493                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47195.886889                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 47844.585749                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48215.461493                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47195.886889                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 47844.585749                       # average overall miss latency
+system.cpu.l2cache.overall_hits::total           3233                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3404                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          430                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3834                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          154                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          154                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1531                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1531                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3404                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1961                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5365                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3404                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1961                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5365                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    164657000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     25864500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    190521500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     67557000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     67557000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    164657000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     93421500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    258078500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    164657000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     93421500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    258078500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         6602                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          458                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         7060                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          154                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          154                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1538                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1538                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6602                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1996                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8598                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6602                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1996                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8598                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.515601                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.938865                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.543059                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.995449                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.995449                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.515601                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.982465                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.623982                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.515601                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.982465                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.623982                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48371.621622                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        60150                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 49692.618675                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44126.061398                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44126.061398                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48371.621622                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47639.724630                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 48104.100652                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48371.621622                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47639.724630                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 48104.100652                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -622,166 +620,166 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3402                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          390                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3792                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          163                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          163                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1555                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1555                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3402                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1945                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5347                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3402                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1945                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5347                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    121826276                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     18549059                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    140375335                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1630163                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1630163                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48802001                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48802001                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    121826276                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     67351060                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    189177336                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    121826276                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     67351060                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    189177336                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.502066                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.933014                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.527106                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.993902                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.993902                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.995519                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.995519                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.502066                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.982323                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.610667                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.502066                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.982323                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.610667                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35810.192828                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47561.689744                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37018.811973                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3404                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          430                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3834                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          154                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          154                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1531                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1531                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3404                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1961                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5365                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3404                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1961                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5365                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    122420067                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     20567586                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    142987653                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1540154                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1540154                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48271230                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48271230                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    122420067                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     68838816                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    191258883                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    122420067                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     68838816                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    191258883                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.515601                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.938865                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.543059                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.995449                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.995449                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.515601                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.982465                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.623982                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.515601                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.982465                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.623982                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35963.591951                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47831.595349                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37294.640845                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31383.923473                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31383.923473                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35810.192828                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34627.794344                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35380.089022                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35810.192828                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34627.794344                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35380.089022                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31529.216199                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31529.216199                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35963.591951                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35103.934727                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35649.372414                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35963.591951                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35103.934727                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35649.372414                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                     56                       # number of replacements
-system.cpu.dcache.tagsinuse               1411.878201                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 67566613                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   1978                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               34159.056117                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                     54                       # number of replacements
+system.cpu.dcache.tagsinuse               1433.982512                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 66194680                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   1993                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               33213.587556                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1411.878201                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.344697                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.344697                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     47052408                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        47052408                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20514004                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20514004                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      67566412                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         67566412                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     67566412                       # number of overall hits
-system.cpu.dcache.overall_hits::total        67566412                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          800                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           800                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1727                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1727                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2527                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2527                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2527                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2527                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     40244500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     40244500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     77286000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     77286000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    117530500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    117530500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    117530500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    117530500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     47053208                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     47053208                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data    1433.982512                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.350093                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.350093                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     45680422                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        45680422                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20514038                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20514038                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      66194460                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         66194460                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     66194460                       # number of overall hits
+system.cpu.dcache.overall_hits::total        66194460                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          872                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           872                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1693                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1693                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2565                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2565                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2565                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2565                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     43604500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     43604500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     76098000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     76098000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    119702500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    119702500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    119702500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    119702500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     45681294                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     45681294                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     67568939                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     67568939                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     67568939                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     67568939                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000017                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000017                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000084                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000084                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000037                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000037                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000037                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000037                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50305.625000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50305.625000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44751.592357                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 44751.592357                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46509.893154                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46509.893154                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46509.893154                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46509.893154                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           35                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     66197025                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     66197025                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     66197025                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     66197025                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000019                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000083                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000083                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000039                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000039                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50005.160550                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50005.160550                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44948.611931                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44948.611931                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46667.641326                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46667.641326                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46667.641326                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46667.641326                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          170                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    17.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    56.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           14                       # number of writebacks
-system.cpu.dcache.writebacks::total                14                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          382                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          382                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
+system.cpu.dcache.writebacks::total                13                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          414                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          414                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data            1                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          383                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          383                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          383                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          383                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          418                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          418                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1726                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1726                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2144                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2144                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2144                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     24060000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     24060000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     73798500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     73798500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     97858500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     97858500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     97858500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     97858500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000084                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data          415                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          415                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          415                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          415                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          458                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          458                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1692                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1692                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2150                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2150                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2150                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2150                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     26607000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     26607000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     72678500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     72678500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     99285500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     99285500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     99285500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     99285500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000082                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000082                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57559.808612                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57559.808612                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42756.952491                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42756.952491                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45642.957090                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45642.957090                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45642.957090                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45642.957090                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58093.886463                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58093.886463                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42954.196217                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42954.196217                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46179.302326                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 46179.302326                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46179.302326                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 46179.302326                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index bb0c7510f332a254b040b0d17c05a502cfb877e6..817f7471eb431f73cf1f21fe39f4e4da34a97d6b 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.131393                       # Nu
 sim_ticks                                131393068000                       # Number of ticks simulated
 final_tick                               131393068000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 538543                       # Simulator instruction rate (inst/s)
-host_op_rate                                   902645                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              535777601                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308992                       # Number of bytes of host memory used
-host_seconds                                   245.24                       # Real time elapsed on the host
+host_inst_rate                                 929815                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1558452                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              925040607                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 311764                       # Number of bytes of host memory used
+host_seconds                                   142.04                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221362963                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst        1387954936                       # Number of bytes read from this memory
@@ -41,7 +41,7 @@ system.cpu.committedInsts                   132071193                       # Nu
 system.cpu.committedOps                     221362963                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             220339554                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     1595632                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts      8268466                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    220339554                       # number of integer instructions
 system.cpu.num_fp_insts                       2162459                       # number of float instructions
index 1372cb624043b745849c691dd2c28e93aec7957d..cfc0b5abb572b35c0fbc2a02acb6eb7f4890bac2 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.250954                       # Nu
 sim_ticks                                250953957000                       # Number of ticks simulated
 final_tick                               250953957000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 308460                       # Simulator instruction rate (inst/s)
-host_op_rate                                   517006                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              586117013                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 316420                       # Number of bytes of host memory used
-host_seconds                                   428.16                       # Real time elapsed on the host
+host_inst_rate                                 507243                       # Simulator instruction rate (inst/s)
+host_op_rate                                   850184                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              963833485                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320216                       # Number of bytes of host memory used
+host_seconds                                   260.37                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221362963                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            181760                       # Number of bytes read from this memory
@@ -35,7 +35,7 @@ system.cpu.committedInsts                   132071193                       # Nu
 system.cpu.committedOps                     221362963                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             220339554                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     1595632                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts      8268466                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    220339554                       # number of integer instructions
 system.cpu.num_fp_insts                       2162459                       # number of float instructions
index c125666afbd910ce44b73b1a762008cde1df940b..81ef154d3df3c018856fe1dc930eb6c7a83d727e 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.112100                       # Number of seconds simulated
-sim_ticks                                5112099861500                       # Number of ticks simulated
-final_tick                               5112099861500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                5112099860500                       # Number of ticks simulated
+final_tick                               5112099860500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1058684                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2167614                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27073251373                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 628224                       # Number of bytes of host memory used
-host_seconds                                   188.82                       # Real time elapsed on the host
+host_inst_rate                                1019592                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2087576                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            26073588986                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 631672                       # Number of bytes of host memory used
+host_seconds                                   196.06                       # Real time elapsed on the host
 sim_insts                                   199905607                       # Number of instructions simulated
-sim_ops                                     409299164                       # Number of ops (including micro ops) simulated
+sim_ops                                     409299132                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide      2420928                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
@@ -194,7 +194,7 @@ system.iocache.tagsinuse                     0.042441                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     47584                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              4994822604059                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              4994822603059                       # Cycle when the warmup percentage was hit.
 system.iocache.occ_blocks::pc.south_bridge.ide     0.042441                       # Average occupied blocks per requestor
 system.iocache.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
 system.iocache.occ_percent::total            0.002653                       # Average percentage of cache occupancy
@@ -245,57 +245,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                      10224199746                       # number of cpu cycles simulated
+system.cpu.numCycles                      10224199744                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   199905607                       # Number of instructions committed
-system.cpu.committedOps                     409299164                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             374462077                       # Number of integer alu accesses
+system.cpu.committedOps                     409299132                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             374462047                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     39972120                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    374462077                       # number of integer instructions
+system.cpu.num_func_calls                     2307315                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     39972114                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    374462047                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           915890450                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          480542967                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           915890300                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          480542889                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
 system.cpu.num_mem_refs                      35654170                       # number of memory refs
 system.cpu.num_load_insts                    27234345                       # Number of load instructions
 system.cpu.num_store_insts                    8419825                       # Number of store instructions
-system.cpu.num_idle_cycles               9770518373.401503                       # Number of idle cycles
-system.cpu.num_busy_cycles               453681372.598497                       # Number of busy cycles
+system.cpu.num_idle_cycles               9770518400.401503                       # Number of idle cycles
+system.cpu.num_busy_cycles               453681343.598497                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.044373                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.955627                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
 system.cpu.icache.replacements                 790584                       # number of replacements
 system.cpu.icache.tagsinuse                510.666660                       # Cycle average of tags in use
-system.cpu.icache.total_refs                243492011                       # Total number of references to valid blocks.
+system.cpu.icache.total_refs                243492014                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                 791096                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 307.790725                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           148824779500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.avg_refs                 307.790728                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle           148824778500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.occ_blocks::cpu.inst     510.666660                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.997396                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.997396                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    243492011                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       243492011                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     243492011                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        243492011                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    243492011                       # number of overall hits
-system.cpu.icache.overall_hits::total       243492011                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    243492014                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       243492014                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     243492014                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        243492014                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    243492014                       # number of overall hits
+system.cpu.icache.overall_hits::total       243492014                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst       791103                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        791103                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst       791103                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         791103                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst       791103                       # number of overall misses
 system.cpu.icache.overall_misses::total        791103                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst    244283114                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244283114                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244283114                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244283114                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244283114                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244283114                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    244283117                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244283117                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244283117                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244283117                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244283117                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244283117                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003238                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.003238                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.003238                       # miss rate for demand accesses
@@ -316,7 +316,7 @@ system.cpu.itb_walker_cache.tagsinuse        3.026333                       # Cy
 system.cpu.itb_walker_cache.total_refs           7886                       # Total number of references to valid blocks.
 system.cpu.itb_walker_cache.sampled_refs         3489                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.avg_refs         2.260246                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5102064746500                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.warmup_cycle 5102064745500                       # Cycle when the warmup percentage was hit.
 system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.026333                       # Average occupied blocks per requestor
 system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.189146                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.occ_percent::total     0.189146                       # Average percentage of cache occupancy
@@ -364,7 +364,7 @@ system.cpu.dtb_walker_cache.tagsinuse        5.014191                       # Cy
 system.cpu.dtb_walker_cache.total_refs          12947                       # Total number of references to valid blocks.
 system.cpu.dtb_walker_cache.sampled_refs         7641                       # Sample count of references to valid blocks.
 system.cpu.dtb_walker_cache.avg_refs         1.694412                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5100425402500                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.warmup_cycle 5100425401500                       # Cycle when the warmup percentage was hit.
 system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.014191                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.313387                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.occ_percent::total     0.313387                       # Average percentage of cache occupancy
@@ -408,22 +408,22 @@ system.cpu.dcache.tagsinuse                511.999425                       # Cy
 system.cpu.dcache.total_refs                 20168705                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1622472                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  12.430849                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle                7550500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle                7549500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.occ_blocks::cpu.data     511.999425                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999999                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     12073184                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        12073184                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8093253                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8093253                       # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     12073185                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        12073185                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8093252                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8093252                       # number of WriteReq hits
 system.cpu.dcache.demand_hits::cpu.data      20166437                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         20166437                       # number of demand (read+write) hits
 system.cpu.dcache.overall_hits::cpu.data     20166437                       # number of overall hits
 system.cpu.dcache.overall_hits::total        20166437                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1308370                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1308370                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       316386                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       316386                       # number of WriteReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      1308369                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1308369                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       316387                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       316387                       # number of WriteReq misses
 system.cpu.dcache.demand_misses::cpu.data      1624756                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        1624756                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1624756                       # number of overall misses
@@ -456,16 +456,16 @@ system.cpu.dcache.writebacks::writebacks      1535700                       # nu
 system.cpu.dcache.writebacks::total           1535700                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                105930                       # number of replacements
-system.cpu.l2cache.tagsinuse             64819.953894                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3456507                       # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse             64819.953901                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3456506                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                170058                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 20.325460                       # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs                 20.325454                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 51906.788142                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 51906.788145                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.dtb.walker     0.004959                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.itb.walker     0.132241                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2490.593014                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  10422.435538                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2490.593013                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  10422.435543                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.792035                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
@@ -475,14 +475,14 @@ system.cpu.l2cache.occ_percent::total        0.989074                       # Av
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6501                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2802                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       777765                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1275492                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2062560                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1275491                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2062559                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      1538639                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total      1538639                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           20                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           20                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       179720                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       179720                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       179721                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       179721                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker         6501                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         2802                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.inst       777765                       # number of demand (read+write) hits
@@ -515,14 +515,14 @@ system.cpu.l2cache.overall_misses::total       179971                       # nu
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6503                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2807                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.inst       791090                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1307738                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2108138                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1307737                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2108137                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks      1538639                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total      1538639                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1823                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total         1823                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       314113                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       314113                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       314114                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       314114                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6503                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         2807                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.inst       791090                       # number of demand (read+write) accesses
@@ -540,8 +540,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.024658
 system.cpu.l2cache.ReadReq_miss_rate::total     0.021620                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989029                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989029                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.427849                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.427849                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.427848                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.427848                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000308                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001781                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016844                       # miss rate for demand accesses
index fe64538c771869aec7e7319248058db35ec264ff..45255855392677d84b4331aada17e39e57ae38fa 100644 (file)
@@ -4,13 +4,13 @@ sim_seconds                                  5.187336                       # Nu
 sim_ticks                                5187335906000                       # Number of ticks simulated
 final_tick                               5187335906000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 632480                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1219228                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25568906299                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 629256                       # Number of bytes of host memory used
-host_seconds                                   202.88                       # Real time elapsed on the host
+host_inst_rate                                 633010                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1220249                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25590316667                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 632708                       # Number of bytes of host memory used
+host_seconds                                   202.71                       # Real time elapsed on the host
 sim_insts                                   128315489                       # Number of instructions simulated
-sim_ops                                     247353050                       # Number of ops (including micro ops) simulated
+sim_ops                                     247353048                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide      2850304                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.inst            824512                       # Number of bytes read from this memory
@@ -293,10 +293,10 @@ system.cpu.numCycles                      10374671812                       # nu
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   128315489                       # Number of instructions committed
-system.cpu.committedOps                     247353050                       # Number of ops (including micro ops) committed
+system.cpu.committedOps                     247353048                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             232087369                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                     2299349                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     23166071                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                    232087369                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index 63a2cacd2aa1011c073575fe653504b484ef19fe..add7e06591f5cc96ee1963f9550da302fc608d95 100644 (file)
@@ -1,57 +1,57 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000015                       # Number of seconds simulated
-sim_ticks                                    15474000                       # Number of ticks simulated
-final_tick                                   15474000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000016                       # Number of seconds simulated
+sim_ticks                                    16021500                       # Number of ticks simulated
+final_tick                                   16021500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  16433                       # Simulator instruction rate (inst/s)
-host_op_rate                                    29770                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47259450                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 286708                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
+host_inst_rate                                  25477                       # Simulator instruction rate (inst/s)
+host_op_rate                                    46153                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75857343                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 290184                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             19392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              9344                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                28736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19392                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                303                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                146                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   449                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1253198914                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            603851622                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1857050536                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1253198914                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1253198914                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1253198914                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           603851622                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1857050536                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           451                       # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              9152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        17792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           17792                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                143                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1110507755                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            571232406                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1681740162                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1110507755                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1110507755                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1110507755                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           571232406                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1681740162                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           422                       # Total number of read requests seen
 system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                            451                       # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead                        28736                       # Total number of bytes read from memory
+system.physmem.cpureqs                            422                       # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead                        26944                       # Total number of bytes read from memory
 system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
-system.physmem.bytesConsumedRd                  28736                       # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd                  26944                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
 system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
-system.physmem.perBankRdReqs::0                    49                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0                    45                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::1                    14                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2                    26                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3                    29                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4                    36                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5                    48                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6                    28                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7                    34                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8                    40                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2                    23                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3                    28                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4                    35                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5                    44                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6                    26                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7                    32                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8                    33                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::9                    24                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10                    8                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11                   32                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12                   41                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13                   11                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14                    5                       # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15                   26                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10                    7                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11                   33                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12                   39                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13                   12                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14                    3                       # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15                   24                       # Track reads on a per bank basis
 system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
 system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14                    0                       # Tr
 system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
 system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
-system.physmem.totGap                        15458000                       # Total gap between requests
+system.physmem.totGap                        16004000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::6                     451                       # Categorize read packet sizes
+system.physmem.readPktSize::6                     422                       # Categorize read packet sizes
 system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
@@ -85,11 +85,11 @@ system.physmem.writePktSize::3                      0                       # Ca
 system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
 system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
-system.physmem.rdQLenPdf::0                       230                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       152                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       233                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       137                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        46                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         6                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -149,266 +149,265 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.totQLat                        1899500                       # Total cycles spent in queuing delays
-system.physmem.totMemAccLat                  13160750                       # Sum of mem lat for all requests
-system.physmem.totBusLat                      2255000                       # Total cycles spent in databus access
-system.physmem.totBankLat                     9006250                       # Total cycles spent in bank access
-system.physmem.avgQLat                        4211.75                       # Average queueing delay per request
-system.physmem.avgBankLat                    19969.51                       # Average bank access latency per request
+system.physmem.totQLat                        2229750                       # Total cycles spent in queuing delays
+system.physmem.totMemAccLat                  13029750                       # Sum of mem lat for all requests
+system.physmem.totBusLat                      2110000                       # Total cycles spent in databus access
+system.physmem.totBankLat                     8690000                       # Total cycles spent in bank access
+system.physmem.avgQLat                        5283.77                       # Average queueing delay per request
+system.physmem.avgBankLat                    20592.42                       # Average bank access latency per request
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
-system.physmem.avgMemAccLat                  29181.26                       # Average memory access latency
-system.physmem.avgRdBW                        1857.05                       # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat                  30876.18                       # Average memory access latency
+system.physmem.avgRdBW                        1681.74                       # Average achieved read bandwidth in MB/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW                1857.05                       # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW                1681.74                       # Average consumed read bandwidth in MB/s
 system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil                          14.51                       # Data bus utilization in percentage
-system.physmem.avgRdQLen                         0.85                       # Average read queue length over time
+system.physmem.busUtil                          13.14                       # Data bus utilization in percentage
+system.physmem.avgRdQLen                         0.81                       # Average read queue length over time
 system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
-system.physmem.readRowHits                        333                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        302                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.84                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   71.56                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        34274.94                       # Average gap between requests
-system.cpu.branchPred.lookups                    2993                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              2993                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               546                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2483                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     793                       # Number of BTB hits
+system.physmem.avgGap                        37924.17                       # Average gap between requests
+system.cpu.branchPred.lookups                    3090                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3090                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               541                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2310                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     714                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             31.937173                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                       0                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  0                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             30.909091                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     211                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 78                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            30949                       # number of cpu cycles simulated
+system.cpu.numCycles                            32044                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8903                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          14396                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2993                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                793                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          3910                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2411                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   3703                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   34                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           178                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                      1874                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   286                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              18564                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.369856                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.872055                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               9523                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14230                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3090                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                925                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3948                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2389                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   3636                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   47                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           340                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      1965                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   259                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              19279                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.312568                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.813131                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    14753     79.47%     79.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      190      1.02%     80.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      153      0.82%     81.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      193      1.04%     82.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      163      0.88%     83.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      168      0.90%     84.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      264      1.42%     85.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      161      0.87%     86.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2519     13.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    15433     80.05%     80.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      214      1.11%     81.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      145      0.75%     81.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      217      1.13%     83.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      192      1.00%     84.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      169      0.88%     84.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      290      1.50%     86.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      155      0.80%     87.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2464     12.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                18564                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.096707                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.465152                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     9437                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3646                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3520                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   143                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1818                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  24283                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1818                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     9780                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    2398                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            497                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3306                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   765                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  22784                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     7                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     39                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   651                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               24893                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 54727                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            54711                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                19279                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.096430                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.444077                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    10008                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  3780                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3579                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   127                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1785                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  24215                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1785                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    10348                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2654                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            416                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3350                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   726                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  22708                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     8                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                     31                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   620                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               25234                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 54863                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            54847                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                 11063                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    13830                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 34                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             34                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2066                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2202                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1748                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores                7                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      20310                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  36                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17272                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               205                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            9822                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        13657                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             24                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         18564                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.930403                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.788380                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                    14171                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 30                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             30                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                      1819                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2277                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1616                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                17                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      20098                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  25                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     17004                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               251                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            9536                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        13688                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         19279                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.881996                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.736426                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               13176     70.98%     70.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1404      7.56%     78.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1053      5.67%     84.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 694      3.74%     87.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 727      3.92%     91.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 623      3.36%     95.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 594      3.20%     98.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 251      1.35%     99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  42      0.23%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               13831     71.74%     71.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1491      7.73%     79.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1108      5.75%     85.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 718      3.72%     88.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 686      3.56%     92.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 589      3.06%     95.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 582      3.02%     98.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 230      1.19%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  44      0.23%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           18564                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           19279                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     132     76.30%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     20     11.56%     87.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    21     12.14%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     127     76.51%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     76.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     24     14.46%     90.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    15      9.04%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 3      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 13885     80.39%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1904     11.02%     91.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1480      8.57%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 13619     80.09%     80.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    4      0.02%     80.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     7      0.04%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1977     11.63%     91.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1394      8.20%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17272                       # Type of FU issued
-system.cpu.iq.rate                           0.558079                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         173                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010016                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              53478                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             30175                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        15918                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  17004                       # Type of FU issued
+system.cpu.iq.rate                           0.530645                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         166                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009762                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              53696                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             29666                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        15641                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  17438                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  17163                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads              159                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads              167                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1149                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses           14                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1224                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses           12                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           12                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          813                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          681                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            13                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            19                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1818                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1705                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    33                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               20346                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                33                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2202                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1748                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 32                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                   1785                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1955                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    34                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               20123                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                54                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2277                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1616                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 25                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                      6                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             12                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             56                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          606                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  662                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16347                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1780                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               925                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            121                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          553                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  674                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16111                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1853                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               893                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3143                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1619                       # Number of branches executed
-system.cpu.iew.exec_stores                       1363                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.528192                       # Inst execution rate
-system.cpu.iew.wb_sent                          16117                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         15922                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10116                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     15624                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3149                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1620                       # Number of branches executed
+system.cpu.iew.exec_stores                       1296                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.502777                       # Inst execution rate
+system.cpu.iew.wb_sent                          15852                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         15645                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10112                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     15481                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.514459                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.647465                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.488235                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.653188                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           10598                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           10375                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               572                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        16746                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.582049                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.457997                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               582                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        17494                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.557162                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.425293                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        13211     78.89%     78.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1328      7.93%     86.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          595      3.55%     90.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          703      4.20%     94.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          355      2.12%     96.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          140      0.84%     97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          119      0.71%     98.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           74      0.44%     98.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          221      1.32%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        13941     79.69%     79.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1339      7.65%     87.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          594      3.40%     90.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          714      4.08%     94.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          361      2.06%     96.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          136      0.78%     97.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          122      0.70%     98.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           74      0.42%     98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          213      1.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        16746                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        17494                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
 system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -418,181 +417,184 @@ system.cpu.commit.membars                           0                       # Nu
 system.cpu.commit.branches                       1208                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                      9654                       # Number of committed integer instructions.
-system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   221                       # number cycles where commit BW limit reached
+system.cpu.commit.function_calls                  106                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events                   213                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        36870                       # The number of ROB reads
-system.cpu.rob.rob_writes                       42537                       # The number of ROB writes
-system.cpu.timesIdled                             155                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           12385                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        37403                       # The number of ROB reads
+system.cpu.rob.rob_writes                       42056                       # The number of ROB writes
+system.cpu.timesIdled                             165                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           12765                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
 system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5380                       # Number of Instructions Simulated
-system.cpu.cpi                               5.752602                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         5.752602                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.173834                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.173834                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    28776                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   17146                       # number of integer regfile writes
+system.cpu.cpi                               5.956134                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         5.956134                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.167894                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.167894                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    28607                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   17139                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                    7131                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    7155                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                144.810143                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1475                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    304                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   4.851974                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                134.419040                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1594                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    279                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   5.713262                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     144.810143                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.070708                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.070708                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1475                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1475                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1475                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1475                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1475                       # number of overall hits
-system.cpu.icache.overall_hits::total            1475                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          399                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           399                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          399                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            399                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          399                       # number of overall misses
-system.cpu.icache.overall_misses::total           399                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     20615000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     20615000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     20615000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     20615000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     20615000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     20615000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1874                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1874                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1874                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1874                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1874                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1874                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.212914                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.212914                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.212914                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.212914                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.212914                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.212914                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51666.666667                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 51666.666667                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 51666.666667                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 51666.666667                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 51666.666667                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 51666.666667                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          312                       # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst     134.419040                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.065634                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.065634                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1594                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1594                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1594                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1594                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1594                       # number of overall hits
+system.cpu.icache.overall_hits::total            1594                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          371                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           371                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          371                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            371                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          371                       # number of overall misses
+system.cpu.icache.overall_misses::total           371                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19224000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19224000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19224000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19224000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19224000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19224000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1965                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1965                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1965                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1965                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1965                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1965                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.188804                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.188804                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.188804                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.188804                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.188804                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.188804                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51816.711590                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 51816.711590                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 51816.711590                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 51816.711590                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 51816.711590                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 51816.711590                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    44.571429                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           95                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           95                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           95                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           95                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           95                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           95                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          304                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          304                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          304                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          304                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          304                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          304                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16157500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16157500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16157500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16157500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16157500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16157500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.162220                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.162220                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.162220                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.162220                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.162220                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.162220                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53149.671053                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53149.671053                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53149.671053                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 53149.671053                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53149.671053                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 53149.671053                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           91                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           91                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           91                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           91                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           91                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           91                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          280                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          280                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          280                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          280                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          280                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          280                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15030000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15030000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15030000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15030000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15030000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15030000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.142494                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.142494                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.142494                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.142494                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.142494                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.142494                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53678.571429                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53678.571429                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53678.571429                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 53678.571429                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53678.571429                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 53678.571429                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               177.966730                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   373                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.002681                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse               167.756635                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   344                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.005814                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    144.947246                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     33.019484                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004423                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001008                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005431                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    134.530220                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     33.226414                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004106                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001014                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005120                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
-system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          303                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           72                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          375                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data           76                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total           76                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          303                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          148                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           451                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          303                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          148                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          451                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15842500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3892500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     19735000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3990500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3990500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     15842500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7883000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     23725500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     15842500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7883000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     23725500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          304                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           72                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          376                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data           76                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           76                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          304                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          148                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          452                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          304                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          148                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          452                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996711                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997340                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          279                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           66                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          345                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           77                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           77                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          279                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          143                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           422                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          279                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          143                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          422                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14740500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3980000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     18720500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4206500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4206500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     14740500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      8186500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     22927000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     14740500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      8186500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     22927000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          280                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           67                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          347                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           77                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           77                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          280                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          144                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          424                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          280                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          144                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          424                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996429                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.985075                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.994236                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996711                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997788                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996711                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997788                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52285.478548                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 52626.666667                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52285.478548                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52606.430155                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52285.478548                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52606.430155                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996429                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.993056                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.995283                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996429                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.993056                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.995283                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52833.333333                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60303.030303                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54262.318841                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54629.870130                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54629.870130                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52833.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57248.251748                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54329.383886                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52833.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57248.251748                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54329.383886                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -601,154 +603,154 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          303                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           72                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          375                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           76                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total           76                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          303                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          451                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          303                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          451                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12091981                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3030041                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15122022                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3057807                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3057807                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12091981                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6087848                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     18179829                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12091981                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6087848                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     18179829                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996711                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997340                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           66                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          345                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           77                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           77                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          279                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          143                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          422                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          279                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          422                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11293716                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3166039                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14459755                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3259559                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3259559                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11293716                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6425598                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17719314                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11293716                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6425598                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17719314                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996429                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.985075                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994236                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996711                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997788                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996711                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997788                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40234.302632                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40234.302632                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41134.108108                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.042129                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41134.108108                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.042129                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996429                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.993056                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.995283                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996429                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.993056                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.995283                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40479.268817                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47970.287879                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41912.333333                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42331.935065                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42331.935065                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40479.268817                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44934.251748                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41988.895735                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40479.268817                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44934.251748                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41988.895735                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 83.491215                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2285                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    146                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  15.650685                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 84.412169                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2338                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    144                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  16.236111                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      83.491215                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020384                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020384                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1426                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1426                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          859                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            859                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2285                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2285                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2285                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2285                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          127                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           127                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          203                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            203                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          203                       # number of overall misses
-system.cpu.dcache.overall_misses::total           203                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      6648000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6648000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      4218500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4218500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     10866500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     10866500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     10866500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     10866500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1553                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1553                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data      84.412169                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020608                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020608                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1480                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1480                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2338                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2338                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2338                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2338                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          136                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           136                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           77                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           77                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          213                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            213                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          213                       # number of overall misses
+system.cpu.dcache.overall_misses::total           213                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      8307000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      8307000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4438000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4438000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     12745000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     12745000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     12745000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     12745000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1616                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1616                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2488                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2488                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2488                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2488                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081777                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.081777                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081283                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.081283                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.081592                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.081592                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.081592                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.081592                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55506.578947                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53529.556650                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53529.556650                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53529.556650                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53529.556650                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          103                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         2551                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2551                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2551                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2551                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.084158                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.084158                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.082353                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.082353                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.083497                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.083497                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.083497                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.083497                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61080.882353                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61080.882353                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57636.363636                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 57636.363636                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59835.680751                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59835.680751                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59835.680751                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59835.680751                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          117                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.600000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    23.400000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           55                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           55                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           55                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           55                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           55                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           55                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           72                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           72                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           76                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           76                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          148                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          148                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          148                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3962500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3962500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4066500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4066500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8029000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      8029000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8029000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      8029000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046362                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046362                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081283                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081283                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059486                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.059486                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.059486                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.059486                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53506.578947                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        54250                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        54250                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        54250                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        54250                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           69                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           69                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           69                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           69                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           69                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           69                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           67                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           67                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           77                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           77                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          144                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          144                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4057000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4057000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4284000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4284000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8341000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      8341000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8341000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      8341000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.041460                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.041460                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.082353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.082353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.056448                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.056448                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.056448                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.056448                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60552.238806                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60552.238806                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55636.363636                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55636.363636                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57923.611111                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 57923.611111                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57923.611111                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 57923.611111                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index f6427353ad842b60eec1db6ecc9a401e104e04f4..d96944a1ac05468a7222dd4e9fe01a9cfcc08660 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.000006                       # Nu
 sim_ticks                                     5615000                       # Number of ticks simulated
 final_tick                                    5615000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54091                       # Simulator instruction rate (inst/s)
-host_op_rate                                    97967                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               56419373                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 276792                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  70800                       # Simulator instruction rate (inst/s)
+host_op_rate                                   128226                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               73842503                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280580                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             54912                       # Number of bytes read from this memory
@@ -41,7 +41,7 @@ system.cpu.committedInsts                        5381                       # Nu
 system.cpu.committedOps                          9748                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  9655                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                         209                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         9655                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index 8f40b774d04d71dbac26198465f43643df4fb47a..db0163c4d7bc88299954d118b0db4a05fd3a3694 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.000122                       # Nu
 sim_ticks                                      121759                       # Number of ticks simulated
 final_tick                                     121759                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   7080                       # Simulator instruction rate (inst/s)
-host_op_rate                                    12826                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 160202                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  32232                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58383                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 729156                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 170120                       # Number of bytes of host memory used
-host_seconds                                     0.76                       # Real time elapsed on the host
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         7475                       # Number of cache demand hits
@@ -22,7 +22,7 @@ system.cpu.committedInsts                        5381                       # Nu
 system.cpu.committedOps                          9748                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  9655                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                         209                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         9655                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
index 84cd243cf9380f06ccb2ec39237724dc666619a4..496e32acaf02d9a7da8001711dc2b30589aff7fb 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28358000                       # Number of ticks simulated
 final_tick                                   28358000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  48918                       # Simulator instruction rate (inst/s)
-host_op_rate                                    88604                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              257715326                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 285372                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  90736                       # Simulator instruction rate (inst/s)
+host_op_rate                                   164316                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              477859669                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 289160                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
@@ -35,7 +35,7 @@ system.cpu.committedInsts                        5381                       # Nu
 system.cpu.committedOps                          9748                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  9655                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                           0                       # number of times a function call or return occured
+system.cpu.num_func_calls                         209                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
 system.cpu.num_int_insts                         9655                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions