frv.md: Add fr400_integer automaton.

        * config/frv/frv.md: Add fr400_integer automaton. Don't
        allow TYPE_MUL, TYPE_MACC, or TYPE_CUT to issue in parallel
        to TYPE_MACC.

From-SVN: r94272

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 51b273e0d9736a452ae4992ac1c367d59f6f854e..4255c8e48b2a4a864ce7d3c89c3c39299e21c101 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2005-01-26  Aldy Hernandez  <aldyh@redhat.com>
+
+       2004-11-11  Eric Christopher  <echristo@redhat.com>
+
+        * config/frv/frv.md: Add fr400_integer automaton. Don't
+        allow TYPE_MUL, TYPE_MACC, or TYPE_CUT to issue in parallel
+        to TYPE_MACC.
+
 2005-01-26  Steven Bosscher  <stevenb@suse.de>
 
        PR middle-end/16585

diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index bab77557273c06af7dceec5193f164685c6d55dc..0fc13e2a9e923a0d19b28a9740d59ac58d99cea5 100644 (file)
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -768,6 +768,9 @@
 ;; of memory unit collision in the same packet.  There's only one divide
 ;; unit too.
 
+(define_automaton "fr400_integer")
+(define_cpu_unit "fr400_mul" "fr400_integer")
+
 (define_insn_reservation "fr400_i1_int" 1
   (and (eq_attr "cpu" "fr400,fr405,fr450")
        (eq_attr "type" "int"))
@@ -788,18 +791,18 @@
 (define_insn_reservation "fr400_i1_mul" 3
   (and (eq_attr "cpu" "fr400,fr405")
        (eq_attr "type" "mul"))
-  "i0")
+  "i0 + fr400_mul")
 
 (define_insn_reservation "fr450_i1_mul" 2
   (and (eq_attr "cpu" "fr450")
        (eq_attr "type" "mul"))
-  "i0")
+  "i0 + fr400_mul")
 
 (define_bypass 1 "fr400_i1_macc" "fr400_i1_macc")
 (define_insn_reservation "fr400_i1_macc" 2
   (and (eq_attr "cpu" "fr405,fr450")
        (eq_attr "type" "macc"))
-  "i0|i1")
+  "(i0|i1) + fr400_mul")
 
 (define_insn_reservation "fr400_i1_scan" 1
   (and (eq_attr "cpu" "fr400,fr405,fr450")
@@ -809,7 +812,7 @@
 (define_insn_reservation "fr400_i1_cut" 2
   (and (eq_attr "cpu" "fr405,fr450")
        (eq_attr "type" "cut"))
-  "i0")
+  "i0 + fr400_mul")
 
 ;; 20 is for a write-after-write hazard.
 (define_insn_reservation "fr400_i1_div" 20