mips.c (override_options): Set MASK_BRANCHLIKELY in target_flags based on ISA...

2002-08-06  Chris Demetriou  <cgd@broadcom.com>

        * config/mips/mips.c (override_options): Set MASK_BRANCHLIKELY
        in target_flags based on ISA, if it was not set on the command
        line.  Warn if MASK_BRANCHLIKLEY is set but the ISA does not
        support Branch Likely instructions.
        * config/mips/mips.h (MASK_BRANCHLIKLEY): New macro.
        (TARGET_BRANCHLIKELY): Likewise.
        (TARGET_SWITCHES): Add -mbranch-likely and -mno-branch-likely.
        (GENERATE_BRANCHLIKELY): Use TARGET_BRANCHLIKELY rather than
        ISA_HAS_BRANCHLIKELY.
        (ISA_HAS_BRANCHLIKELY): Do not include MIPS16 check.
        * doc/invoke.texi: Document new MIPS -mbranch-likely and
        -mno-branch-likely options.

From-SVN: r56088

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d51638742a23fb8ca8780401bae9c0dc51f5078c..e02d1c6e4d84bd966fae9e2be5af2a7d2e753c94 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,18 @@
+2002-08-06  Chris Demetriou  <cgd@broadcom.com>
+
+       * config/mips/mips.c (override_options): Set MASK_BRANCHLIKELY
+       in target_flags based on ISA, if it was not set on the command
+       line.  Warn if MASK_BRANCHLIKLEY is set but the ISA does not
+       support Branch Likely instructions.
+       * config/mips/mips.h (MASK_BRANCHLIKLEY): New macro.
+       (TARGET_BRANCHLIKELY): Likewise.
+       (TARGET_SWITCHES): Add -mbranch-likely and -mno-branch-likely.
+       (GENERATE_BRANCHLIKELY): Use TARGET_BRANCHLIKELY rather than
+       ISA_HAS_BRANCHLIKELY.
+       (ISA_HAS_BRANCHLIKELY): Do not include MIPS16 check.
+       * doc/invoke.texi: Document new MIPS -mbranch-likely and
+       -mno-branch-likely options.
+
 2002-08-06  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
        * ip2k.c (ip2k_set_compare): Add missing iteration variable.

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 31cd0d04ba05bf7b31bd954ad7ab85aa17d1ee54..aa6be83c2067dba45dbd58ae82656bb68ee6e0f9 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -5177,6 +5177,31 @@ override_options ()
   if (mips_abi != ABI_32 && mips_abi != ABI_O64)
     flag_pcc_struct_return = 0;
 
+  if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
+    {
+      /* If neither -mbranch-likely nor -mno-branch-likely was given
+        on the command line, set MASK_BRANCHLIKELY based on the target
+        architecture.
+
+        By default, we enable use of Branch Likely instructions on
+        all architectures which support them except for MIPS32 and MIPS64
+        (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
+        implement them).
+
+        The MIPS32 and MIPS64 architecture specifications say "Software
+        is strongly encouraged to avoid use of Branch Likely
+        instructions, as they will be removed from a future revision
+        of the [MIPS32 and MIPS64] architecture."  Therefore, we do not
+        issue those instructions unless instructed to do so by
+        -mbranch-likely.  */
+      if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS64))
+       target_flags |= MASK_BRANCHLIKELY;
+      else
+       target_flags &= ~MASK_BRANCHLIKELY;
+    }
+  if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
+    warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
+
   /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined.  We need
      to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work.  */
   /* ??? -non_shared turns off pic code generation, but this is not

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 7db4f9e0b23433018c7e2de35638aba8367910a0..eaf68528911216da02fe3bca4d007bf9340cc951 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -232,6 +232,8 @@ extern void         sbss_section PARAMS ((void));
                                           consts in rodata */
 #define MASK_NO_FUSED_MADD 0x01000000   /* Don't generate floating point
                                           multiply-add operations.  */
+#define MASK_BRANCHLIKELY  0x02000000   /* Generate Branch Likely
+                                          instructions.  */
 
                                        /* Debug switches, not documented */
 #define MASK_DEBUG     0               /* unused */
@@ -322,6 +324,8 @@ extern void         sbss_section PARAMS ((void));
 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
 #define TARGET_CHECK_RANGE_DIV  (target_flags & MASK_CHECK_RANGE_DIV)
 
+#define TARGET_BRANCHLIKELY    (target_flags & MASK_BRANCHLIKELY)
+
 /* This is true if we must enable the assembly language file switching
    code.  */
 
@@ -608,6 +612,10 @@ extern void                sbss_section PARAMS ((void));
      N_("Trap on integer divide overflow")},                           \
   {"no-check-range-division",-MASK_CHECK_RANGE_DIV,                    \
      N_("Don't trap on integer divide overflow")},                     \
+  { "branch-likely",      MASK_BRANCHLIKELY,                           \
+      N_("Use Branch Likely instructions, overriding default for arch")}, \
+  { "no-branch-likely",  -MASK_BRANCHLIKELY,                           \
+      N_("Don't use Branch Likely instructions, overriding default for arch")}, \
   {"debug",              MASK_DEBUG,                                   \
      NULL},                                                            \
   {"debuga",             MASK_DEBUG_A,                                 \
@@ -741,7 +749,7 @@ extern void         sbss_section PARAMS ((void));
 /* This is meant to be redefined in the host dependent files.  */
 #define SUBTARGET_TARGET_OPTIONS
 
-#define GENERATE_BRANCHLIKELY   (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
+#define GENERATE_BRANCHLIKELY   (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
 
 /* Generate three-operand multiply instructions for SImode.  */
 #define GENERATE_MULT3_SI       ((TARGET_MIPS3900                       \
@@ -776,8 +784,7 @@ extern void         sbss_section PARAMS ((void));
 /* ISA has branch likely instructions (eg. mips2).  */
 /* Disable branchlikely for tx39 until compare rewrite.  They haven't
    been generated up to this point.  */
-#define ISA_HAS_BRANCHLIKELY   (!ISA_MIPS1                             \
-                                && !TARGET_MIPS16)
+#define ISA_HAS_BRANCHLIKELY   (!ISA_MIPS1)
 
 /* ISA has the conditional move instructions introduced in mips4.  */
 #define ISA_HAS_CONDMOVE        ((ISA_MIPS4                            \

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index a8c7da5ebe2fd3715753bb9b0275f5b89c265f7f..71beb9485c6deff38f55d97f2c5db207617cc579 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -477,7 +477,8 @@ in the following sections.
 -m4650  -msingle-float  -mmad @gol
 -mstats  -EL  -EB  -G @var{num}  -nocpp @gol
 -mabi=32  -mabi=n32  -mabi=64  -mabi=eabi @gol
--mfix7000  -mno-crt0 -mflush-func=@var{func} -mno-flush-func}
+-mfix7000  -mno-crt0 -mflush-func=@var{func} -mno-flush-func
+-mbranch-likely -mno-branch-likely}
 
 @emph{i386 and x86-64 Options}
 @gccoptlist{
@@ -7369,6 +7370,18 @@ memory range for which the cache is being flushed, the size of the
 memory range, and the number 3 (to flush both caches).  The default
 depends on the target gcc was configured for, but commonly is either
 @samp{_flush_func} or @samp{__cpu_flush}.
+
+@item -mbranch-likely
+@itemx -mno-branch-likely
+@opindex mbranch-likely
+@opindex mno-branch-likely
+Enable or disable use of Branch Likely instructions, regardless of the
+default for the selected architecture.  By default, Branch Likely
+instructions may be generated if they are supported by the selected
+architecture.  An exception is for the MIPS32 and MIPS64 architectures
+and processors which implement those architectures; for those, Branch
+Likely instructions will not be generated by default because the MIPS32
+and MIPS64 architectures specifically deprecate their use.
 @end table
 
 @node i386 and x86-64 Options