Reformat spi_flash_ctrl
authorAnton Blanchard <anton@linux.ibm.com>
Mon, 22 Mar 2021 00:01:10 +0000 (11:01 +1100)
committerAnton Blanchard <anton@ozlabs.org>
Mon, 22 Mar 2021 00:01:10 +0000 (11:01 +1100)
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
spi_flash_ctrl.vhdl

index e34a7c0398028a5bd103cd8b053a29ebd8552571..d45be902ed5a72859a9b2fce194f2441c537297c 100644 (file)
@@ -232,10 +232,10 @@ begin
             if rst = '1' then
                 wb_out.ack   <= '0';
                 wb_out.stall <= '0';
-               wb_stash.cyc <= '0';
-               wb_stash.stb <= '0';
-               wb_stash.sel <= (others => '0');
-               wb_stash.we <= '0';
+                wb_stash.cyc <= '0';
+                wb_stash.stb <= '0';
+                wb_stash.sel <= (others => '0');
+                wb_stash.we <= '0';
             else
                 -- Latch wb responses as well for 1 cycle. Stall is updated
                 -- below
@@ -348,17 +348,17 @@ begin
     auto_sync: process(clk)
     begin
         if rising_edge(clk) then
-           if rst = '1' then
+            if rst = '1' then
                 auto_last_addr <= (others => '0');
-               auto_state <= AUTO_BOOT;
-           else
+                auto_state <= AUTO_BOOT;
+            else
                 auto_state <= auto_next;
                 auto_cnt   <= auto_cnt_next;
                 auto_data  <= auto_data_next;
                 if auto_latch_adr = '1' then
                     auto_last_addr <= auto_lad_next;
                 end if;
-           end if;
+            end if;
         end if;
     end process;