ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c49b29ab3f31e19d4a8c738d82de37e15b173ea8..a98bc30d97b2dac5775755a94b58f49e4b23faf3 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -127,7 +127,10 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
        assign O = I0 ? s1[1] : s1[0];
 endmodule
 
-(* abc_box_id = 21, whitebox *)
+(* abc_box_id = 21 *)
+`ifdef ABC_MODEL
+    (* whitebox *)
+`endif
 module SB_CARRY (output CO, input I0, I1, CI);
        assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
@@ -135,11 +138,11 @@ endmodule
 // Positive Edge SiliconBlue FF Cells
 
 (* abc_box_id = 1, abc_flop *)
-`ifdef ABC_FLOPS
+`ifdef ABC_MODEL
     (* whitebox *)
 `endif
 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
-`ifndef ABC_FLOPS
+`ifndef ABC_MODEL
        always @(posedge C)
                Q <= D;
 `else

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d5d3547013244c0303d8861d9f71065651b6e42e..7cedecdffb269c9f188e4837bbfaf91dfa633376 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
        {
                if (check_label("begin"))
                {
-                       run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
+                       run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v");
                        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
                        run("proc");
                }