/* register assignment: */
int ir3_block_ra(struct ir3_block *block, enum shader_t type,
bool half_precision, bool frag_coord, bool frag_face,
- bool *has_samp);
+ bool *has_samp, int *max_bary);
#ifndef ARRAY_SIZE
# define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
struct ir3_block *block;
struct ir3_instruction **inputs;
unsigned i, j, actual_in;
- int ret = 0;
+ int ret = 0, max_bary;
assert(!so->ir);
}
ret = ir3_block_ra(block, so->type, key.half_precision,
- so->frag_coord, so->frag_face, &so->has_samp);
+ so->frag_coord, so->frag_face, &so->has_samp, &max_bary);
if (ret) {
DBG("RA failed!");
goto out;
*/
if (so->type == SHADER_VERTEX)
so->total_in = actual_in;
+ else
+ so->total_in = align(max_bary + 1, 4);
out:
if (ret) {
bool frag_face;
bool has_samp;
int cnt;
+ int max_bary;
bool error;
};
if (is_meta(n))
continue;
+ if (is_input(n)) {
+ struct ir3_register *inloc = n->regs[1];
+ assert(inloc->flags & IR3_REG_IMMED);
+ ctx->max_bary = MAX2(ctx->max_bary, inloc->iim_val);
+ }
+
for (i = 1; i < n->regs_count; i++) {
reg = n->regs[i];
int ir3_block_ra(struct ir3_block *block, enum shader_t type,
bool half_precision, bool frag_coord, bool frag_face,
- bool *has_samp)
+ bool *has_samp, int *max_bary)
{
struct ir3_ra_ctx ctx = {
.block = block,
.half_precision = half_precision,
.frag_coord = frag_coord,
.frag_face = frag_face,
+ .max_bary = -1,
};
int ret;
ir3_clear_mark(block->shader);
ret = block_ra(&ctx, block);
*has_samp = ctx.has_samp;
+ *max_bary = ctx.max_bary;
return ret;
}
unsigned i;
for (i = 0; i < v->inputs_count; i++) {
if (v->inputs[i].compmask) {
- uint32_t regid = (v->inputs[i].regid + 3) >> 2;
+ int32_t regid = (v->inputs[i].regid + 3) >> 2;
v->info.max_reg = MAX2(v->info.max_reg, regid);
}
}
for (i = 0; i < v->outputs_count; i++) {
- uint32_t regid = (v->outputs[i].regid + 3) >> 2;
+ int32_t regid = (v->outputs[i].regid + 3) >> 2;
v->info.max_reg = MAX2(v->info.max_reg, regid);
}
}