2002-02-27 Chris Demetriou <cgd@broadcom.com>

        * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
        add a comma) so that it more closely match the MIPS ISA
        documentation opcode partitioning.
        (PREF): Put useful names on opcode fields, and include
        instruction-printing string.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 9083040d85427f188fde08a34387bcb6f604e9e8..4789ba900abf0a1ab9d7396ee9cb6cad28dcc962 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,11 @@
+2002-02-27  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
+       add a comma) so that it more closely match the MIPS ISA
+       documentation opcode partitioning.
+       (PREF): Put useful names on opcode fields, and include
+       instruction-printing string.
+
 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 
        * mips.igen (check_u64): New function which in the future will

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 72626d201cbcafd78efdf013031c6d99b9a0f459..d19ac97371ebdf927b66dcf58832607db129acdb 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -2083,7 +2083,8 @@
 }
 
 
-110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
+110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
+"pref <HINT>, <OFFSET>(r<BASE>)"
 *mipsIV:
 *mipsV:
 *vr5000:
@@ -3974,7 +3975,7 @@
 }
 
 
-010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
+010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
 "prefx <HINT>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *mipsV: